library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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entity opcode_fetch is
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entity opcode_fetch is
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Port( CLK_I : in std_logic;
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Port( CLK_I : in std_logic;
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T2 : in std_logic;
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T2 : in std_logic;
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CLR : in std_logic;
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CLR : in std_logic;
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CE : in std_logic;
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CE : in std_logic;
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PC_OP : in std_logic_vector( 2 downto 0);
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PC_OP : in std_logic_vector( 2 downto 0);
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JDATA : in std_logic_vector(15 downto 0);
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JDATA : in std_logic_vector(15 downto 0);
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RR : in std_logic_vector(15 downto 0);
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RR : in std_logic_vector(15 downto 0);
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RDATA : in std_logic_vector( 7 downto 0);
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RDATA : in std_logic_vector( 7 downto 0);
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PC : out std_logic_vector(15 downto 0)
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PC : out std_logic_vector(15 downto 0)
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);
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);
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end opcode_fetch;
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end opcode_fetch;
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architecture Behavioral of opcode_fetch is
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architecture Behavioral of opcode_fetch is
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signal LPC : std_logic_vector(15 downto 0);
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signal LPC : std_logic_vector(15 downto 0);
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signal LRET : std_logic_vector( 7 downto 0);
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signal LRET : std_logic_vector( 7 downto 0);
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begin
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begin
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PC <= LPC;
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PC <= LPC;
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process(CLK_I, CLR)
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process(CLK_I, CLR)
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begin
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begin
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if (CLR = '1') then
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if (CLR = '1') then
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LPC <= X"0000";
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LPC <= X"0000";
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elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
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elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
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case PC_OP is
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case PC_OP is
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when PC_NEXT => LPC <= LPC + 1; -- next address
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when PC_NEXT => LPC <= LPC + 1; -- next address
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when PC_JMP => LPC <= JDATA; -- jump address
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when PC_JMP => LPC <= JDATA; -- jump address
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when PC_RETL => LRET <= RDATA; -- return address L
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when PC_RETL => LRET <= RDATA; -- return address L
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LPC <= LPC + 1;
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LPC <= LPC + 1;
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when PC_RETH => LPC <= RDATA & LRET; -- return address H
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when PC_RETH => LPC <= RDATA & LRET; -- return address H
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when PC_JPRR => LPC <= RR;
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when PC_JPRR => LPC <= RR;
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when PC_WAIT =>
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when PC_WAIT =>
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when others => LPC <= X"0008"; -- interrupt
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when others => LPC <= X"0008"; -- interrupt
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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