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-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
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-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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ENTITY testbench IS
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ENTITY testbench IS
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END testbench;
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END testbench;
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ARCHITECTURE behavior OF testbench IS
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ARCHITECTURE behavior OF testbench IS
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COMPONENT cpu_engine
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COMPONENT cpu_engine
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PORT(
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PORT(
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clk_i : IN std_logic;
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clk_i : IN std_logic;
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dat_i : IN std_logic_vector(7 downto 0);
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dat_i : IN std_logic_vector(7 downto 0);
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rst_i : IN std_logic;
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rst_i : IN std_logic;
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ack_i : IN std_logic;
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ack_i : IN std_logic;
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int : IN std_logic;
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int : IN std_logic;
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dat_o : OUT std_logic_vector(7 downto 0);
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dat_o : OUT std_logic_vector(7 downto 0);
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adr_o : OUT std_logic_vector(15 downto 0);
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adr_o : OUT std_logic_vector(15 downto 0);
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cyc_o : OUT std_logic;
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cyc_o : OUT std_logic;
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stb_o : OUT std_logic;
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stb_o : OUT std_logic;
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tga_o : OUT std_logic_vector(0 to 0);
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tga_o : OUT std_logic_vector(0 to 0);
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we_o : OUT std_logic;
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we_o : OUT std_logic;
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halt : OUT std_logic;
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halt : OUT std_logic;
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q_pc : OUT std_logic_vector(15 downto 0);
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q_pc : OUT std_logic_vector(15 downto 0);
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q_opc : OUT std_logic_vector(7 downto 0);
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q_opc : OUT std_logic_vector(7 downto 0);
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q_cat : OUT op_category;
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q_cat : OUT op_category;
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q_imm : OUT std_logic_vector(15 downto 0);
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q_imm : OUT std_logic_vector(15 downto 0);
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q_cyc : OUT cycle;
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q_cyc : OUT cycle;
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q_sx : OUT std_logic_vector(1 downto 0);
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q_sx : OUT std_logic_vector(1 downto 0);
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q_sy : OUT std_logic_vector(3 downto 0);
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q_sy : OUT std_logic_vector(3 downto 0);
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q_op : OUT std_logic_vector(4 downto 0);
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q_op : OUT std_logic_vector(4 downto 0);
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q_sa : OUT std_logic_vector(4 downto 0);
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q_sa : OUT std_logic_vector(4 downto 0);
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q_smq : OUT std_logic;
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q_smq : OUT std_logic;
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q_we_rr : OUT std_logic;
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q_we_rr : OUT std_logic;
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q_we_ll : OUT std_logic;
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q_we_ll : OUT std_logic;
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q_we_sp : OUT SP_OP;
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q_we_sp : OUT SP_OP;
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q_rr : OUT std_logic_vector(15 downto 0);
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q_rr : OUT std_logic_vector(15 downto 0);
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q_ll : OUT std_logic_vector(15 downto 0);
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q_ll : OUT std_logic_vector(15 downto 0);
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q_sp : OUT std_logic_vector(15 downto 0)
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q_sp : OUT std_logic_vector(15 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal CLK_I : std_logic;
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signal CLK_I : std_logic;
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signal DAT_I : std_logic_vector( 7 downto 0);
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signal DAT_I : std_logic_vector( 7 downto 0);
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signal DAT_O : std_logic_vector( 7 downto 0);
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signal DAT_O : std_logic_vector( 7 downto 0);
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signal RST_I : std_logic;
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signal RST_I : std_logic;
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signal ACK_I : std_logic;
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signal ACK_I : std_logic;
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signal ADR_O : std_logic_vector(15 downto 0);
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signal ADR_O : std_logic_vector(15 downto 0);
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signal CYC_O : std_logic;
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signal CYC_O : std_logic;
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signal STB_O : std_logic;
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signal STB_O : std_logic;
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signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
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signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
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signal WE_O : std_logic;
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signal WE_O : std_logic;
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signal INT : std_logic;
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signal INT : std_logic;
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signal HALT : std_logic;
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signal HALT : std_logic;
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-- debug signals
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-- debug signals
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--
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--
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signal Q_PC : std_logic_vector(15 downto 0);
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signal Q_PC : std_logic_vector(15 downto 0);
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signal Q_OPC : std_logic_vector( 7 downto 0);
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signal Q_OPC : std_logic_vector( 7 downto 0);
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signal Q_CAT : op_category;
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signal Q_CAT : op_category;
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signal Q_IMM : std_logic_vector(15 downto 0);
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signal Q_IMM : std_logic_vector(15 downto 0);
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signal Q_CYC : cycle;
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signal Q_CYC : cycle;
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-- select signals
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-- select signals
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signal Q_SX : std_logic_vector(1 downto 0);
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signal Q_SX : std_logic_vector(1 downto 0);
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signal Q_SY : std_logic_vector(3 downto 0);
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signal Q_SY : std_logic_vector(3 downto 0);
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signal Q_OP : std_logic_vector(4 downto 0);
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signal Q_OP : std_logic_vector(4 downto 0);
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signal Q_SA : std_logic_vector(4 downto 0);
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signal Q_SA : std_logic_vector(4 downto 0);
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signal Q_SMQ : std_logic;
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signal Q_SMQ : std_logic;
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-- write enable/select signal
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-- write enable/select signal
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signal Q_WE_RR : std_logic;
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signal Q_WE_RR : std_logic;
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signal Q_WE_LL : std_logic;
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signal Q_WE_LL : std_logic;
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signal Q_WE_SP : SP_OP;
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signal Q_WE_SP : SP_OP;
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signal Q_RR : std_logic_vector(15 downto 0);
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signal Q_RR : std_logic_vector(15 downto 0);
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signal Q_LL : std_logic_vector(15 downto 0);
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signal Q_LL : std_logic_vector(15 downto 0);
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signal Q_SP : std_logic_vector(15 downto 0);
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signal Q_SP : std_logic_vector(15 downto 0);
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signal clk_counter : INTEGER := 0;
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signal clk_counter : INTEGER := 0;
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BEGIN
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BEGIN
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uut: cpu_engine
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uut: cpu_engine
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PORT MAP(
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PORT MAP(
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clk_i => clk_i,
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clk_i => clk_i,
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dat_i => dat_i,
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dat_i => dat_i,
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dat_o => dat_o,
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dat_o => dat_o,
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rst_i => rst_i,
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rst_i => rst_i,
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ack_i => ack_i,
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ack_i => ack_i,
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adr_o => adr_o,
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adr_o => adr_o,
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cyc_o => cyc_o,
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cyc_o => cyc_o,
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stb_o => stb_o,
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stb_o => stb_o,
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tga_o => tga_o,
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tga_o => tga_o,
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we_o => we_o,
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we_o => we_o,
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int => int,
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int => int,
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halt => halt,
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halt => halt,
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q_pc => q_pc,
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q_pc => q_pc,
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q_opc => q_opc,
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q_opc => q_opc,
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q_cat => q_cat,
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q_cat => q_cat,
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q_imm => q_imm,
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q_imm => q_imm,
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q_cyc => q_cyc,
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q_cyc => q_cyc,
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q_sx => q_sx,
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q_sx => q_sx,
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q_sy => q_sy,
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q_sy => q_sy,
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q_op => q_op,
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q_op => q_op,
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q_sa => q_sa,
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q_sa => q_sa,
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q_smq => q_smq,
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q_smq => q_smq,
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q_we_rr => q_we_rr,
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q_we_rr => q_we_rr,
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q_we_ll => q_we_ll,
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q_we_ll => q_we_ll,
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q_we_sp => q_we_sp,
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q_we_sp => q_we_sp,
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q_rr => q_rr,
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q_rr => q_rr,
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q_ll => q_ll,
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q_ll => q_ll,
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q_sp => q_sp
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q_sp => q_sp
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);
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);
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ack_i <= stb_o;
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ack_i <= stb_o;
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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PROCESS -- clock process for CLK_I,
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PROCESS -- clock process for CLK_I,
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BEGIN
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BEGIN
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CLOCK_LOOP : LOOP
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CLOCK_LOOP : LOOP
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CLK_I <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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CLK_I <= transport '1';
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CLK_I <= transport '1';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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WAIT FOR 11 ns;
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WAIT FOR 11 ns;
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CLK_I <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 12 ns;
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WAIT FOR 12 ns;
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END LOOP CLOCK_LOOP;
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END LOOP CLOCK_LOOP;
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END PROCESS;
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END PROCESS;
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PROCESS(CLK_I)
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PROCESS(CLK_I)
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BEGIN
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BEGIN
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (Q_CYC = M1) then
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if (Q_CYC = M1) then
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CLK_COUNTER <= CLK_COUNTER + 1;
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CLK_COUNTER <= CLK_COUNTER + 1;
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end if;
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end if;
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if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
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if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
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else DAT_I <= X"01"; -- control
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else DAT_I <= X"01"; -- control
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end if;
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end if;
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case CLK_COUNTER is
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case CLK_COUNTER is
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when 0 => RST_I <= '1'; INT <= '0';
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when 0 => RST_I <= '1'; INT <= '0';
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when 1 => RST_I <= '0';
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when 1 => RST_I <= '0';
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-- when 20 => INT <= '1';
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-- when 20 => INT <= '1';
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when 1000 => CLK_COUNTER <= 0;
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when 1000 => CLK_COUNTER <= 0;
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ASSERT (FALSE) REPORT
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ASSERT (FALSE) REPORT
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"simulation done (no error)"
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"simulation done (no error)"
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SEVERITY FAILURE;
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SEVERITY FAILURE;
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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END PROCESS;
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END PROCESS;
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END;
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END;
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