library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity uart_baudgen is
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entity uart_baudgen is
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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RST_I : in std_logic;
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RST_I : in std_logic;
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RD : in std_logic;
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RD : in std_logic;
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WR : in std_logic;
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WR : in std_logic;
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TX_DATA : in std_logic_vector(7 downto 0);
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TX_DATA : in std_logic_vector(7 downto 0);
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TX_SEROUT : out std_logic;
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TX_SEROUT : out std_logic;
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RX_SERIN : in std_logic;
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RX_SERIN : in std_logic;
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RX_DATA : out std_logic_vector(7 downto 0);
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RX_DATA : out std_logic_vector(7 downto 0);
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RX_READY : out std_logic;
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RX_READY : out std_logic;
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TX_BUSY : out std_logic
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TX_BUSY : out std_logic
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);
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);
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end uart_baudgen;
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end uart_baudgen;
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architecture Behavioral of uart_baudgen is
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architecture Behavioral of uart_baudgen is
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COMPONENT baudgen
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COMPONENT baudgen
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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RST_I : IN std_logic;
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RST_I : IN std_logic;
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CE_16 : OUT std_logic
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CE_16 : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT uart
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COMPONENT uart
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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RST_I : in std_logic;
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RST_I : in std_logic;
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CE_16 : in std_logic;
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CE_16 : in std_logic;
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TX_DATA : in std_logic_vector(7 downto 0);
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TX_DATA : in std_logic_vector(7 downto 0);
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TX_FLAG : in std_logic;
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TX_FLAG : in std_logic;
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TX_SEROUT : out std_logic;
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TX_SEROUT : out std_logic;
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TX_FLAGQ : out std_logic;
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TX_FLAGQ : out std_logic;
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RX_SERIN : in std_logic;
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RX_SERIN : in std_logic;
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RX_DATA : out std_logic_vector(7 downto 0);
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RX_DATA : out std_logic_vector(7 downto 0);
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RX_FLAG : out std_logic
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RX_FLAG : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal CE_16 : std_logic;
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signal CE_16 : std_logic;
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signal RX_FLAG : std_logic;
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signal RX_FLAG : std_logic;
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signal RX_OLD_FLAG : std_logic;
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signal RX_OLD_FLAG : std_logic;
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signal TX_FLAG : std_logic;
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signal TX_FLAG : std_logic;
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signal TX_FLAGQ : std_logic;
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signal TX_FLAGQ : std_logic;
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signal LTX_DATA : std_logic_vector(7 downto 0);
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signal LTX_DATA : std_logic_vector(7 downto 0);
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signal LRX_READY : std_logic;
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signal LRX_READY : std_logic;
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begin
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begin
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RX_READY <= LRX_READY;
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RX_READY <= LRX_READY;
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TX_BUSY <= TX_FLAG xor TX_FLAGQ;
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TX_BUSY <= TX_FLAG xor TX_FLAGQ;
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baud: baudgen
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baud: baudgen
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GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
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GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
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PORT MAP(
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PORT MAP(
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CLK_I => CLK_I,
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CLK_I => CLK_I,
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RST_I => RST_I,
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RST_I => RST_I,
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CE_16 => CE_16
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CE_16 => CE_16
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);
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);
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urt: uart
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urt: uart
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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RST_I => RST_I,
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RST_I => RST_I,
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CE_16 => CE_16,
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CE_16 => CE_16,
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TX_DATA => LTX_DATA,
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TX_DATA => LTX_DATA,
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TX_FLAG => TX_FLAG,
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TX_FLAG => TX_FLAG,
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TX_SEROUT => TX_SEROUT,
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TX_SEROUT => TX_SEROUT,
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TX_FLAGQ => TX_FLAGQ,
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TX_FLAGQ => TX_FLAGQ,
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RX_SERIN => RX_SERIN,
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RX_SERIN => RX_SERIN,
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RX_DATA => RX_DATA,
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RX_DATA => RX_DATA,
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RX_FLAG => RX_FLAG
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RX_FLAG => RX_FLAG
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);
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);
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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if (RST_I = '1') then
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TX_FLAG <= '0';
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TX_FLAG <= '0';
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LTX_DATA <= X"33";
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LTX_DATA <= X"33";
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else
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else
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if (RD = '1') then -- read Rx data
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if (RD = '1') then -- read Rx data
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LRX_READY <= '0';
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LRX_READY <= '0';
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end if;
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end if;
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if (WR = '1') then -- write Tx data
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if (WR = '1') then -- write Tx data
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TX_FLAG <= not TX_FLAG;
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TX_FLAG <= not TX_FLAG;
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LTX_DATA <= TX_DATA;
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LTX_DATA <= TX_DATA;
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end if;
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end if;
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if (RX_FLAG /= RX_OLD_FLAG) then
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if (RX_FLAG /= RX_OLD_FLAG) then
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LRX_READY <= '1';
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LRX_READY <= '1';
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end if;
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end if;
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RX_OLD_FLAG <= RX_FLAG;
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RX_OLD_FLAG <= RX_FLAG;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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