library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity UART_TX is
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entity UART_TX is
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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RST_I : in std_logic; -- RESET
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RST_I : in std_logic; -- RESET
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CE_16 : in std_logic; -- BUAD rate clock
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CE_16 : in std_logic; -- BUAD rate clock
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DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
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DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
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DATA_FLAG : in std_logic; -- toggle to send data
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DATA_FLAG : in std_logic; -- toggle to send data
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SER_OUT : out std_logic; -- Serial output line
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SER_OUT : out std_logic; -- Serial output line
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DATA_FLAGQ : out std_logic -- Transmitting Flag
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DATA_FLAGQ : out std_logic -- Transmitting Flag
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);
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);
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end UART_TX;
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end UART_TX;
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architecture TX_UART_arch of UART_TX is
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architecture TX_UART_arch of UART_TX is
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signal BUF : std_logic_vector(7 downto 0);
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signal BUF : std_logic_vector(7 downto 0);
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signal TODO : integer range 0 to 9; -- bits to send
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signal TODO : integer range 0 to 9; -- bits to send
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signal FLAGQ : std_logic;
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signal FLAGQ : std_logic;
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signal CE_1 : std_logic;
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signal CE_1 : std_logic;
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signal C16 : std_logic_vector(3 downto 0);
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signal C16 : std_logic_vector(3 downto 0);
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begin
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begin
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DATA_FLAGQ <= FLAGQ;
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DATA_FLAGQ <= FLAGQ;
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-- generate a CE_1 every 16 CE_16...
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-- generate a CE_1 every 16 CE_16...
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--
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--
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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CE_1 <= '0';
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CE_1 <= '0';
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if (RST_I = '1') then
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if (RST_I = '1') then
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C16 <= "0000";
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C16 <= "0000";
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elsif (CE_16 = '1') then
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elsif (CE_16 = '1') then
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if (C16 = "1111") then
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if (C16 = "1111") then
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CE_1 <= '1';
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CE_1 <= '1';
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end if;
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end if;
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C16 <= C16 + "0001";
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C16 <= C16 + "0001";
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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if (RST_I = '1') then
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SER_OUT <= '1';
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SER_OUT <= '1';
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BUF <= "11111111";
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BUF <= "11111111";
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TODO <= 0;
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TODO <= 0;
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FLAGQ <= DATA_FLAG; -- idle
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FLAGQ <= DATA_FLAG; -- idle
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elsif (CE_1 = '1') then
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elsif (CE_1 = '1') then
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if (TODO > 0) then -- transmitting
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if (TODO > 0) then -- transmitting
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SER_OUT <= BUF(0); -- next bit
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SER_OUT <= BUF(0); -- next bit
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BUF <= '1' & BUF(7 downto 1);
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BUF <= '1' & BUF(7 downto 1);
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if (TODO = 1) then
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if (TODO = 1) then
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FLAGQ <= DATA_FLAG;
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FLAGQ <= DATA_FLAG;
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end if;
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end if;
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TODO <= TODO - 1;
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TODO <= TODO - 1;
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elsif (FLAGQ /= DATA_FLAG) then -- new byte
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elsif (FLAGQ /= DATA_FLAG) then -- new byte
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SER_OUT <= '0'; -- start bit
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SER_OUT <= '0'; -- start bit
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TODO <= 9;
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TODO <= 9;
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BUF <= DATA;
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BUF <= DATA;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end TX_UART_arch;
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end TX_UART_arch;
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