//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_registers.v ////
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//// can_registers.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// from Bosch. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2003/07/07 11:21:37 mohor
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// Revision 1.28 2003/07/07 11:21:37 mohor
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// Little fixes (to fix warnings).
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// Little fixes (to fix warnings).
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//
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//
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// Revision 1.27 2003/06/22 09:43:03 mohor
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// Revision 1.27 2003/06/22 09:43:03 mohor
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// synthesi full_case parallel_case fixed.
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// synthesi full_case parallel_case fixed.
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//
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//
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// Revision 1.26 2003/06/22 01:33:14 mohor
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// Revision 1.26 2003/06/22 01:33:14 mohor
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// clkout is clk/2 after the reset.
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// clkout is clk/2 after the reset.
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//
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//
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// Revision 1.25 2003/06/21 12:16:30 mohor
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// Revision 1.25 2003/06/21 12:16:30 mohor
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// paralel_case and full_case compiler directives added to case statements.
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// paralel_case and full_case compiler directives added to case statements.
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//
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//
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// Revision 1.24 2003/06/09 11:22:54 mohor
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// Revision 1.24 2003/06/09 11:22:54 mohor
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// data_out is already registered in the can_top.v file.
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// data_out is already registered in the can_top.v file.
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//
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//
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// Revision 1.23 2003/04/15 15:31:24 mohor
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// Revision 1.23 2003/04/15 15:31:24 mohor
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// Some features are supported in extended mode only (listen_only_mode...).
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// Some features are supported in extended mode only (listen_only_mode...).
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//
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//
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// Revision 1.22 2003/03/20 16:58:50 mohor
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// Revision 1.22 2003/03/20 16:58:50 mohor
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// unix.
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// unix.
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//
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//
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// Revision 1.20 2003/03/11 16:31:05 mohor
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// Revision 1.20 2003/03/11 16:31:05 mohor
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// Mux used for clkout to avoid "gated clocks warning".
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// Mux used for clkout to avoid "gated clocks warning".
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//
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//
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// Revision 1.19 2003/03/10 17:34:25 mohor
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// Revision 1.19 2003/03/10 17:34:25 mohor
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// Doubled declarations removed.
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// Doubled declarations removed.
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//
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//
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// Revision 1.18 2003/03/01 22:52:11 mohor
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// Revision 1.18 2003/03/01 22:52:11 mohor
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// Data is latched on read.
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// Data is latched on read.
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//
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//
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// Revision 1.17 2003/02/19 15:09:02 mohor
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// Revision 1.17 2003/02/19 15:09:02 mohor
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// Incomplete sensitivity list fixed.
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// Incomplete sensitivity list fixed.
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//
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//
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// Revision 1.16 2003/02/19 14:44:03 mohor
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// Revision 1.16 2003/02/19 14:44:03 mohor
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// CAN core finished. Host interface added. Registers finished.
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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// Synchronization to the wishbone finished.
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//
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//
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// Revision 1.15 2003/02/18 00:10:15 mohor
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// Revision 1.15 2003/02/18 00:10:15 mohor
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// Most of the registers added. Registers "arbitration lost capture", "error code
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// Most of the registers added. Registers "arbitration lost capture", "error code
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// capture" + few more still need to be added.
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// capture" + few more still need to be added.
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//
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//
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// Revision 1.14 2003/02/14 20:17:01 mohor
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// Revision 1.14 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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// Several registers added. Not finished, yet.
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//
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//
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// Revision 1.13 2003/02/12 14:25:30 mohor
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// Revision 1.13 2003/02/12 14:25:30 mohor
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// abort_tx added.
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// abort_tx added.
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//
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//
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// Revision 1.12 2003/02/11 00:56:06 mohor
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// Revision 1.12 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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// Wishbone interface added.
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//
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//
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// Revision 1.11 2003/02/09 02:24:33 mohor
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// Revision 1.11 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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// still need to be fixed.
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//
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//
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// Revision 1.10 2003/01/31 01:13:38 mohor
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// Revision 1.10 2003/01/31 01:13:38 mohor
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// backup.
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// backup.
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//
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//
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// Revision 1.9 2003/01/15 13:16:48 mohor
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// Revision 1.9 2003/01/15 13:16:48 mohor
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// When a frame with "remote request" is received, no data is stored
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// When a frame with "remote request" is received, no data is stored
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// to fifo, just the frame information (identifier, ...). Data length
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// to fifo, just the frame information (identifier, ...). Data length
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// that is stored is the received data length and not the actual data
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// that is stored is the received data length and not the actual data
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// length that is stored to fifo.
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// length that is stored to fifo.
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//
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//
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// Revision 1.8 2003/01/14 17:25:09 mohor
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// Revision 1.8 2003/01/14 17:25:09 mohor
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// Addresses corrected to decimal values (previously hex).
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// Addresses corrected to decimal values (previously hex).
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//
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//
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// Revision 1.7 2003/01/14 12:19:35 mohor
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// Revision 1.7 2003/01/14 12:19:35 mohor
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// rx_fifo is now working.
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// rx_fifo is now working.
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//
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//
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// Revision 1.6 2003/01/10 17:51:34 mohor
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// Revision 1.6 2003/01/10 17:51:34 mohor
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// Temporary version (backup).
|
// Temporary version (backup).
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//
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//
|
// Revision 1.5 2003/01/09 14:46:58 mohor
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// Revision 1.5 2003/01/09 14:46:58 mohor
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// Temporary files (backup).
|
// Temporary files (backup).
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//
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//
|
// Revision 1.4 2003/01/08 02:10:55 mohor
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// Revision 1.4 2003/01/08 02:10:55 mohor
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// Acceptance filter added.
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// Acceptance filter added.
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//
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//
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// Revision 1.3 2002/12/27 00:12:52 mohor
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// Revision 1.3 2002/12/27 00:12:52 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
|
// Header changed, testbench improved to send a frame (crc still missing).
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//
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//
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// Revision 1.2 2002/12/26 16:00:34 mohor
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// Revision 1.2 2002/12/26 16:00:34 mohor
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// Testbench define file added. Clock divider register added.
|
// Testbench define file added. Clock divider register added.
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//
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//
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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// Initial
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//
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//
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//
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//
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//
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//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
|
`include "can_defines.v"
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`include "can_defines.v"
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|
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module can_registers
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module can_registers
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(
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(
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clk,
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clk,
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rst,
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rst,
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cs,
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cs,
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we,
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we,
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addr,
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addr,
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data_in,
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data_in,
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data_out,
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data_out,
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irq,
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irq,
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|
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sample_point,
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sample_point,
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transmitting,
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transmitting,
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set_reset_mode,
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set_reset_mode,
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node_bus_off,
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node_bus_off,
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error_status,
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error_status,
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rx_err_cnt,
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rx_err_cnt,
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tx_err_cnt,
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tx_err_cnt,
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transmit_status,
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transmit_status,
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receive_status,
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receive_status,
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tx_successful,
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tx_successful,
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need_to_tx,
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need_to_tx,
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overrun,
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overrun,
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info_empty,
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info_empty,
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set_bus_error_irq,
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set_bus_error_irq,
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set_arbitration_lost_irq,
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set_arbitration_lost_irq,
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arbitration_lost_capture,
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arbitration_lost_capture,
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node_error_passive,
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node_error_passive,
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node_error_active,
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node_error_active,
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rx_message_counter,
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rx_message_counter,
|
|
|
|
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/* Mode register */
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/* Mode register */
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reset_mode,
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reset_mode,
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listen_only_mode,
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listen_only_mode,
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acceptance_filter_mode,
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acceptance_filter_mode,
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self_test_mode,
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self_test_mode,
|
|
|
|
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/* Command register */
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/* Command register */
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clear_data_overrun,
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clear_data_overrun,
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release_buffer,
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release_buffer,
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abort_tx,
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abort_tx,
|
tx_request,
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tx_request,
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self_rx_request,
|
self_rx_request,
|
single_shot_transmission,
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single_shot_transmission,
|
tx_state,
|
tx_state,
|
tx_state_q,
|
tx_state_q,
|
|
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/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
read_arbitration_lost_capture_reg,
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read_arbitration_lost_capture_reg,
|
|
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/* Error Code Capture Register */
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/* Error Code Capture Register */
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read_error_code_capture_reg,
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read_error_code_capture_reg,
|
error_capture_code,
|
error_capture_code,
|
|
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/* Bus Timing 0 register */
|
/* Bus Timing 0 register */
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baud_r_presc,
|
baud_r_presc,
|
sync_jump_width,
|
sync_jump_width,
|
|
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/* Bus Timing 1 register */
|
/* Bus Timing 1 register */
|
time_segment1,
|
time_segment1,
|
time_segment2,
|
time_segment2,
|
triple_sampling,
|
triple_sampling,
|
|
|
/* Error Warning Limit register */
|
/* Error Warning Limit register */
|
error_warning_limit,
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error_warning_limit,
|
|
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/* Rx Error Counter register */
|
/* Rx Error Counter register */
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we_rx_err_cnt,
|
we_rx_err_cnt,
|
|
|
/* Tx Error Counter register */
|
/* Tx Error Counter register */
|
we_tx_err_cnt,
|
we_tx_err_cnt,
|
|
|
/* Clock Divider register */
|
/* Clock Divider register */
|
extended_mode,
|
extended_mode,
|
clkout,
|
clkout,
|
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
acceptance_code_0,
|
acceptance_code_0,
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
acceptance_mask_0,
|
acceptance_mask_0,
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
acceptance_code_1,
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acceptance_code_1,
|
acceptance_code_2,
|
acceptance_code_2,
|
acceptance_code_3,
|
acceptance_code_3,
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
acceptance_mask_1,
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acceptance_mask_1,
|
acceptance_mask_2,
|
acceptance_mask_2,
|
acceptance_mask_3,
|
acceptance_mask_3,
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
tx_data_0,
|
tx_data_0,
|
tx_data_1,
|
tx_data_1,
|
tx_data_2,
|
tx_data_2,
|
tx_data_3,
|
tx_data_3,
|
tx_data_4,
|
tx_data_4,
|
tx_data_5,
|
tx_data_5,
|
tx_data_6,
|
tx_data_6,
|
tx_data_7,
|
tx_data_7,
|
tx_data_8,
|
tx_data_8,
|
tx_data_9,
|
tx_data_9,
|
tx_data_10,
|
tx_data_10,
|
tx_data_11,
|
tx_data_11,
|
tx_data_12
|
tx_data_12
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
|
|
|
|
|
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input cs;
|
input cs;
|
input we;
|
input we;
|
input [7:0] addr;
|
input [7:0] addr;
|
input [7:0] data_in;
|
input [7:0] data_in;
|
|
|
output [7:0] data_out;
|
output [7:0] data_out;
|
reg [7:0] data_out;
|
reg [7:0] data_out;
|
|
|
output irq;
|
output irq;
|
|
|
input sample_point;
|
input sample_point;
|
input transmitting;
|
input transmitting;
|
input set_reset_mode;
|
input set_reset_mode;
|
input node_bus_off;
|
input node_bus_off;
|
input error_status;
|
input error_status;
|
input [7:0] rx_err_cnt;
|
input [7:0] rx_err_cnt;
|
input [7:0] tx_err_cnt;
|
input [7:0] tx_err_cnt;
|
input transmit_status;
|
input transmit_status;
|
input receive_status;
|
input receive_status;
|
input tx_successful;
|
input tx_successful;
|
input need_to_tx;
|
input need_to_tx;
|
input overrun;
|
input overrun;
|
input info_empty;
|
input info_empty;
|
input set_bus_error_irq;
|
input set_bus_error_irq;
|
input set_arbitration_lost_irq;
|
input set_arbitration_lost_irq;
|
input [4:0] arbitration_lost_capture;
|
input [4:0] arbitration_lost_capture;
|
input node_error_passive;
|
input node_error_passive;
|
input node_error_active;
|
input node_error_active;
|
input [6:0] rx_message_counter;
|
input [6:0] rx_message_counter;
|
|
|
|
|
|
|
/* Mode register */
|
/* Mode register */
|
output reset_mode;
|
output reset_mode;
|
output listen_only_mode;
|
output listen_only_mode;
|
output acceptance_filter_mode;
|
output acceptance_filter_mode;
|
output self_test_mode;
|
output self_test_mode;
|
|
|
/* Command register */
|
/* Command register */
|
output clear_data_overrun;
|
output clear_data_overrun;
|
output release_buffer;
|
output release_buffer;
|
output abort_tx;
|
output abort_tx;
|
output tx_request;
|
output tx_request;
|
output self_rx_request;
|
output self_rx_request;
|
output single_shot_transmission;
|
output single_shot_transmission;
|
input tx_state;
|
input tx_state;
|
input tx_state_q;
|
input tx_state_q;
|
|
|
/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
output read_arbitration_lost_capture_reg;
|
output read_arbitration_lost_capture_reg;
|
|
|
/* Error Code Capture Register */
|
/* Error Code Capture Register */
|
output read_error_code_capture_reg;
|
output read_error_code_capture_reg;
|
input [7:0] error_capture_code;
|
input [7:0] error_capture_code;
|
|
|
/* Bus Timing 0 register */
|
/* Bus Timing 0 register */
|
output [5:0] baud_r_presc;
|
output [5:0] baud_r_presc;
|
output [1:0] sync_jump_width;
|
output [1:0] sync_jump_width;
|
|
|
|
|
/* Bus Timing 1 register */
|
/* Bus Timing 1 register */
|
output [3:0] time_segment1;
|
output [3:0] time_segment1;
|
output [2:0] time_segment2;
|
output [2:0] time_segment2;
|
output triple_sampling;
|
output triple_sampling;
|
|
|
/* Error Warning Limit register */
|
/* Error Warning Limit register */
|
output [7:0] error_warning_limit;
|
output [7:0] error_warning_limit;
|
|
|
/* Rx Error Counter register */
|
/* Rx Error Counter register */
|
output we_rx_err_cnt;
|
output we_rx_err_cnt;
|
|
|
/* Tx Error Counter register */
|
/* Tx Error Counter register */
|
output we_tx_err_cnt;
|
output we_tx_err_cnt;
|
|
|
/* Clock Divider register */
|
/* Clock Divider register */
|
output extended_mode;
|
output extended_mode;
|
output clkout;
|
output clkout;
|
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
output [7:0] acceptance_code_0;
|
output [7:0] acceptance_code_0;
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
output [7:0] acceptance_mask_0;
|
output [7:0] acceptance_mask_0;
|
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
output [7:0] acceptance_code_1;
|
output [7:0] acceptance_code_1;
|
output [7:0] acceptance_code_2;
|
output [7:0] acceptance_code_2;
|
output [7:0] acceptance_code_3;
|
output [7:0] acceptance_code_3;
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
output [7:0] acceptance_mask_1;
|
output [7:0] acceptance_mask_1;
|
output [7:0] acceptance_mask_2;
|
output [7:0] acceptance_mask_2;
|
output [7:0] acceptance_mask_3;
|
output [7:0] acceptance_mask_3;
|
|
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
output [7:0] tx_data_0;
|
output [7:0] tx_data_0;
|
output [7:0] tx_data_1;
|
output [7:0] tx_data_1;
|
output [7:0] tx_data_2;
|
output [7:0] tx_data_2;
|
output [7:0] tx_data_3;
|
output [7:0] tx_data_3;
|
output [7:0] tx_data_4;
|
output [7:0] tx_data_4;
|
output [7:0] tx_data_5;
|
output [7:0] tx_data_5;
|
output [7:0] tx_data_6;
|
output [7:0] tx_data_6;
|
output [7:0] tx_data_7;
|
output [7:0] tx_data_7;
|
output [7:0] tx_data_8;
|
output [7:0] tx_data_8;
|
output [7:0] tx_data_9;
|
output [7:0] tx_data_9;
|
output [7:0] tx_data_10;
|
output [7:0] tx_data_10;
|
output [7:0] tx_data_11;
|
output [7:0] tx_data_11;
|
output [7:0] tx_data_12;
|
output [7:0] tx_data_12;
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
|
|
reg tx_successful_q;
|
reg tx_successful_q;
|
reg overrun_q;
|
reg overrun_q;
|
reg overrun_status;
|
reg overrun_status;
|
reg transmission_complete;
|
reg transmission_complete;
|
reg transmit_buffer_status_q;
|
reg transmit_buffer_status_q;
|
reg receive_buffer_status;
|
reg receive_buffer_status;
|
reg info_empty_q;
|
reg info_empty_q;
|
reg error_status_q;
|
reg error_status_q;
|
reg node_bus_off_q;
|
reg node_bus_off_q;
|
reg node_error_passive_q;
|
reg node_error_passive_q;
|
reg transmit_buffer_status;
|
reg transmit_buffer_status;
|
reg single_shot_transmission;
|
reg single_shot_transmission;
|
reg self_rx_request;
|
reg self_rx_request;
|
|
|
|
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
wire data_overrun_irq_en;
|
wire data_overrun_irq_en;
|
wire error_warning_irq_en;
|
wire error_warning_irq_en;
|
wire transmit_irq_en;
|
wire transmit_irq_en;
|
wire receive_irq_en;
|
wire receive_irq_en;
|
|
|
wire [7:0] irq_reg;
|
wire [7:0] irq_reg;
|
|
|
wire we_mode = cs & we & (addr == 8'd0);
|
wire we_mode = cs & we & (addr == 8'd0);
|
wire we_command = cs & we & (addr == 8'd1);
|
wire we_command = cs & we & (addr == 8'd1);
|
wire we_bus_timing_0 = cs & we & (addr == 8'd6) & reset_mode;
|
wire we_bus_timing_0 = cs & we & (addr == 8'd6) & reset_mode;
|
wire we_bus_timing_1 = cs & we & (addr == 8'd7) & reset_mode;
|
wire we_bus_timing_1 = cs & we & (addr == 8'd7) & reset_mode;
|
wire we_clock_divider_low = cs & we & (addr == 8'd31);
|
wire we_clock_divider_low = cs & we & (addr == 8'd31);
|
wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
|
wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
|
|
|
wire read = cs & (~we);
|
wire read = cs & (~we);
|
wire read_irq_reg = read & (addr == 8'd3);
|
wire read_irq_reg = read & (addr == 8'd3);
|
assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);
|
assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);
|
assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);
|
assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
wire we_acceptance_code_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
|
wire we_acceptance_code_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
|
wire we_acceptance_mask_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
|
wire we_acceptance_mask_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
|
wire we_tx_data_0 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) & transmit_buffer_status;
|
wire we_tx_data_0 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) & transmit_buffer_status;
|
wire we_tx_data_1 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) & transmit_buffer_status;
|
wire we_tx_data_1 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) & transmit_buffer_status;
|
wire we_tx_data_2 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) & transmit_buffer_status;
|
wire we_tx_data_2 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) & transmit_buffer_status;
|
wire we_tx_data_3 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) & transmit_buffer_status;
|
wire we_tx_data_3 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) & transmit_buffer_status;
|
wire we_tx_data_4 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) & transmit_buffer_status;
|
wire we_tx_data_4 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) & transmit_buffer_status;
|
wire we_tx_data_5 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) & transmit_buffer_status;
|
wire we_tx_data_5 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) & transmit_buffer_status;
|
wire we_tx_data_6 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;
|
wire we_tx_data_6 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;
|
wire we_tx_data_7 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) & transmit_buffer_status;
|
wire we_tx_data_7 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) & transmit_buffer_status;
|
wire we_tx_data_8 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) & transmit_buffer_status;
|
wire we_tx_data_8 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) & transmit_buffer_status;
|
wire we_tx_data_9 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) & transmit_buffer_status;
|
wire we_tx_data_9 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) & transmit_buffer_status;
|
wire we_tx_data_10 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd26)) & transmit_buffer_status;
|
wire we_tx_data_10 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd26)) & transmit_buffer_status;
|
wire we_tx_data_11 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd27)) & transmit_buffer_status;
|
wire we_tx_data_11 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd27)) & transmit_buffer_status;
|
wire we_tx_data_12 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd28)) & transmit_buffer_status;
|
wire we_tx_data_12 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd28)) & transmit_buffer_status;
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
wire we_interrupt_enable = cs & we & (addr == 8'd4) & extended_mode;
|
wire we_interrupt_enable = cs & we & (addr == 8'd4) & extended_mode;
|
wire we_error_warning_limit = cs & we & (addr == 8'd13) & reset_mode & extended_mode;
|
wire we_error_warning_limit = cs & we & (addr == 8'd13) & reset_mode & extended_mode;
|
assign we_rx_err_cnt = cs & we & (addr == 8'd14) & reset_mode & extended_mode;
|
assign we_rx_err_cnt = cs & we & (addr == 8'd14) & reset_mode & extended_mode;
|
assign we_tx_err_cnt = cs & we & (addr == 8'd15) & reset_mode & extended_mode;
|
assign we_tx_err_cnt = cs & we & (addr == 8'd15) & reset_mode & extended_mode;
|
wire we_acceptance_code_1 = cs & we & (addr == 8'd17) & reset_mode & extended_mode;
|
wire we_acceptance_code_1 = cs & we & (addr == 8'd17) & reset_mode & extended_mode;
|
wire we_acceptance_code_2 = cs & we & (addr == 8'd18) & reset_mode & extended_mode;
|
wire we_acceptance_code_2 = cs & we & (addr == 8'd18) & reset_mode & extended_mode;
|
wire we_acceptance_code_3 = cs & we & (addr == 8'd19) & reset_mode & extended_mode;
|
wire we_acceptance_code_3 = cs & we & (addr == 8'd19) & reset_mode & extended_mode;
|
wire we_acceptance_mask_1 = cs & we & (addr == 8'd21) & reset_mode & extended_mode;
|
wire we_acceptance_mask_1 = cs & we & (addr == 8'd21) & reset_mode & extended_mode;
|
wire we_acceptance_mask_2 = cs & we & (addr == 8'd22) & reset_mode & extended_mode;
|
wire we_acceptance_mask_2 = cs & we & (addr == 8'd22) & reset_mode & extended_mode;
|
wire we_acceptance_mask_3 = cs & we & (addr == 8'd23) & reset_mode & extended_mode;
|
wire we_acceptance_mask_3 = cs & we & (addr == 8'd23) & reset_mode & extended_mode;
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
tx_successful_q <=#Tp tx_successful;
|
tx_successful_q <=#Tp tx_successful;
|
overrun_q <=#Tp overrun;
|
overrun_q <=#Tp overrun;
|
transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
info_empty_q <=#Tp info_empty;
|
info_empty_q <=#Tp info_empty;
|
error_status_q <=#Tp error_status;
|
error_status_q <=#Tp error_status;
|
node_bus_off_q <=#Tp node_bus_off;
|
node_bus_off_q <=#Tp node_bus_off;
|
node_error_passive_q <=#Tp node_error_passive;
|
node_error_passive_q <=#Tp node_error_passive;
|
end
|
end
|
|
|
|
|
|
|
/* Mode register */
|
/* Mode register */
|
wire [0:0] mode;
|
wire [0:0] mode;
|
wire [4:1] mode_basic;
|
wire [4:1] mode_basic;
|
wire [3:1] mode_ext;
|
wire [3:1] mode_ext;
|
wire receive_irq_en_basic;
|
wire receive_irq_en_basic;
|
wire transmit_irq_en_basic;
|
wire transmit_irq_en_basic;
|
wire error_irq_en_basic;
|
wire error_irq_en_basic;
|
wire overrun_irq_en_basic;
|
wire overrun_irq_en_basic;
|
|
|
can_register_asyn_syn #(1, 1'h1) MODE_REG0
|
can_register_asyn_syn #(1, 1'h1) MODE_REG0
|
( .data_in(data_in[0]),
|
( .data_in(data_in[0]),
|
.data_out(mode[0]),
|
.data_out(mode[0]),
|
.we(we_mode),
|
.we(we_mode),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.rst_sync(set_reset_mode)
|
.rst_sync(set_reset_mode)
|
);
|
);
|
|
|
can_register_asyn #(4, 0) MODE_REG_BASIC
|
can_register_asyn #(4, 0) MODE_REG_BASIC
|
( .data_in(data_in[4:1]),
|
( .data_in(data_in[4:1]),
|
.data_out(mode_basic[4:1]),
|
.data_out(mode_basic[4:1]),
|
.we(we_mode),
|
.we(we_mode),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
|
|
can_register_asyn #(3, 0) MODE_REG_EXT
|
can_register_asyn #(3, 0) MODE_REG_EXT
|
( .data_in(data_in[3:1]),
|
( .data_in(data_in[3:1]),
|
.data_out(mode_ext[3:1]),
|
.data_out(mode_ext[3:1]),
|
.we(we_mode & reset_mode),
|
.we(we_mode & reset_mode),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
|
|
assign reset_mode = mode[0];
|
assign reset_mode = mode[0];
|
assign listen_only_mode = extended_mode & mode_ext[1];
|
assign listen_only_mode = extended_mode & mode_ext[1];
|
assign self_test_mode = extended_mode & mode_ext[2];
|
assign self_test_mode = extended_mode & mode_ext[2];
|
assign acceptance_filter_mode = extended_mode & mode_ext[3];
|
assign acceptance_filter_mode = extended_mode & mode_ext[3];
|
|
|
assign receive_irq_en_basic = mode_basic[1];
|
assign receive_irq_en_basic = mode_basic[1];
|
assign transmit_irq_en_basic = mode_basic[2];
|
assign transmit_irq_en_basic = mode_basic[2];
|
assign error_irq_en_basic = mode_basic[3];
|
assign error_irq_en_basic = mode_basic[3];
|
assign overrun_irq_en_basic = mode_basic[4];
|
assign overrun_irq_en_basic = mode_basic[4];
|
/* End Mode register */
|
/* End Mode register */
|
|
|
|
|
/* Command register */
|
/* Command register */
|
wire [4:0] command;
|
wire [4:0] command;
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
|
( .data_in(data_in[0]),
|
( .data_in(data_in[0]),
|
.data_out(command[0]),
|
.data_out(command[0]),
|
.we(we_command),
|
.we(we_command),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.rst_sync(command[0] & sample_point)
|
.rst_sync(command[0] & sample_point)
|
);
|
);
|
|
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
|
( .data_in(data_in[1]),
|
( .data_in(data_in[1]),
|
.data_out(command[1]),
|
.data_out(command[1]),
|
.we(we_command),
|
.we(we_command),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)))
|
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)))
|
);
|
);
|
|
|
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
|
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
|
( .data_in(data_in[3:2]),
|
( .data_in(data_in[3:2]),
|
.data_out(command[3:2]),
|
.data_out(command[3:2]),
|
.we(we_command),
|
.we(we_command),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.rst_sync(|command[3:2])
|
.rst_sync(|command[3:2])
|
);
|
);
|
|
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
|
( .data_in(data_in[4]),
|
( .data_in(data_in[4]),
|
.data_out(command[4]),
|
.data_out(command[4]),
|
.we(we_command),
|
.we(we_command),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.rst_sync(command[4] & sample_point)
|
.rst_sync(command[4] & sample_point)
|
);
|
);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
self_rx_request <= 1'b0;
|
self_rx_request <= 1'b0;
|
else if (command[4] & (~command[0]))
|
else if (command[4] & (~command[0]))
|
self_rx_request <=#Tp 1'b1;
|
self_rx_request <=#Tp 1'b1;
|
else if ((~tx_state) & tx_state_q)
|
else if ((~tx_state) & tx_state_q)
|
self_rx_request <=#Tp 1'b0;
|
self_rx_request <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
assign clear_data_overrun = command[3];
|
assign clear_data_overrun = command[3];
|
assign release_buffer = command[2];
|
assign release_buffer = command[2];
|
assign tx_request = command[0] | command[4];
|
assign tx_request = command[0] | command[4];
|
assign abort_tx = command[1] & (~tx_request);
|
assign abort_tx = command[1] & (~tx_request);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
single_shot_transmission <= 1'b0;
|
single_shot_transmission <= 1'b0;
|
else if (tx_request & command[1] & sample_point)
|
else if (tx_request & command[1] & sample_point)
|
single_shot_transmission <=#Tp 1'b1;
|
single_shot_transmission <=#Tp 1'b1;
|
else if ((~tx_state) & tx_state_q)
|
else if ((~tx_state) & tx_state_q)
|
single_shot_transmission <=#Tp 1'b0;
|
single_shot_transmission <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
/* End Command register */
|
/* End Command register */
|
|
|
|
|
/* Status register */
|
/* Status register */
|
|
|
wire [7:0] status;
|
wire [7:0] status;
|
|
|
assign status[7] = node_bus_off;
|
assign status[7] = node_bus_off;
|
assign status[6] = error_status;
|
assign status[6] = error_status;
|
assign status[5] = transmit_status;
|
assign status[5] = transmit_status;
|
assign status[4] = receive_status;
|
assign status[4] = receive_status;
|
assign status[3] = transmission_complete;
|
assign status[3] = transmission_complete;
|
assign status[2] = transmit_buffer_status;
|
assign status[2] = transmit_buffer_status;
|
assign status[1] = overrun_status;
|
assign status[1] = overrun_status;
|
assign status[0] = receive_buffer_status;
|
assign status[0] = receive_buffer_status;
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmission_complete <= 1'b1;
|
transmission_complete <= 1'b1;
|
else if (tx_successful & (~tx_successful_q) | abort_tx)
|
else if (tx_successful & (~tx_successful_q) | abort_tx)
|
transmission_complete <=#Tp 1'b1;
|
transmission_complete <=#Tp 1'b1;
|
else if (tx_request)
|
else if (tx_request)
|
transmission_complete <=#Tp 1'b0;
|
transmission_complete <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmit_buffer_status <= 1'b1;
|
transmit_buffer_status <= 1'b1;
|
else if (tx_request)
|
else if (tx_request)
|
transmit_buffer_status <=#Tp 1'b0;
|
transmit_buffer_status <=#Tp 1'b0;
|
else if (~need_to_tx)
|
else if (~need_to_tx)
|
transmit_buffer_status <=#Tp 1'b1;
|
transmit_buffer_status <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overrun_status <= 1'b0;
|
overrun_status <= 1'b0;
|
else if (overrun & (~overrun_q))
|
else if (overrun & (~overrun_q))
|
overrun_status <=#Tp 1'b1;
|
overrun_status <=#Tp 1'b1;
|
else if (clear_data_overrun)
|
else if (clear_data_overrun)
|
overrun_status <=#Tp 1'b0;
|
overrun_status <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
receive_buffer_status <= 1'b0;
|
receive_buffer_status <= 1'b0;
|
else if (release_buffer)
|
else if (release_buffer)
|
receive_buffer_status <=#Tp 1'b0;
|
receive_buffer_status <=#Tp 1'b0;
|
else if (~info_empty)
|
else if (~info_empty)
|
receive_buffer_status <=#Tp 1'b1;
|
receive_buffer_status <=#Tp 1'b1;
|
end
|
end
|
|
|
/* End Status register */
|
/* End Status register */
|
|
|
|
|
/* Interrupt Enable register (extended mode) */
|
/* Interrupt Enable register (extended mode) */
|
wire [7:0] irq_en_ext;
|
wire [7:0] irq_en_ext;
|
wire bus_error_irq_en;
|
wire bus_error_irq_en;
|
wire arbitration_lost_irq_en;
|
wire arbitration_lost_irq_en;
|
wire error_passive_irq_en;
|
wire error_passive_irq_en;
|
wire data_overrun_irq_en_ext;
|
wire data_overrun_irq_en_ext;
|
wire error_warning_irq_en_ext;
|
wire error_warning_irq_en_ext;
|
wire transmit_irq_en_ext;
|
wire transmit_irq_en_ext;
|
wire receive_irq_en_ext;
|
wire receive_irq_en_ext;
|
|
|
can_register #(8) IRQ_EN_REG
|
can_register #(8) IRQ_EN_REG
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(irq_en_ext),
|
.data_out(irq_en_ext),
|
.we(we_interrupt_enable),
|
.we(we_interrupt_enable),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
|
|
assign bus_error_irq_en = irq_en_ext[7];
|
assign bus_error_irq_en = irq_en_ext[7];
|
assign arbitration_lost_irq_en = irq_en_ext[6];
|
assign arbitration_lost_irq_en = irq_en_ext[6];
|
assign error_passive_irq_en = irq_en_ext[5];
|
assign error_passive_irq_en = irq_en_ext[5];
|
assign data_overrun_irq_en_ext = irq_en_ext[3];
|
assign data_overrun_irq_en_ext = irq_en_ext[3];
|
assign error_warning_irq_en_ext = irq_en_ext[2];
|
assign error_warning_irq_en_ext = irq_en_ext[2];
|
assign transmit_irq_en_ext = irq_en_ext[1];
|
assign transmit_irq_en_ext = irq_en_ext[1];
|
assign receive_irq_en_ext = irq_en_ext[0];
|
assign receive_irq_en_ext = irq_en_ext[0];
|
/* End Bus Timing 0 register */
|
/* End Bus Timing 0 register */
|
|
|
|
|
/* Bus Timing 0 register */
|
/* Bus Timing 0 register */
|
wire [7:0] bus_timing_0;
|
wire [7:0] bus_timing_0;
|
can_register #(8) BUS_TIMING_0_REG
|
can_register #(8) BUS_TIMING_0_REG
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(bus_timing_0),
|
.data_out(bus_timing_0),
|
.we(we_bus_timing_0),
|
.we(we_bus_timing_0),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
assign baud_r_presc = bus_timing_0[5:0];
|
assign baud_r_presc = bus_timing_0[5:0];
|
assign sync_jump_width = bus_timing_0[7:6];
|
assign sync_jump_width = bus_timing_0[7:6];
|
/* End Bus Timing 0 register */
|
/* End Bus Timing 0 register */
|
|
|
|
|
/* Bus Timing 1 register */
|
/* Bus Timing 1 register */
|
wire [7:0] bus_timing_1;
|
wire [7:0] bus_timing_1;
|
can_register #(8) BUS_TIMING_1_REG
|
can_register #(8) BUS_TIMING_1_REG
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(bus_timing_1),
|
.data_out(bus_timing_1),
|
.we(we_bus_timing_1),
|
.we(we_bus_timing_1),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
assign time_segment1 = bus_timing_1[3:0];
|
assign time_segment1 = bus_timing_1[3:0];
|
assign time_segment2 = bus_timing_1[6:4];
|
assign time_segment2 = bus_timing_1[6:4];
|
assign triple_sampling = bus_timing_1[7];
|
assign triple_sampling = bus_timing_1[7];
|
/* End Bus Timing 1 register */
|
/* End Bus Timing 1 register */
|
|
|
|
|
/* Error Warning Limit register */
|
/* Error Warning Limit register */
|
can_register_asyn #(8, 96) ERROR_WARNING_REG
|
can_register_asyn #(8, 96) ERROR_WARNING_REG
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(error_warning_limit),
|
.data_out(error_warning_limit),
|
.we(we_error_warning_limit),
|
.we(we_error_warning_limit),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
/* End Error Warning Limit register */
|
/* End Error Warning Limit register */
|
|
|
|
|
|
|
/* Clock Divider register */
|
/* Clock Divider register */
|
wire [7:0] clock_divider;
|
wire [7:0] clock_divider;
|
wire clock_off;
|
wire clock_off;
|
wire [2:0] cd;
|
wire [2:0] cd;
|
reg [2:0] clkout_div;
|
reg [2:0] clkout_div;
|
reg [2:0] clkout_cnt;
|
reg [2:0] clkout_cnt;
|
reg clkout_tmp;
|
reg clkout_tmp;
|
//reg clkout;
|
//reg clkout;
|
|
|
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
|
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
|
( .data_in(data_in[7]),
|
( .data_in(data_in[7]),
|
.data_out(clock_divider[7]),
|
.data_out(clock_divider[7]),
|
.we(we_clock_divider_hi),
|
.we(we_clock_divider_hi),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
|
|
assign clock_divider[6:4] = 3'h0;
|
assign clock_divider[6:4] = 3'h0;
|
|
|
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_3
|
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_3
|
( .data_in(data_in[3]),
|
( .data_in(data_in[3]),
|
.data_out(clock_divider[3]),
|
.data_out(clock_divider[3]),
|
.we(we_clock_divider_hi),
|
.we(we_clock_divider_hi),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
|
|
can_register_asyn #(3, 0) CLOCK_DIVIDER_REG_LOW
|
can_register_asyn #(3, 0) CLOCK_DIVIDER_REG_LOW
|
( .data_in(data_in[2:0]),
|
( .data_in(data_in[2:0]),
|
.data_out(clock_divider[2:0]),
|
.data_out(clock_divider[2:0]),
|
.we(we_clock_divider_low),
|
.we(we_clock_divider_low),
|
.clk(clk),
|
.clk(clk),
|
.rst(rst)
|
.rst(rst)
|
);
|
);
|
|
|
assign extended_mode = clock_divider[7];
|
assign extended_mode = clock_divider[7];
|
assign clock_off = clock_divider[3];
|
assign clock_off = clock_divider[3];
|
assign cd[2:0] = clock_divider[2:0];
|
assign cd[2:0] = clock_divider[2:0];
|
|
|
|
|
|
|
always @ (cd)
|
always @ (cd)
|
begin
|
begin
|
case (cd) /* synthesis full_case parallel_case */
|
case (cd) /* synthesis full_case parallel_case */
|
3'b000 : clkout_div <= 0;
|
3'b000 : clkout_div <= 0;
|
3'b001 : clkout_div <= 1;
|
3'b001 : clkout_div <= 1;
|
3'b010 : clkout_div <= 2;
|
3'b010 : clkout_div <= 2;
|
3'b011 : clkout_div <= 3;
|
3'b011 : clkout_div <= 3;
|
3'b100 : clkout_div <= 4;
|
3'b100 : clkout_div <= 4;
|
3'b101 : clkout_div <= 5;
|
3'b101 : clkout_div <= 5;
|
3'b110 : clkout_div <= 6;
|
3'b110 : clkout_div <= 6;
|
3'b111 : clkout_div <= 0;
|
3'b111 : clkout_div <= 0;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
clkout_cnt <= 3'h0;
|
clkout_cnt <= 3'h0;
|
else if (clkout_cnt == clkout_div)
|
else if (clkout_cnt == clkout_div)
|
clkout_cnt <=#Tp 3'h0;
|
clkout_cnt <=#Tp 3'h0;
|
else
|
else
|
clkout_cnt <= clkout_cnt + 1'b1;
|
clkout_cnt <= clkout_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
clkout_tmp <= 1'b0;
|
clkout_tmp <= 1'b0;
|
else if (clkout_cnt == clkout_div)
|
else if (clkout_cnt == clkout_div)
|
clkout_tmp <=#Tp ~clkout_tmp;
|
clkout_tmp <=#Tp ~clkout_tmp;
|
end
|
end
|
|
|
|
|
/*
|
/*
|
//always @ (cd or clk or clkout_tmp or clock_off)
|
//always @ (cd or clk or clkout_tmp or clock_off)
|
always @ (cd or clkout_tmp or clock_off)
|
always @ (cd or clkout_tmp or clock_off)
|
begin
|
begin
|
if (clock_off)
|
if (clock_off)
|
clkout <=#Tp 1'b1;
|
clkout <=#Tp 1'b1;
|
// else if (&cd)
|
// else if (&cd)
|
// clkout <=#Tp clk;
|
// clkout <=#Tp clk;
|
else
|
else
|
clkout <=#Tp clkout_tmp;
|
clkout <=#Tp clkout_tmp;
|
end
|
end
|
*/
|
*/
|
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
|
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
|
|
|
|
|
|
|
/* End Clock Divider register */
|
/* End Clock Divider register */
|
|
|
|
|
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
|
|
/* Acceptance code register */
|
/* Acceptance code register */
|
can_register #(8) ACCEPTANCE_CODE_REG0
|
can_register #(8) ACCEPTANCE_CODE_REG0
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_code_0),
|
.data_out(acceptance_code_0),
|
.we(we_acceptance_code_0),
|
.we(we_acceptance_code_0),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
can_register #(8) ACCEPTANCE_MASK_REG0
|
can_register #(8) ACCEPTANCE_MASK_REG0
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_mask_0),
|
.data_out(acceptance_mask_0),
|
.we(we_acceptance_mask_0),
|
.we(we_acceptance_mask_0),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance mask register */
|
/* End: Acceptance mask register */
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
|
|
/* Tx data 0 register. */
|
/* Tx data 0 register. */
|
can_register #(8) TX_DATA_REG0
|
can_register #(8) TX_DATA_REG0
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_0),
|
.data_out(tx_data_0),
|
.we(we_tx_data_0),
|
.we(we_tx_data_0),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 0 register. */
|
/* End: Tx data 0 register. */
|
|
|
|
|
/* Tx data 1 register. */
|
/* Tx data 1 register. */
|
can_register #(8) TX_DATA_REG1
|
can_register #(8) TX_DATA_REG1
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_1),
|
.data_out(tx_data_1),
|
.we(we_tx_data_1),
|
.we(we_tx_data_1),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 1 register. */
|
/* End: Tx data 1 register. */
|
|
|
|
|
/* Tx data 2 register. */
|
/* Tx data 2 register. */
|
can_register #(8) TX_DATA_REG2
|
can_register #(8) TX_DATA_REG2
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_2),
|
.data_out(tx_data_2),
|
.we(we_tx_data_2),
|
.we(we_tx_data_2),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 2 register. */
|
/* End: Tx data 2 register. */
|
|
|
|
|
/* Tx data 3 register. */
|
/* Tx data 3 register. */
|
can_register #(8) TX_DATA_REG3
|
can_register #(8) TX_DATA_REG3
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_3),
|
.data_out(tx_data_3),
|
.we(we_tx_data_3),
|
.we(we_tx_data_3),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 3 register. */
|
/* End: Tx data 3 register. */
|
|
|
|
|
/* Tx data 4 register. */
|
/* Tx data 4 register. */
|
can_register #(8) TX_DATA_REG4
|
can_register #(8) TX_DATA_REG4
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_4),
|
.data_out(tx_data_4),
|
.we(we_tx_data_4),
|
.we(we_tx_data_4),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 4 register. */
|
/* End: Tx data 4 register. */
|
|
|
|
|
/* Tx data 5 register. */
|
/* Tx data 5 register. */
|
can_register #(8) TX_DATA_REG5
|
can_register #(8) TX_DATA_REG5
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_5),
|
.data_out(tx_data_5),
|
.we(we_tx_data_5),
|
.we(we_tx_data_5),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 5 register. */
|
/* End: Tx data 5 register. */
|
|
|
|
|
/* Tx data 6 register. */
|
/* Tx data 6 register. */
|
can_register #(8) TX_DATA_REG6
|
can_register #(8) TX_DATA_REG6
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_6),
|
.data_out(tx_data_6),
|
.we(we_tx_data_6),
|
.we(we_tx_data_6),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 6 register. */
|
/* End: Tx data 6 register. */
|
|
|
|
|
/* Tx data 7 register. */
|
/* Tx data 7 register. */
|
can_register #(8) TX_DATA_REG7
|
can_register #(8) TX_DATA_REG7
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_7),
|
.data_out(tx_data_7),
|
.we(we_tx_data_7),
|
.we(we_tx_data_7),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 7 register. */
|
/* End: Tx data 7 register. */
|
|
|
|
|
/* Tx data 8 register. */
|
/* Tx data 8 register. */
|
can_register #(8) TX_DATA_REG8
|
can_register #(8) TX_DATA_REG8
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_8),
|
.data_out(tx_data_8),
|
.we(we_tx_data_8),
|
.we(we_tx_data_8),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 8 register. */
|
/* End: Tx data 8 register. */
|
|
|
|
|
/* Tx data 9 register. */
|
/* Tx data 9 register. */
|
can_register #(8) TX_DATA_REG9
|
can_register #(8) TX_DATA_REG9
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_9),
|
.data_out(tx_data_9),
|
.we(we_tx_data_9),
|
.we(we_tx_data_9),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 9 register. */
|
/* End: Tx data 9 register. */
|
|
|
|
|
/* Tx data 10 register. */
|
/* Tx data 10 register. */
|
can_register #(8) TX_DATA_REG10
|
can_register #(8) TX_DATA_REG10
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_10),
|
.data_out(tx_data_10),
|
.we(we_tx_data_10),
|
.we(we_tx_data_10),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 10 register. */
|
/* End: Tx data 10 register. */
|
|
|
|
|
/* Tx data 11 register. */
|
/* Tx data 11 register. */
|
can_register #(8) TX_DATA_REG11
|
can_register #(8) TX_DATA_REG11
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_11),
|
.data_out(tx_data_11),
|
.we(we_tx_data_11),
|
.we(we_tx_data_11),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 11 register. */
|
/* End: Tx data 11 register. */
|
|
|
|
|
/* Tx data 12 register. */
|
/* Tx data 12 register. */
|
can_register #(8) TX_DATA_REG12
|
can_register #(8) TX_DATA_REG12
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(tx_data_12),
|
.data_out(tx_data_12),
|
.we(we_tx_data_12),
|
.we(we_tx_data_12),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Tx data 12 register. */
|
/* End: Tx data 12 register. */
|
|
|
|
|
|
|
|
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
|
|
/* Acceptance code register 1 */
|
/* Acceptance code register 1 */
|
can_register #(8) ACCEPTANCE_CODE_REG1
|
can_register #(8) ACCEPTANCE_CODE_REG1
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_code_1),
|
.data_out(acceptance_code_1),
|
.we(we_acceptance_code_1),
|
.we(we_acceptance_code_1),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance code register 2 */
|
/* Acceptance code register 2 */
|
can_register #(8) ACCEPTANCE_CODE_REG2
|
can_register #(8) ACCEPTANCE_CODE_REG2
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_code_2),
|
.data_out(acceptance_code_2),
|
.we(we_acceptance_code_2),
|
.we(we_acceptance_code_2),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance code register 3 */
|
/* Acceptance code register 3 */
|
can_register #(8) ACCEPTANCE_CODE_REG3
|
can_register #(8) ACCEPTANCE_CODE_REG3
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_code_3),
|
.data_out(acceptance_code_3),
|
.we(we_acceptance_code_3),
|
.we(we_acceptance_code_3),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance mask register 1 */
|
/* Acceptance mask register 1 */
|
can_register #(8) ACCEPTANCE_MASK_REG1
|
can_register #(8) ACCEPTANCE_MASK_REG1
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_mask_1),
|
.data_out(acceptance_mask_1),
|
.we(we_acceptance_mask_1),
|
.we(we_acceptance_mask_1),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance mask register 2 */
|
/* Acceptance mask register 2 */
|
can_register #(8) ACCEPTANCE_MASK_REG2
|
can_register #(8) ACCEPTANCE_MASK_REG2
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_mask_2),
|
.data_out(acceptance_mask_2),
|
.we(we_acceptance_mask_2),
|
.we(we_acceptance_mask_2),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* Acceptance mask register 3 */
|
/* Acceptance mask register 3 */
|
can_register #(8) ACCEPTANCE_MASK_REG3
|
can_register #(8) ACCEPTANCE_MASK_REG3
|
( .data_in(data_in),
|
( .data_in(data_in),
|
.data_out(acceptance_mask_3),
|
.data_out(acceptance_mask_3),
|
.we(we_acceptance_mask_3),
|
.we(we_acceptance_mask_3),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* End: Acceptance code register */
|
/* End: Acceptance code register */
|
|
|
|
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
|
|
|
|
|
|
// Reading data from registers
|
// Reading data from registers
|
always @ ( addr or read or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
|
always @ ( addr or read or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
|
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
|
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
|
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
|
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
|
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
|
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
|
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
|
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
|
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
|
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
|
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
|
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
|
)
|
)
|
begin
|
begin
|
if(read) // read
|
if(read) // read
|
begin
|
begin
|
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
|
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
|
begin
|
begin
|
case(addr) /* synthesis full_case parallel_case */
|
case(addr) /* synthesis full_case parallel_case */
|
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
|
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
|
8'd1 : data_out <= 8'h0;
|
8'd1 : data_out <= 8'h0;
|
8'd2 : data_out <= status;
|
8'd2 : data_out <= status;
|
8'd3 : data_out <= irq_reg;
|
8'd3 : data_out <= irq_reg;
|
8'd4 : data_out <= irq_en_ext;
|
8'd4 : data_out <= irq_en_ext;
|
8'd6 : data_out <= bus_timing_0;
|
8'd6 : data_out <= bus_timing_0;
|
8'd7 : data_out <= bus_timing_1;
|
8'd7 : data_out <= bus_timing_1;
|
8'd11 : data_out <= {3'h0, arbitration_lost_capture[4:0]};
|
8'd11 : data_out <= {3'h0, arbitration_lost_capture[4:0]};
|
8'd12 : data_out <= error_capture_code;
|
8'd12 : data_out <= error_capture_code;
|
8'd13 : data_out <= error_warning_limit;
|
8'd13 : data_out <= error_warning_limit;
|
8'd14 : data_out <= rx_err_cnt;
|
8'd14 : data_out <= rx_err_cnt;
|
8'd15 : data_out <= tx_err_cnt;
|
8'd15 : data_out <= tx_err_cnt;
|
8'd16 : data_out <= acceptance_code_0;
|
8'd16 : data_out <= acceptance_code_0;
|
8'd17 : data_out <= acceptance_code_1;
|
8'd17 : data_out <= acceptance_code_1;
|
8'd18 : data_out <= acceptance_code_2;
|
8'd18 : data_out <= acceptance_code_2;
|
8'd19 : data_out <= acceptance_code_3;
|
8'd19 : data_out <= acceptance_code_3;
|
8'd20 : data_out <= acceptance_mask_0;
|
8'd20 : data_out <= acceptance_mask_0;
|
8'd21 : data_out <= acceptance_mask_1;
|
8'd21 : data_out <= acceptance_mask_1;
|
8'd22 : data_out <= acceptance_mask_2;
|
8'd22 : data_out <= acceptance_mask_2;
|
8'd23 : data_out <= acceptance_mask_3;
|
8'd23 : data_out <= acceptance_mask_3;
|
8'd24 : data_out <= 8'h0;
|
8'd24 : data_out <= 8'h0;
|
8'd25 : data_out <= 8'h0;
|
8'd25 : data_out <= 8'h0;
|
8'd26 : data_out <= 8'h0;
|
8'd26 : data_out <= 8'h0;
|
8'd27 : data_out <= 8'h0;
|
8'd27 : data_out <= 8'h0;
|
8'd28 : data_out <= 8'h0;
|
8'd28 : data_out <= 8'h0;
|
8'd29 : data_out <= {1'b0, rx_message_counter};
|
8'd29 : data_out <= {1'b0, rx_message_counter};
|
8'd31 : data_out <= clock_divider;
|
8'd31 : data_out <= clock_divider;
|
endcase
|
endcase
|
end
|
end
|
else // BASIC mode
|
else // BASIC mode
|
begin
|
begin
|
case(addr) /* synthesis full_case parallel_case */
|
case(addr) /* synthesis full_case parallel_case */
|
8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
|
8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
|
8'd1 : data_out <= 8'hff;
|
8'd1 : data_out <= 8'hff;
|
8'd2 : data_out <= status;
|
8'd2 : data_out <= status;
|
8'd3 : data_out <= {4'hf, irq_reg[3:0]};
|
8'd3 : data_out <= {4'hf, irq_reg[3:0]};
|
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
|
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
|
8'd5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
|
8'd5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
|
8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
|
8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
|
8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
|
8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
|
8'd10 : data_out <= reset_mode? 8'hff : tx_data_0;
|
8'd10 : data_out <= reset_mode? 8'hff : tx_data_0;
|
8'd11 : data_out <= reset_mode? 8'hff : tx_data_1;
|
8'd11 : data_out <= reset_mode? 8'hff : tx_data_1;
|
8'd12 : data_out <= reset_mode? 8'hff : tx_data_2;
|
8'd12 : data_out <= reset_mode? 8'hff : tx_data_2;
|
8'd13 : data_out <= reset_mode? 8'hff : tx_data_3;
|
8'd13 : data_out <= reset_mode? 8'hff : tx_data_3;
|
8'd14 : data_out <= reset_mode? 8'hff : tx_data_4;
|
8'd14 : data_out <= reset_mode? 8'hff : tx_data_4;
|
8'd15 : data_out <= reset_mode? 8'hff : tx_data_5;
|
8'd15 : data_out <= reset_mode? 8'hff : tx_data_5;
|
8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
|
8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
|
8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
|
8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
|
8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
|
8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
|
8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
|
8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
|
8'd31 : data_out <= clock_divider;
|
8'd31 : data_out <= clock_divider;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else
|
else
|
data_out <= 8'h0;
|
data_out <= 8'h0;
|
end
|
end
|
|
|
|
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
|
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
|
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
|
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
|
assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
|
assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
|
assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
|
assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
|
|
|
|
|
reg data_overrun_irq;
|
reg data_overrun_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_overrun_irq <= 1'b0;
|
data_overrun_irq <= 1'b0;
|
else if (overrun & (~overrun_q) & data_overrun_irq_en)
|
else if (overrun & (~overrun_q) & data_overrun_irq_en)
|
data_overrun_irq <=#Tp 1'b1;
|
data_overrun_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
data_overrun_irq <=#Tp 1'b0;
|
data_overrun_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
reg transmit_irq;
|
reg transmit_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmit_irq <= 1'b0;
|
transmit_irq <= 1'b0;
|
else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
|
else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
|
transmit_irq <=#Tp 1'b1;
|
transmit_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
transmit_irq <=#Tp 1'b0;
|
transmit_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
reg receive_irq;
|
reg receive_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
receive_irq <= 1'b0;
|
receive_irq <= 1'b0;
|
else if (release_buffer)
|
else if (release_buffer)
|
receive_irq <=#Tp 1'b0;
|
receive_irq <=#Tp 1'b0;
|
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
|
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
|
receive_irq <=#Tp 1'b1;
|
receive_irq <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
reg error_irq;
|
reg error_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_irq <= 1'b0;
|
error_irq <= 1'b0;
|
else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
|
else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
|
error_irq <=#Tp 1'b1;
|
error_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
error_irq <=#Tp 1'b0;
|
error_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
reg bus_error_irq;
|
reg bus_error_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_error_irq <= 1'b0;
|
bus_error_irq <= 1'b0;
|
else if (set_bus_error_irq & bus_error_irq_en)
|
else if (set_bus_error_irq & bus_error_irq_en)
|
bus_error_irq <=#Tp 1'b1;
|
bus_error_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
bus_error_irq <=#Tp 1'b0;
|
bus_error_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
reg arbitration_lost_irq;
|
reg arbitration_lost_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_lost_irq <= 1'b0;
|
arbitration_lost_irq <= 1'b0;
|
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
|
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
|
arbitration_lost_irq <=#Tp 1'b1;
|
arbitration_lost_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
arbitration_lost_irq <=#Tp 1'b0;
|
arbitration_lost_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
reg error_passive_irq;
|
reg error_passive_irq;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_passive_irq <= 1'b0;
|
error_passive_irq <= 1'b0;
|
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
|
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
|
error_passive_irq <=#Tp 1'b1;
|
error_passive_irq <=#Tp 1'b1;
|
else if (read_irq_reg)
|
else if (read_irq_reg)
|
error_passive_irq <=#Tp 1'b0;
|
error_passive_irq <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
|
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
|
|
|
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
|
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|