//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_bsp.v ////
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//// can_bsp.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// from Bosch. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.35 2003/06/27 20:56:12 simons
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|
// Virtual silicon ram instances added.
|
|
//
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// Revision 1.34 2003/06/22 09:43:03 mohor
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// Revision 1.34 2003/06/22 09:43:03 mohor
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// synthesis full_case parallel_case fixed.
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// synthesis full_case parallel_case fixed.
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//
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//
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// Revision 1.33 2003/06/21 12:16:30 mohor
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// Revision 1.33 2003/06/21 12:16:30 mohor
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// paralel_case and full_case compiler directives added to case statements.
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// paralel_case and full_case compiler directives added to case statements.
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//
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//
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// Revision 1.32 2003/06/17 14:28:32 mohor
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// Revision 1.32 2003/06/17 14:28:32 mohor
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// Form error was detected when stuff bit occured at the end of crc.
|
// Form error was detected when stuff bit occured at the end of crc.
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//
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//
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// Revision 1.31 2003/06/16 14:31:29 tadejm
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// Revision 1.31 2003/06/16 14:31:29 tadejm
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// Bit stuffing corrected when stuffing comes at the end of the crc.
|
// Bit stuffing corrected when stuffing comes at the end of the crc.
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//
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//
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// Revision 1.30 2003/06/16 13:57:58 mohor
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// Revision 1.30 2003/06/16 13:57:58 mohor
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// using extended mode.
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// using extended mode.
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//
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//
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// Revision 1.29 2003/06/11 14:21:35 mohor
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// Revision 1.29 2003/06/11 14:21:35 mohor
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// When switching to tx, sync stage is overjumped.
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// When switching to tx, sync stage is overjumped.
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//
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//
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// Revision 1.28 2003/03/01 22:53:33 mohor
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// Revision 1.28 2003/03/01 22:53:33 mohor
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// Actel APA ram supported.
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// Actel APA ram supported.
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//
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//
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// Revision 1.27 2003/02/20 00:26:02 mohor
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// Revision 1.27 2003/02/20 00:26:02 mohor
|
// When a dominant bit was detected at the third bit of the intermission and
|
// When a dominant bit was detected at the third bit of the intermission and
|
// node had a message to transmit, bit_stuff error could occur. Fixed.
|
// node had a message to transmit, bit_stuff error could occur. Fixed.
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//
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//
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// Revision 1.26 2003/02/19 23:21:54 mohor
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// Revision 1.26 2003/02/19 23:21:54 mohor
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// When bit error occured while active error flag was transmitted, counter was
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// When bit error occured while active error flag was transmitted, counter was
|
// not incremented.
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// not incremented.
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//
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//
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// Revision 1.25 2003/02/19 14:44:03 mohor
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// Revision 1.25 2003/02/19 14:44:03 mohor
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// CAN core finished. Host interface added. Registers finished.
|
// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
|
// Synchronization to the wishbone finished.
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//
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//
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// Revision 1.24 2003/02/18 00:10:15 mohor
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// Revision 1.24 2003/02/18 00:10:15 mohor
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// Most of the registers added. Registers "arbitration lost capture", "error code
|
// Most of the registers added. Registers "arbitration lost capture", "error code
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// capture" + few more still need to be added.
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// capture" + few more still need to be added.
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//
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//
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// Revision 1.23 2003/02/14 20:17:01 mohor
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// Revision 1.23 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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// Several registers added. Not finished, yet.
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//
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//
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// Revision 1.22 2003/02/12 14:23:59 mohor
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// Revision 1.22 2003/02/12 14:23:59 mohor
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// abort_tx added. Bit destuff fixed.
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// abort_tx added. Bit destuff fixed.
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//
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//
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// Revision 1.21 2003/02/11 00:56:06 mohor
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// Revision 1.21 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
|
// Wishbone interface added.
|
//
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//
|
// Revision 1.20 2003/02/10 16:02:11 mohor
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// Revision 1.20 2003/02/10 16:02:11 mohor
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// CAN is working according to the specification. WB interface and more
|
// CAN is working according to the specification. WB interface and more
|
// registers (status, IRQ, ...) needs to be added.
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// registers (status, IRQ, ...) needs to be added.
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//
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//
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// Revision 1.19 2003/02/09 18:40:29 mohor
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// Revision 1.19 2003/02/09 18:40:29 mohor
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// Overload fixed. Hard synchronization also enabled at the last bit of
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// Overload fixed. Hard synchronization also enabled at the last bit of
|
// interframe.
|
// interframe.
|
//
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//
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// Revision 1.18 2003/02/09 02:24:33 mohor
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// Revision 1.18 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
|
// Bosch license warning added. Error counters finished. Overload frames
|
// still need to be fixed.
|
// still need to be fixed.
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//
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//
|
// Revision 1.17 2003/02/04 17:24:41 mohor
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// Revision 1.17 2003/02/04 17:24:41 mohor
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// Backup.
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// Backup.
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//
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//
|
// Revision 1.16 2003/02/04 14:34:52 mohor
|
// Revision 1.16 2003/02/04 14:34:52 mohor
|
// *** empty log message ***
|
// *** empty log message ***
|
//
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//
|
// Revision 1.15 2003/01/31 01:13:37 mohor
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// Revision 1.15 2003/01/31 01:13:37 mohor
|
// backup.
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// backup.
|
//
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//
|
// Revision 1.14 2003/01/16 13:36:19 mohor
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// Revision 1.14 2003/01/16 13:36:19 mohor
|
// Form error supported. When receiving messages, last bit of the end-of-frame
|
// Form error supported. When receiving messages, last bit of the end-of-frame
|
// does not generate form error. Receiver goes to the idle mode one bit sooner.
|
// does not generate form error. Receiver goes to the idle mode one bit sooner.
|
// (CAN specification ver 2.0, part B, page 57).
|
// (CAN specification ver 2.0, part B, page 57).
|
//
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//
|
// Revision 1.13 2003/01/15 21:59:45 mohor
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// Revision 1.13 2003/01/15 21:59:45 mohor
|
// Data is stored to fifo at the end of ack stage.
|
// Data is stored to fifo at the end of ack stage.
|
//
|
//
|
// Revision 1.12 2003/01/15 21:05:11 mohor
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// Revision 1.12 2003/01/15 21:05:11 mohor
|
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
|
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
|
//
|
//
|
// Revision 1.11 2003/01/15 14:40:23 mohor
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// Revision 1.11 2003/01/15 14:40:23 mohor
|
// RX state machine fixed to receive "remote request" frames correctly.
|
// RX state machine fixed to receive "remote request" frames correctly.
|
// No data bytes are written to fifo when such frames are received.
|
// No data bytes are written to fifo when such frames are received.
|
//
|
//
|
// Revision 1.10 2003/01/15 13:16:47 mohor
|
// Revision 1.10 2003/01/15 13:16:47 mohor
|
// When a frame with "remote request" is received, no data is stored to
|
// When a frame with "remote request" is received, no data is stored to
|
// fifo, just the frame information (identifier, ...). Data length that
|
// fifo, just the frame information (identifier, ...). Data length that
|
// is stored is the received data length and not the actual data length
|
// is stored is the received data length and not the actual data length
|
// that is stored to fifo.
|
// that is stored to fifo.
|
//
|
//
|
// Revision 1.9 2003/01/14 12:19:35 mohor
|
// Revision 1.9 2003/01/14 12:19:35 mohor
|
// rx_fifo is now working.
|
// rx_fifo is now working.
|
//
|
//
|
// Revision 1.8 2003/01/10 17:51:33 mohor
|
// Revision 1.8 2003/01/10 17:51:33 mohor
|
// Temporary version (backup).
|
// Temporary version (backup).
|
//
|
//
|
// Revision 1.7 2003/01/09 21:54:45 mohor
|
// Revision 1.7 2003/01/09 21:54:45 mohor
|
// rx fifo added. Not 100 % verified, yet.
|
// rx fifo added. Not 100 % verified, yet.
|
//
|
//
|
// Revision 1.6 2003/01/09 14:46:58 mohor
|
// Revision 1.6 2003/01/09 14:46:58 mohor
|
// Temporary files (backup).
|
// Temporary files (backup).
|
//
|
//
|
// Revision 1.5 2003/01/08 13:30:31 mohor
|
// Revision 1.5 2003/01/08 13:30:31 mohor
|
// Temp version.
|
// Temp version.
|
//
|
//
|
// Revision 1.4 2003/01/08 02:10:53 mohor
|
// Revision 1.4 2003/01/08 02:10:53 mohor
|
// Acceptance filter added.
|
// Acceptance filter added.
|
//
|
//
|
// Revision 1.3 2002/12/28 04:13:23 mohor
|
// Revision 1.3 2002/12/28 04:13:23 mohor
|
// Backup version.
|
// Backup version.
|
//
|
//
|
// Revision 1.2 2002/12/27 00:12:52 mohor
|
// Revision 1.2 2002/12/27 00:12:52 mohor
|
// Header changed, testbench improved to send a frame (crc still missing).
|
// Header changed, testbench improved to send a frame (crc still missing).
|
//
|
//
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
// Initial
|
// Initial
|
//
|
//
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "can_defines.v"
|
`include "can_defines.v"
|
|
|
module can_bsp
|
module can_bsp
|
(
|
(
|
clk,
|
clk,
|
rst,
|
rst,
|
|
|
sample_point,
|
sample_point,
|
sampled_bit,
|
sampled_bit,
|
sampled_bit_q,
|
sampled_bit_q,
|
tx_point,
|
tx_point,
|
hard_sync,
|
hard_sync,
|
|
|
addr,
|
addr,
|
data_in,
|
data_in,
|
data_out,
|
data_out,
|
fifo_selected,
|
fifo_selected,
|
|
|
|
|
|
|
/* Mode register */
|
/* Mode register */
|
reset_mode,
|
reset_mode,
|
listen_only_mode,
|
listen_only_mode,
|
acceptance_filter_mode,
|
acceptance_filter_mode,
|
self_test_mode,
|
self_test_mode,
|
|
|
/* Command register */
|
/* Command register */
|
release_buffer,
|
release_buffer,
|
tx_request,
|
tx_request,
|
abort_tx,
|
abort_tx,
|
self_rx_request,
|
self_rx_request,
|
single_shot_transmission,
|
single_shot_transmission,
|
|
|
/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
read_arbitration_lost_capture_reg,
|
read_arbitration_lost_capture_reg,
|
|
|
/* Error Code Capture Register */
|
/* Error Code Capture Register */
|
read_error_code_capture_reg,
|
read_error_code_capture_reg,
|
error_capture_code,
|
error_capture_code,
|
|
|
/* Error Warning Limit register */
|
/* Error Warning Limit register */
|
error_warning_limit,
|
error_warning_limit,
|
|
|
/* Rx Error Counter register */
|
/* Rx Error Counter register */
|
we_rx_err_cnt,
|
we_rx_err_cnt,
|
|
|
/* Tx Error Counter register */
|
/* Tx Error Counter register */
|
we_tx_err_cnt,
|
we_tx_err_cnt,
|
|
|
/* Clock Divider register */
|
/* Clock Divider register */
|
extended_mode,
|
extended_mode,
|
|
|
rx_idle,
|
rx_idle,
|
transmitting,
|
transmitting,
|
|
go_rx_inter,
|
last_bit_of_inter,
|
last_bit_of_inter,
|
set_reset_mode,
|
set_reset_mode,
|
node_bus_off,
|
node_bus_off,
|
error_status,
|
error_status,
|
rx_err_cnt,
|
rx_err_cnt,
|
tx_err_cnt,
|
tx_err_cnt,
|
transmit_status,
|
transmit_status,
|
receive_status,
|
receive_status,
|
tx_successful,
|
tx_successful,
|
need_to_tx,
|
need_to_tx,
|
overrun,
|
overrun,
|
info_empty,
|
info_empty,
|
set_bus_error_irq,
|
set_bus_error_irq,
|
set_arbitration_lost_irq,
|
set_arbitration_lost_irq,
|
arbitration_lost_capture,
|
arbitration_lost_capture,
|
node_error_passive,
|
node_error_passive,
|
node_error_active,
|
node_error_active,
|
rx_message_counter,
|
rx_message_counter,
|
|
|
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
acceptance_code_0,
|
acceptance_code_0,
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
acceptance_mask_0,
|
acceptance_mask_0,
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
acceptance_code_1,
|
acceptance_code_1,
|
acceptance_code_2,
|
acceptance_code_2,
|
acceptance_code_3,
|
acceptance_code_3,
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
acceptance_mask_1,
|
acceptance_mask_1,
|
acceptance_mask_2,
|
acceptance_mask_2,
|
acceptance_mask_3,
|
acceptance_mask_3,
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
tx_data_0,
|
tx_data_0,
|
tx_data_1,
|
tx_data_1,
|
tx_data_2,
|
tx_data_2,
|
tx_data_3,
|
tx_data_3,
|
tx_data_4,
|
tx_data_4,
|
tx_data_5,
|
tx_data_5,
|
tx_data_6,
|
tx_data_6,
|
tx_data_7,
|
tx_data_7,
|
tx_data_8,
|
tx_data_8,
|
tx_data_9,
|
tx_data_9,
|
tx_data_10,
|
tx_data_10,
|
tx_data_11,
|
tx_data_11,
|
tx_data_12,
|
tx_data_12,
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
/* Tx signal */
|
/* Tx signal */
|
tx,
|
tx,
|
tx_oen
|
tx_oen
|
|
|
/* Bist */
|
/* Bist */
|
`ifdef CAN_BIST
|
`ifdef CAN_BIST
|
,
|
,
|
scanb_rst,
|
scanb_rst,
|
scanb_clk,
|
scanb_clk,
|
scanb_si,
|
scanb_si,
|
scanb_so,
|
scanb_so,
|
scanb_en
|
scanb_en
|
`endif
|
`endif
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input sample_point;
|
input sample_point;
|
input sampled_bit;
|
input sampled_bit;
|
input sampled_bit_q;
|
input sampled_bit_q;
|
input tx_point;
|
input tx_point;
|
input hard_sync;
|
input hard_sync;
|
input [7:0] addr;
|
input [7:0] addr;
|
input [7:0] data_in;
|
input [7:0] data_in;
|
output [7:0] data_out;
|
output [7:0] data_out;
|
input fifo_selected;
|
input fifo_selected;
|
|
|
|
|
input reset_mode;
|
input reset_mode;
|
input listen_only_mode;
|
input listen_only_mode;
|
input acceptance_filter_mode;
|
input acceptance_filter_mode;
|
input extended_mode;
|
input extended_mode;
|
input self_test_mode;
|
input self_test_mode;
|
|
|
|
|
/* Command register */
|
/* Command register */
|
input release_buffer;
|
input release_buffer;
|
input tx_request;
|
input tx_request;
|
input abort_tx;
|
input abort_tx;
|
input self_rx_request;
|
input self_rx_request;
|
input single_shot_transmission;
|
input single_shot_transmission;
|
|
|
/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
input read_arbitration_lost_capture_reg;
|
input read_arbitration_lost_capture_reg;
|
|
|
/* Error Code Capture Register */
|
/* Error Code Capture Register */
|
input read_error_code_capture_reg;
|
input read_error_code_capture_reg;
|
output [7:0] error_capture_code;
|
output [7:0] error_capture_code;
|
|
|
/* Error Warning Limit register */
|
/* Error Warning Limit register */
|
input [7:0] error_warning_limit;
|
input [7:0] error_warning_limit;
|
|
|
/* Rx Error Counter register */
|
/* Rx Error Counter register */
|
input we_rx_err_cnt;
|
input we_rx_err_cnt;
|
|
|
/* Tx Error Counter register */
|
/* Tx Error Counter register */
|
input we_tx_err_cnt;
|
input we_tx_err_cnt;
|
|
|
output rx_idle;
|
output rx_idle;
|
output transmitting;
|
output transmitting;
|
|
output go_rx_inter;
|
output last_bit_of_inter;
|
output last_bit_of_inter;
|
output set_reset_mode;
|
output set_reset_mode;
|
output node_bus_off;
|
output node_bus_off;
|
output error_status;
|
output error_status;
|
output [8:0] rx_err_cnt;
|
output [8:0] rx_err_cnt;
|
output [8:0] tx_err_cnt;
|
output [8:0] tx_err_cnt;
|
output transmit_status;
|
output transmit_status;
|
output receive_status;
|
output receive_status;
|
output tx_successful;
|
output tx_successful;
|
output need_to_tx;
|
output need_to_tx;
|
output overrun;
|
output overrun;
|
output info_empty;
|
output info_empty;
|
output set_bus_error_irq;
|
output set_bus_error_irq;
|
output set_arbitration_lost_irq;
|
output set_arbitration_lost_irq;
|
output [4:0] arbitration_lost_capture;
|
output [4:0] arbitration_lost_capture;
|
output node_error_passive;
|
output node_error_passive;
|
output node_error_active;
|
output node_error_active;
|
output [6:0] rx_message_counter;
|
output [6:0] rx_message_counter;
|
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
input [7:0] acceptance_code_0;
|
input [7:0] acceptance_code_0;
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
input [7:0] acceptance_mask_0;
|
input [7:0] acceptance_mask_0;
|
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
input [7:0] acceptance_code_1;
|
input [7:0] acceptance_code_1;
|
input [7:0] acceptance_code_2;
|
input [7:0] acceptance_code_2;
|
input [7:0] acceptance_code_3;
|
input [7:0] acceptance_code_3;
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
input [7:0] acceptance_mask_1;
|
input [7:0] acceptance_mask_1;
|
input [7:0] acceptance_mask_2;
|
input [7:0] acceptance_mask_2;
|
input [7:0] acceptance_mask_3;
|
input [7:0] acceptance_mask_3;
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
input [7:0] tx_data_0;
|
input [7:0] tx_data_0;
|
input [7:0] tx_data_1;
|
input [7:0] tx_data_1;
|
input [7:0] tx_data_2;
|
input [7:0] tx_data_2;
|
input [7:0] tx_data_3;
|
input [7:0] tx_data_3;
|
input [7:0] tx_data_4;
|
input [7:0] tx_data_4;
|
input [7:0] tx_data_5;
|
input [7:0] tx_data_5;
|
input [7:0] tx_data_6;
|
input [7:0] tx_data_6;
|
input [7:0] tx_data_7;
|
input [7:0] tx_data_7;
|
input [7:0] tx_data_8;
|
input [7:0] tx_data_8;
|
input [7:0] tx_data_9;
|
input [7:0] tx_data_9;
|
input [7:0] tx_data_10;
|
input [7:0] tx_data_10;
|
input [7:0] tx_data_11;
|
input [7:0] tx_data_11;
|
input [7:0] tx_data_12;
|
input [7:0] tx_data_12;
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
/* Tx signal */
|
/* Tx signal */
|
output tx;
|
output tx;
|
output tx_oen;
|
output tx_oen;
|
|
|
/* Bist */
|
/* Bist */
|
`ifdef CAN_BIST
|
`ifdef CAN_BIST
|
input scanb_rst;
|
input scanb_rst;
|
input scanb_clk;
|
input scanb_clk;
|
input scanb_si;
|
input scanb_si;
|
output scanb_so;
|
output scanb_so;
|
input scanb_en;
|
input scanb_en;
|
`endif
|
`endif
|
|
|
reg reset_mode_q;
|
reg reset_mode_q;
|
reg [5:0] bit_cnt;
|
reg [5:0] bit_cnt;
|
|
|
reg [3:0] data_len;
|
reg [3:0] data_len;
|
reg [28:0] id;
|
reg [28:0] id;
|
reg [2:0] bit_stuff_cnt;
|
reg [2:0] bit_stuff_cnt;
|
reg [2:0] bit_stuff_cnt_tx;
|
reg [2:0] bit_stuff_cnt_tx;
|
reg tx_point_q;
|
reg tx_point_q;
|
|
|
reg rx_idle;
|
reg rx_idle;
|
reg rx_id1;
|
reg rx_id1;
|
reg rx_rtr1;
|
reg rx_rtr1;
|
reg rx_ide;
|
reg rx_ide;
|
reg rx_id2;
|
reg rx_id2;
|
reg rx_rtr2;
|
reg rx_rtr2;
|
reg rx_r1;
|
reg rx_r1;
|
reg rx_r0;
|
reg rx_r0;
|
reg rx_dlc;
|
reg rx_dlc;
|
reg rx_data;
|
reg rx_data;
|
reg rx_crc;
|
reg rx_crc;
|
reg rx_crc_lim;
|
reg rx_crc_lim;
|
reg rx_ack;
|
reg rx_ack;
|
reg rx_ack_lim;
|
reg rx_ack_lim;
|
reg rx_eof;
|
reg rx_eof;
|
reg rx_inter;
|
reg rx_inter;
|
reg go_early_tx_latched;
|
reg go_early_tx_latched;
|
|
|
reg rtr1;
|
reg rtr1;
|
reg ide;
|
reg ide;
|
reg rtr2;
|
reg rtr2;
|
reg [14:0] crc_in;
|
reg [14:0] crc_in;
|
|
|
reg [7:0] tmp_data;
|
reg [7:0] tmp_data;
|
reg [7:0] tmp_fifo [0:7];
|
reg [7:0] tmp_fifo [0:7];
|
reg write_data_to_tmp_fifo;
|
reg write_data_to_tmp_fifo;
|
reg [2:0] byte_cnt;
|
reg [2:0] byte_cnt;
|
reg bit_stuff_cnt_en;
|
reg bit_stuff_cnt_en;
|
reg bit_stuff_cnt_tx_en;
|
reg bit_stuff_cnt_tx_en;
|
reg crc_enable;
|
reg crc_enable;
|
|
|
reg [2:0] eof_cnt;
|
reg [2:0] eof_cnt;
|
reg [2:0] passive_cnt;
|
reg [2:0] passive_cnt;
|
|
|
reg transmitting;
|
reg transmitting;
|
|
|
reg error_frame;
|
reg error_frame;
|
reg error_frame_q;
|
reg error_frame_q;
|
reg enable_error_cnt2;
|
reg enable_error_cnt2;
|
reg [2:0] error_cnt1;
|
reg [2:0] error_cnt1;
|
reg [2:0] error_cnt2;
|
reg [2:0] error_cnt2;
|
reg [2:0] delayed_dominant_cnt;
|
reg [2:0] delayed_dominant_cnt;
|
reg enable_overload_cnt2;
|
reg enable_overload_cnt2;
|
reg overload_frame;
|
reg overload_frame;
|
reg overload_frame_blocked;
|
reg overload_frame_blocked;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt2;
|
reg [2:0] overload_cnt2;
|
reg tx;
|
reg tx;
|
reg crc_err;
|
reg crc_err;
|
|
|
reg arbitration_lost;
|
reg arbitration_lost;
|
reg arbitration_lost_q;
|
reg arbitration_lost_q;
|
reg [4:0] arbitration_lost_capture;
|
reg [4:0] arbitration_lost_capture;
|
reg arbitration_cnt_en;
|
reg arbitration_cnt_en;
|
reg arbitration_blocked;
|
reg arbitration_blocked;
|
reg tx_q;
|
reg tx_q;
|
|
|
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
|
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
|
reg [2:0] header_cnt; // Counting header length
|
reg [2:0] header_cnt; // Counting header length
|
reg wr_fifo; // Write data and header to 64-byte fifo
|
reg wr_fifo; // Write data and header to 64-byte fifo
|
reg [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
|
reg [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
|
|
|
reg [5:0] tx_pointer;
|
reg [5:0] tx_pointer;
|
reg tx_bit;
|
reg tx_bit;
|
reg tx_state;
|
reg tx_state;
|
reg transmitter;
|
reg transmitter;
|
reg finish_msg;
|
reg finish_msg;
|
|
|
reg [8:0] rx_err_cnt;
|
reg [8:0] rx_err_cnt;
|
reg [8:0] tx_err_cnt;
|
reg [8:0] tx_err_cnt;
|
reg rx_err_cnt_blocked;
|
reg rx_err_cnt_blocked;
|
reg [3:0] bus_free_cnt;
|
reg [3:0] bus_free_cnt;
|
reg bus_free_cnt_en;
|
reg bus_free_cnt_en;
|
reg bus_free;
|
reg bus_free;
|
reg waiting_for_bus_free;
|
reg waiting_for_bus_free;
|
|
|
reg node_error_passive;
|
reg node_error_passive;
|
reg node_bus_off;
|
reg node_bus_off;
|
reg node_bus_off_q;
|
reg node_bus_off_q;
|
reg ack_err_latched;
|
reg ack_err_latched;
|
reg bit_err_latched;
|
reg bit_err_latched;
|
reg stuff_err_latched;
|
reg stuff_err_latched;
|
reg form_err_latched;
|
reg form_err_latched;
|
reg rule3_exc1_1;
|
reg rule3_exc1_1;
|
reg rule3_exc1_2;
|
reg rule3_exc1_2;
|
reg rule3_exc2;
|
reg rule3_exc2;
|
reg suspend;
|
reg suspend;
|
reg susp_cnt_en;
|
reg susp_cnt_en;
|
reg [2:0] susp_cnt;
|
reg [2:0] susp_cnt;
|
reg error_flag_over_blocked;
|
reg error_flag_over_blocked;
|
|
|
reg [7:0] error_capture_code;
|
reg [7:0] error_capture_code;
|
reg [7:6] error_capture_code_type;
|
reg [7:6] error_capture_code_type;
|
reg error_capture_code_blocked;
|
reg error_capture_code_blocked;
|
|
|
wire [4:0] error_capture_code_segment;
|
wire [4:0] error_capture_code_segment;
|
wire error_capture_code_direction;
|
wire error_capture_code_direction;
|
|
|
wire bit_de_stuff;
|
wire bit_de_stuff;
|
wire bit_de_stuff_tx;
|
wire bit_de_stuff_tx;
|
|
|
wire rule5;
|
wire rule5;
|
|
|
/* Rx state machine */
|
/* Rx state machine */
|
wire go_rx_idle;
|
wire go_rx_idle;
|
wire go_rx_id1;
|
wire go_rx_id1;
|
wire go_rx_rtr1;
|
wire go_rx_rtr1;
|
wire go_rx_ide;
|
wire go_rx_ide;
|
wire go_rx_id2;
|
wire go_rx_id2;
|
wire go_rx_rtr2;
|
wire go_rx_rtr2;
|
wire go_rx_r1;
|
wire go_rx_r1;
|
wire go_rx_r0;
|
wire go_rx_r0;
|
wire go_rx_dlc;
|
wire go_rx_dlc;
|
wire go_rx_data;
|
wire go_rx_data;
|
wire go_rx_crc;
|
wire go_rx_crc;
|
wire go_rx_crc_lim;
|
wire go_rx_crc_lim;
|
wire go_rx_ack;
|
wire go_rx_ack;
|
wire go_rx_ack_lim;
|
wire go_rx_ack_lim;
|
wire go_rx_eof;
|
wire go_rx_eof;
|
wire go_overload_frame;
|
wire go_overload_frame;
|
wire go_rx_inter;
|
wire go_rx_inter;
|
wire go_error_frame;
|
wire go_error_frame;
|
|
|
wire go_crc_enable;
|
wire go_crc_enable;
|
wire rst_crc_enable;
|
wire rst_crc_enable;
|
|
|
wire bit_de_stuff_set;
|
wire bit_de_stuff_set;
|
wire bit_de_stuff_reset;
|
wire bit_de_stuff_reset;
|
|
|
wire go_early_tx;
|
wire go_early_tx;
|
wire go_tx;
|
wire go_tx;
|
|
|
wire [14:0] calculated_crc;
|
wire [14:0] calculated_crc;
|
wire [15:0] r_calculated_crc;
|
wire [15:0] r_calculated_crc;
|
wire remote_rq;
|
wire remote_rq;
|
wire [3:0] limited_data_len;
|
wire [3:0] limited_data_len;
|
wire form_err;
|
wire form_err;
|
|
|
wire error_frame_ended;
|
wire error_frame_ended;
|
wire overload_frame_ended;
|
wire overload_frame_ended;
|
wire bit_err;
|
wire bit_err;
|
wire ack_err;
|
wire ack_err;
|
wire stuff_err;
|
wire stuff_err;
|
// of intermission, it starts reading the identifier (and transmitting its own).
|
// of intermission, it starts reading the identifier (and transmitting its own).
|
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
|
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
|
// be send in a row. This is not implemented because host can not send an overload request.
|
// be send in a row. This is not implemented because host can not send an overload request.
|
|
|
wire id_ok; // If received ID matches ID set in registers
|
wire id_ok; // If received ID matches ID set in registers
|
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
|
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
|
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
|
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
|
|
|
wire [2:0] header_len;
|
wire [2:0] header_len;
|
wire storing_header;
|
wire storing_header;
|
wire [3:0] limited_data_len_minus1;
|
wire [3:0] limited_data_len_minus1;
|
wire reset_wr_fifo;
|
wire reset_wr_fifo;
|
wire err;
|
wire err;
|
|
|
wire arbitration_field;
|
wire arbitration_field;
|
|
|
wire [18:0] basic_chain;
|
wire [18:0] basic_chain;
|
wire [63:0] basic_chain_data;
|
wire [63:0] basic_chain_data;
|
wire [18:0] extended_chain_std;
|
wire [18:0] extended_chain_std;
|
wire [38:0] extended_chain_ext;
|
wire [38:0] extended_chain_ext;
|
wire [63:0] extended_chain_data_std;
|
wire [63:0] extended_chain_data_std;
|
wire [63:0] extended_chain_data_ext;
|
wire [63:0] extended_chain_data_ext;
|
|
|
wire rst_tx_pointer;
|
wire rst_tx_pointer;
|
|
|
wire [7:0] r_tx_data_0;
|
wire [7:0] r_tx_data_0;
|
wire [7:0] r_tx_data_1;
|
wire [7:0] r_tx_data_1;
|
wire [7:0] r_tx_data_2;
|
wire [7:0] r_tx_data_2;
|
wire [7:0] r_tx_data_3;
|
wire [7:0] r_tx_data_3;
|
wire [7:0] r_tx_data_4;
|
wire [7:0] r_tx_data_4;
|
wire [7:0] r_tx_data_5;
|
wire [7:0] r_tx_data_5;
|
wire [7:0] r_tx_data_6;
|
wire [7:0] r_tx_data_6;
|
wire [7:0] r_tx_data_7;
|
wire [7:0] r_tx_data_7;
|
wire [7:0] r_tx_data_8;
|
wire [7:0] r_tx_data_8;
|
wire [7:0] r_tx_data_9;
|
wire [7:0] r_tx_data_9;
|
wire [7:0] r_tx_data_10;
|
wire [7:0] r_tx_data_10;
|
wire [7:0] r_tx_data_11;
|
wire [7:0] r_tx_data_11;
|
wire [7:0] r_tx_data_12;
|
wire [7:0] r_tx_data_12;
|
|
|
wire send_ack;
|
wire send_ack;
|
wire bit_err_exc1;
|
wire bit_err_exc1;
|
wire bit_err_exc2;
|
wire bit_err_exc2;
|
wire bit_err_exc3;
|
wire bit_err_exc3;
|
wire bit_err_exc4;
|
wire bit_err_exc4;
|
wire bit_err_exc5;
|
wire bit_err_exc5;
|
wire error_flag_over;
|
wire error_flag_over;
|
wire overload_flag_over;
|
wire overload_flag_over;
|
|
|
|
|
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
|
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
|
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
|
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
|
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
|
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
|
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
|
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
|
assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
|
assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
|
assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
|
assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
|
assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) | rx_r1);
|
assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) | rx_r1);
|
assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;
|
assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;
|
assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit | (|data_len[2:0])) & (~remote_rq);
|
assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit | (|data_len[2:0])) & (~remote_rq);
|
assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
|
assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
|
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
|
assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_eof = sample_point & rx_ack_lim;
|
assign go_rx_eof = sample_point & rx_ack_lim;
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);
|
|
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
|
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 7) & tx_point;
|
|
|
assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed |
|
assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) |
|
sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7))
|
sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7))
|
)
|
)
|
& (~overload_frame_blocked)
|
& (~overload_frame_blocked)
|
;
|
;
|
|
|
|
|
assign go_crc_enable = hard_sync | go_tx;
|
assign go_crc_enable = hard_sync | go_tx;
|
assign rst_crc_enable = go_rx_crc;
|
assign rst_crc_enable = go_rx_crc;
|
|
|
assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
|
assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
|
assign bit_de_stuff_reset = go_rx_ack | reset_mode | go_error_frame | go_overload_frame;
|
assign bit_de_stuff_reset = go_rx_ack | reset_mode | go_error_frame | go_overload_frame;
|
|
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
|
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
|
assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));
|
assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));
|
|
|
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
|
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
|
|
|
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
|
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
|
|
|
|
|
// Rx idle state
|
// Rx idle state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_idle <= 1'b0;
|
rx_idle <= 1'b0;
|
else if (reset_mode | go_rx_id1 | error_frame)
|
else if (reset_mode | go_rx_id1 | error_frame)
|
rx_idle <=#Tp 1'b0;
|
rx_idle <=#Tp 1'b0;
|
else if (go_rx_idle)
|
else if (go_rx_idle)
|
rx_idle <=#Tp 1'b1;
|
rx_idle <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx id1 state
|
// Rx id1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id1 <= 1'b0;
|
rx_id1 <= 1'b0;
|
else if (reset_mode | go_rx_rtr1 | error_frame)
|
else if (reset_mode | go_rx_rtr1 | error_frame)
|
rx_id1 <=#Tp 1'b0;
|
rx_id1 <=#Tp 1'b0;
|
else if (go_rx_id1)
|
else if (go_rx_id1)
|
rx_id1 <=#Tp 1'b1;
|
rx_id1 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx rtr1 state
|
// Rx rtr1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr1 <= 1'b0;
|
rx_rtr1 <= 1'b0;
|
else if (reset_mode | go_rx_ide | error_frame)
|
else if (reset_mode | go_rx_ide | error_frame)
|
rx_rtr1 <=#Tp 1'b0;
|
rx_rtr1 <=#Tp 1'b0;
|
else if (go_rx_rtr1)
|
else if (go_rx_rtr1)
|
rx_rtr1 <=#Tp 1'b1;
|
rx_rtr1 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx ide state
|
// Rx ide state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ide <= 1'b0;
|
rx_ide <= 1'b0;
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
|
rx_ide <=#Tp 1'b0;
|
rx_ide <=#Tp 1'b0;
|
else if (go_rx_ide)
|
else if (go_rx_ide)
|
rx_ide <=#Tp 1'b1;
|
rx_ide <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx id2 state
|
// Rx id2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id2 <= 1'b0;
|
rx_id2 <= 1'b0;
|
else if (reset_mode | go_rx_rtr2 | error_frame)
|
else if (reset_mode | go_rx_rtr2 | error_frame)
|
rx_id2 <=#Tp 1'b0;
|
rx_id2 <=#Tp 1'b0;
|
else if (go_rx_id2)
|
else if (go_rx_id2)
|
rx_id2 <=#Tp 1'b1;
|
rx_id2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx rtr2 state
|
// Rx rtr2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr2 <= 1'b0;
|
rx_rtr2 <= 1'b0;
|
else if (reset_mode | go_rx_r1 | error_frame)
|
else if (reset_mode | go_rx_r1 | error_frame)
|
rx_rtr2 <=#Tp 1'b0;
|
rx_rtr2 <=#Tp 1'b0;
|
else if (go_rx_rtr2)
|
else if (go_rx_rtr2)
|
rx_rtr2 <=#Tp 1'b1;
|
rx_rtr2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r1 <= 1'b0;
|
rx_r1 <= 1'b0;
|
else if (reset_mode | go_rx_r0 | error_frame)
|
else if (reset_mode | go_rx_r0 | error_frame)
|
rx_r1 <=#Tp 1'b0;
|
rx_r1 <=#Tp 1'b0;
|
else if (go_rx_r1)
|
else if (go_rx_r1)
|
rx_r1 <=#Tp 1'b1;
|
rx_r1 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r0 <= 1'b0;
|
rx_r0 <= 1'b0;
|
else if (reset_mode | go_rx_dlc | error_frame)
|
else if (reset_mode | go_rx_dlc | error_frame)
|
rx_r0 <=#Tp 1'b0;
|
rx_r0 <=#Tp 1'b0;
|
else if (go_rx_r0)
|
else if (go_rx_r0)
|
rx_r0 <=#Tp 1'b1;
|
rx_r0 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx dlc state
|
// Rx dlc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_dlc <= 1'b0;
|
rx_dlc <= 1'b0;
|
else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
|
else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
|
rx_dlc <=#Tp 1'b0;
|
rx_dlc <=#Tp 1'b0;
|
else if (go_rx_dlc)
|
else if (go_rx_dlc)
|
rx_dlc <=#Tp 1'b1;
|
rx_dlc <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx data state
|
// Rx data state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_data <= 1'b0;
|
rx_data <= 1'b0;
|
else if (reset_mode | go_rx_crc | error_frame)
|
else if (reset_mode | go_rx_crc | error_frame)
|
rx_data <=#Tp 1'b0;
|
rx_data <=#Tp 1'b0;
|
else if (go_rx_data)
|
else if (go_rx_data)
|
rx_data <=#Tp 1'b1;
|
rx_data <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx crc state
|
// Rx crc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc <= 1'b0;
|
rx_crc <= 1'b0;
|
else if (reset_mode | go_rx_crc_lim | error_frame)
|
else if (reset_mode | go_rx_crc_lim | error_frame)
|
rx_crc <=#Tp 1'b0;
|
rx_crc <=#Tp 1'b0;
|
else if (go_rx_crc)
|
else if (go_rx_crc)
|
rx_crc <=#Tp 1'b1;
|
rx_crc <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx crc delimiter state
|
// Rx crc delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc_lim <= 1'b0;
|
rx_crc_lim <= 1'b0;
|
else if (reset_mode | go_rx_ack | error_frame)
|
else if (reset_mode | go_rx_ack | error_frame)
|
rx_crc_lim <=#Tp 1'b0;
|
rx_crc_lim <=#Tp 1'b0;
|
else if (go_rx_crc_lim)
|
else if (go_rx_crc_lim)
|
rx_crc_lim <=#Tp 1'b1;
|
rx_crc_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx ack state
|
// Rx ack state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack <= 1'b0;
|
rx_ack <= 1'b0;
|
else if (reset_mode | go_rx_ack_lim | error_frame)
|
else if (reset_mode | go_rx_ack_lim | error_frame)
|
rx_ack <=#Tp 1'b0;
|
rx_ack <=#Tp 1'b0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
rx_ack <=#Tp 1'b1;
|
rx_ack <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx ack delimiter state
|
// Rx ack delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack_lim <= 1'b0;
|
rx_ack_lim <= 1'b0;
|
else if (reset_mode | go_rx_eof | error_frame)
|
else if (reset_mode | go_rx_eof | error_frame)
|
rx_ack_lim <=#Tp 1'b0;
|
rx_ack_lim <=#Tp 1'b0;
|
else if (go_rx_ack_lim)
|
else if (go_rx_ack_lim)
|
rx_ack_lim <=#Tp 1'b1;
|
rx_ack_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (go_rx_inter | error_frame | go_overload_frame)
|
else if (go_rx_inter | error_frame | go_overload_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Interframe space
|
// Interframe space
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_inter <= 1'b0;
|
rx_inter <= 1'b0;
|
else if (reset_mode | go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
else if (reset_mode | go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
rx_inter <=#Tp 1'b0;
|
rx_inter <=#Tp 1'b0;
|
else if (go_rx_inter)
|
else if (go_rx_inter)
|
rx_inter <=#Tp 1'b1;
|
rx_inter <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// ID register
|
// ID register
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
id <= 0;
|
id <= 0;
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
id <=#Tp {id[27:0], sampled_bit};
|
id <=#Tp {id[27:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// rtr1 bit
|
// rtr1 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr1 <= 0;
|
rtr1 <= 0;
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
rtr1 <=#Tp sampled_bit;
|
rtr1 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// rtr2 bit
|
// rtr2 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr2 <= 0;
|
rtr2 <= 0;
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
rtr2 <=#Tp sampled_bit;
|
rtr2 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// ide bit
|
// ide bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ide <= 0;
|
ide <= 0;
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
ide <=#Tp sampled_bit;
|
ide <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// Data length
|
// Data length
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_len <= 0;
|
data_len <= 0;
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// Data
|
// Data
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tmp_data <= 0;
|
tmp_data <= 0;
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
write_data_to_tmp_fifo <= 0;
|
write_data_to_tmp_fifo <= 0;
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
else
|
else
|
write_data_to_tmp_fifo <=#Tp 0;
|
write_data_to_tmp_fifo <=#Tp 0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
byte_cnt <= 0;
|
byte_cnt <= 0;
|
else if (write_data_to_tmp_fifo)
|
else if (write_data_to_tmp_fifo)
|
byte_cnt <=#Tp byte_cnt + 1;
|
byte_cnt <=#Tp byte_cnt + 1;
|
else if (reset_mode | (sample_point & go_rx_crc_lim))
|
else if (reset_mode | (sample_point & go_rx_crc_lim))
|
byte_cnt <=#Tp 0;
|
byte_cnt <=#Tp 0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (write_data_to_tmp_fifo)
|
if (write_data_to_tmp_fifo)
|
tmp_fifo[byte_cnt] <=#Tp tmp_data;
|
tmp_fifo[byte_cnt] <=#Tp tmp_data;
|
end
|
end
|
|
|
|
|
|
|
// CRC
|
// CRC
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_in <= 0;
|
crc_in <= 0;
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// bit_cnt
|
// bit_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_cnt <= 0;
|
bit_cnt <= 0;
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
bit_cnt <=#Tp 0;
|
bit_cnt <=#Tp 0;
|
else if (sample_point & (~bit_de_stuff))
|
else if (sample_point & (~bit_de_stuff))
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
// eof_cnt
|
// eof_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
eof_cnt <= 0;
|
eof_cnt <= 0;
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
|
if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
|
eof_cnt <=#Tp 0;
|
eof_cnt <=#Tp 0;
|
else if (rx_eof)
|
else if (rx_eof)
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Enabling bit de-stuffing
|
// Enabling bit de-stuffing
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_en <= 1'b0;
|
bit_stuff_cnt_en <= 1'b0;
|
else if (bit_de_stuff_set)
|
else if (bit_de_stuff_set)
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// bit_stuff_cnt
|
// bit_stuff_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt <= 1;
|
bit_stuff_cnt <= 1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt <=#Tp 1;
|
bit_stuff_cnt <=#Tp 1;
|
else if (sample_point & bit_stuff_cnt_en)
|
else if (sample_point & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt == 5)
|
if (bit_stuff_cnt == 5)
|
bit_stuff_cnt <=#Tp 1;
|
bit_stuff_cnt <=#Tp 1;
|
else if (sampled_bit == sampled_bit_q)
|
else if (sampled_bit == sampled_bit_q)
|
bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
|
bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
|
else
|
else
|
bit_stuff_cnt <=#Tp 1;
|
bit_stuff_cnt <=#Tp 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Enabling bit de-stuffing for tx
|
// Enabling bit de-stuffing for tx
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_tx_en <= 1'b0;
|
bit_stuff_cnt_tx_en <= 1'b0;
|
else if (bit_de_stuff_set & transmitting)
|
else if (bit_de_stuff_set & transmitting)
|
bit_stuff_cnt_tx_en <=#Tp 1'b1;
|
bit_stuff_cnt_tx_en <=#Tp 1'b1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_tx_en <=#Tp 1'b0;
|
bit_stuff_cnt_tx_en <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// bit_stuff_cnt_tx
|
// bit_stuff_cnt_tx
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_tx <= 1;
|
bit_stuff_cnt_tx <= 1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_tx <=#Tp 1;
|
bit_stuff_cnt_tx <=#Tp 1;
|
else if (tx_point_q & bit_stuff_cnt_en)
|
else if (tx_point_q & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt_tx == 5)
|
if (bit_stuff_cnt_tx == 5)
|
bit_stuff_cnt_tx <=#Tp 1;
|
bit_stuff_cnt_tx <=#Tp 1;
|
else if (tx == tx_q)
|
else if (tx == tx_q)
|
bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
|
bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
|
else
|
else
|
bit_stuff_cnt_tx <=#Tp 1;
|
bit_stuff_cnt_tx <=#Tp 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign bit_de_stuff = bit_stuff_cnt == 5;
|
assign bit_de_stuff = bit_stuff_cnt == 5;
|
assign bit_de_stuff_tx = bit_stuff_cnt_tx == 5;
|
assign bit_de_stuff_tx = bit_stuff_cnt_tx == 5;
|
|
|
|
|
|
|
// stuff_err
|
// stuff_err
|
assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
|
assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
|
|
|
|
|
|
|
// Generating delayed signals
|
// Generating delayed signals
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
reset_mode_q <=#Tp reset_mode;
|
reset_mode_q <=#Tp reset_mode;
|
node_bus_off_q <=#Tp node_bus_off;
|
node_bus_off_q <=#Tp node_bus_off;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_enable <= 1'b0;
|
crc_enable <= 1'b0;
|
else if (go_crc_enable)
|
else if (go_crc_enable)
|
crc_enable <=#Tp 1'b1;
|
crc_enable <=#Tp 1'b1;
|
else if (reset_mode | rst_crc_enable)
|
else if (reset_mode | rst_crc_enable)
|
crc_enable <=#Tp 1'b0;
|
crc_enable <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// CRC error generation
|
// CRC error generation
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_err <= 1'b0;
|
crc_err <= 1'b0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
crc_err <=#Tp crc_in != calculated_crc;
|
crc_err <=#Tp crc_in != calculated_crc;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended)
|
crc_err <=#Tp 1'b0;
|
crc_err <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// Conditions for form error
|
// Conditions for form error
|
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) ) |
|
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) ) |
|
((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
|
((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
|
( rx_ack_lim & (~sampled_bit) ) |
|
( rx_ack_lim & (~sampled_bit) ) |
|
((eof_cnt < 6) & rx_eof & (~sampled_bit) & (~tx_state) ) |
|
((eof_cnt < 6) & rx_eof & (~sampled_bit) & (~tx_state) ) |
|
( & rx_eof & (~sampled_bit) & tx_state )
|
( & rx_eof & (~sampled_bit) & tx_state )
|
);
|
);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ack_err_latched <= 1'b0;
|
ack_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
ack_err_latched <=#Tp 1'b0;
|
ack_err_latched <=#Tp 1'b0;
|
else if (ack_err)
|
else if (ack_err)
|
ack_err_latched <=#Tp 1'b1;
|
ack_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_err_latched <= 1'b0;
|
bit_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
bit_err_latched <=#Tp 1'b0;
|
bit_err_latched <=#Tp 1'b0;
|
else if (bit_err)
|
else if (bit_err)
|
bit_err_latched <=#Tp 1'b1;
|
bit_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Rule 5 (Fault confinement).
|
// Rule 5 (Fault confinement).
|
assign rule5 = (~node_error_passive) & bit_err & (error_frame & (error_cnt1 < 7) |
|
assign rule5 = (~node_error_passive) & bit_err & (error_frame & (error_cnt1 < 7) |
|
overload_frame & (overload_cnt1 < 7) );
|
overload_frame & (overload_cnt1 < 7) );
|
|
|
// Rule 3 exception 1 - first part (Fault confinement).
|
// Rule 3 exception 1 - first part (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rule3_exc1_1 <= 1'b0;
|
rule3_exc1_1 <= 1'b0;
|
else if (reset_mode | error_flag_over | rule3_exc1_2)
|
else if (reset_mode | error_flag_over | rule3_exc1_2)
|
rule3_exc1_1 <=#Tp 1'b0;
|
rule3_exc1_1 <=#Tp 1'b0;
|
else if (transmitter & node_error_passive & ack_err)
|
else if (transmitter & node_error_passive & ack_err)
|
rule3_exc1_1 <=#Tp 1'b1;
|
rule3_exc1_1 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Rule 3 exception 1 - second part (Fault confinement).
|
// Rule 3 exception 1 - second part (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rule3_exc1_2 <= 1'b0;
|
rule3_exc1_2 <= 1'b0;
|
else if (reset_mode | error_flag_over)
|
else if (reset_mode | error_flag_over)
|
rule3_exc1_2 <=#Tp 1'b0;
|
rule3_exc1_2 <=#Tp 1'b0;
|
else if (rule3_exc1_1)
|
else if (rule3_exc1_1)
|
rule3_exc1_2 <=#Tp 1'b1;
|
rule3_exc1_2 <=#Tp 1'b1;
|
else if ((error_cnt1 < 7) & sample_point & (~sampled_bit))
|
else if ((error_cnt1 < 7) & sample_point & (~sampled_bit))
|
rule3_exc1_2 <=#Tp 1'b0;
|
rule3_exc1_2 <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// Rule 3 exception 2 (Fault confinement).
|
// Rule 3 exception 2 (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rule3_exc2 <= 1'b0;
|
rule3_exc2 <= 1'b0;
|
else if (reset_mode | error_flag_over)
|
else if (reset_mode | error_flag_over)
|
rule3_exc2 <=#Tp 1'b0;
|
rule3_exc2 <=#Tp 1'b0;
|
else if (transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))
|
else if (transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))
|
rule3_exc2 <=#Tp 1'b1;
|
rule3_exc2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
stuff_err_latched <= 1'b0;
|
stuff_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
stuff_err_latched <=#Tp 1'b0;
|
stuff_err_latched <=#Tp 1'b0;
|
else if (stuff_err)
|
else if (stuff_err)
|
stuff_err_latched <=#Tp 1'b1;
|
stuff_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
form_err_latched <= 1'b0;
|
form_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
form_err_latched <=#Tp 1'b0;
|
form_err_latched <=#Tp 1'b0;
|
else if (form_err)
|
else if (form_err)
|
form_err_latched <=#Tp 1'b1;
|
form_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Instantiation of the RX CRC module
|
// Instantiation of the RX CRC module
|
can_crc i_can_crc_rx
|
can_crc i_can_crc_rx
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.data(sampled_bit),
|
.data(sampled_bit),
|
.enable(crc_enable & sample_point & (~bit_de_stuff)),
|
.enable(crc_enable & sample_point & (~bit_de_stuff)),
|
.initialize(go_crc_enable),
|
.initialize(go_crc_enable),
|
.crc(calculated_crc)
|
.crc(calculated_crc)
|
);
|
);
|
|
|
|
|
|
|
|
|
assign no_byte0 = rtr1 | (data_len<1);
|
assign no_byte0 = rtr1 | (data_len<1);
|
assign no_byte1 = rtr1 | (data_len<2);
|
assign no_byte1 = rtr1 | (data_len<2);
|
|
|
can_acf i_can_acf
|
can_acf i_can_acf
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
|
|
.id(id),
|
.id(id),
|
|
|
/* Mode register */
|
/* Mode register */
|
.reset_mode(reset_mode),
|
.reset_mode(reset_mode),
|
.acceptance_filter_mode(acceptance_filter_mode),
|
.acceptance_filter_mode(acceptance_filter_mode),
|
|
|
// Clock Divider register
|
// Clock Divider register
|
.extended_mode(extended_mode),
|
.extended_mode(extended_mode),
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
.acceptance_code_0(acceptance_code_0),
|
.acceptance_code_0(acceptance_code_0),
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
.acceptance_mask_0(acceptance_mask_0),
|
.acceptance_mask_0(acceptance_mask_0),
|
/* End: This section is for BASIC and EXTENDED mode */
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
/* This section is for EXTENDED mode */
|
/* This section is for EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
.acceptance_code_1(acceptance_code_1),
|
.acceptance_code_1(acceptance_code_1),
|
.acceptance_code_2(acceptance_code_2),
|
.acceptance_code_2(acceptance_code_2),
|
.acceptance_code_3(acceptance_code_3),
|
.acceptance_code_3(acceptance_code_3),
|
|
|
/* Acceptance mask register */
|
/* Acceptance mask register */
|
.acceptance_mask_1(acceptance_mask_1),
|
.acceptance_mask_1(acceptance_mask_1),
|
.acceptance_mask_2(acceptance_mask_2),
|
.acceptance_mask_2(acceptance_mask_2),
|
.acceptance_mask_3(acceptance_mask_3),
|
.acceptance_mask_3(acceptance_mask_3),
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_inter(go_rx_inter),
|
.go_rx_inter(go_rx_inter),
|
.go_error_frame(go_error_frame),
|
.go_error_frame(go_error_frame),
|
|
|
.data0(tmp_fifo[0]),
|
.data0(tmp_fifo[0]),
|
.data1(tmp_fifo[1]),
|
.data1(tmp_fifo[1]),
|
.rtr1(rtr1),
|
.rtr1(rtr1),
|
.rtr2(rtr2),
|
.rtr2(rtr2),
|
.ide(ide),
|
.ide(ide),
|
.no_byte0(no_byte0),
|
.no_byte0(no_byte0),
|
.no_byte1(no_byte1),
|
.no_byte1(no_byte1),
|
|
|
.id_ok(id_ok)
|
.id_ok(id_ok)
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign storing_header = header_cnt < header_len;
|
assign storing_header = header_cnt < header_len;
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + header_len)) | reset_mode;
|
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + header_len)) | reset_mode;
|
|
|
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
|
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
|
|
|
|
|
|
|
// Write enable signal for 64-byte rx fifo
|
// Write enable signal for 64-byte rx fifo
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
wr_fifo <= 1'b0;
|
wr_fifo <= 1'b0;
|
else if (reset_wr_fifo)
|
else if (reset_wr_fifo)
|
wr_fifo <=#Tp 1'b0;
|
wr_fifo <=#Tp 1'b0;
|
else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
|
else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
|
wr_fifo <=#Tp 1'b1;
|
wr_fifo <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Header counter. Header length depends on the mode of operation and frame format.
|
// Header counter. Header length depends on the mode of operation and frame format.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
header_cnt <= 0;
|
header_cnt <= 0;
|
else if (reset_wr_fifo)
|
else if (reset_wr_fifo)
|
header_cnt <=#Tp 0;
|
header_cnt <=#Tp 0;
|
else if (wr_fifo & storing_header)
|
else if (wr_fifo & storing_header)
|
header_cnt <=#Tp header_cnt + 1;
|
header_cnt <=#Tp header_cnt + 1;
|
end
|
end
|
|
|
|
|
// Data counter. Length of the data is limited to 8 bytes.
|
// Data counter. Length of the data is limited to 8 bytes.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_cnt <= 0;
|
data_cnt <= 0;
|
else if (reset_wr_fifo)
|
else if (reset_wr_fifo)
|
data_cnt <=#Tp 0;
|
data_cnt <=#Tp 0;
|
else if (wr_fifo)
|
else if (wr_fifo)
|
data_cnt <=#Tp data_cnt + 1;
|
data_cnt <=#Tp data_cnt + 1;
|
end
|
end
|
|
|
|
|
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
|
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
|
always @ (extended_mode or ide or data_cnt or header_cnt or header_len or
|
always @ (extended_mode or ide or data_cnt or header_cnt or header_len or
|
storing_header or id or rtr1 or rtr2 or data_len or
|
storing_header or id or rtr1 or rtr2 or data_len or
|
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
|
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
|
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
|
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
|
begin
|
begin
|
if (storing_header)
|
if (storing_header)
|
begin
|
begin
|
if (extended_mode) // extended mode
|
if (extended_mode) // extended mode
|
begin
|
begin
|
if (ide) // extended format
|
if (ide) // extended format
|
begin
|
begin
|
case (header_cnt) /* synthesis full_case parallel_case */
|
case (header_cnt) /* synthesis full_case parallel_case */
|
3'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
|
3'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
|
3'h1 : data_for_fifo <= id[28:21];
|
3'h1 : data_for_fifo <= id[28:21];
|
3'h2 : data_for_fifo <= id[20:13];
|
3'h2 : data_for_fifo <= id[20:13];
|
3'h3 : data_for_fifo <= id[12:5];
|
3'h3 : data_for_fifo <= id[12:5];
|
3'h4 : data_for_fifo <= {id[4:0], 3'h0};
|
3'h4 : data_for_fifo <= {id[4:0], 3'h0};
|
endcase
|
endcase
|
end
|
end
|
else // standard format
|
else // standard format
|
begin
|
begin
|
case (header_cnt) /* synthesis full_case parallel_case */
|
case (header_cnt) /* synthesis full_case parallel_case */
|
3'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
|
3'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
|
3'h1 : data_for_fifo <= id[10:3];
|
3'h1 : data_for_fifo <= id[10:3];
|
3'h2 : data_for_fifo <= {id[2:0], 5'h0};
|
3'h2 : data_for_fifo <= {id[2:0], 5'h0};
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else // normal mode
|
else // normal mode
|
begin
|
begin
|
case (header_cnt) /* synthesis full_case parallel_case */
|
case (header_cnt) /* synthesis full_case parallel_case */
|
3'h0 : data_for_fifo <= id[10:3];
|
3'h0 : data_for_fifo <= id[10:3];
|
3'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
|
3'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else
|
else
|
data_for_fifo <= tmp_fifo[data_cnt-header_len];
|
data_for_fifo <= tmp_fifo[data_cnt-header_len];
|
end
|
end
|
|
|
|
|
|
|
|
|
// Instantiation of the RX fifo module
|
// Instantiation of the RX fifo module
|
can_fifo i_can_fifo
|
can_fifo i_can_fifo
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
|
|
.wr(wr_fifo),
|
.wr(wr_fifo),
|
|
|
.data_in(data_for_fifo),
|
.data_in(data_for_fifo),
|
.addr(addr),
|
.addr(addr),
|
.data_out(data_out),
|
.data_out(data_out),
|
.fifo_selected(fifo_selected),
|
.fifo_selected(fifo_selected),
|
|
|
.reset_mode(reset_mode),
|
.reset_mode(reset_mode),
|
.release_buffer(release_buffer),
|
.release_buffer(release_buffer),
|
.extended_mode(extended_mode),
|
.extended_mode(extended_mode),
|
.overrun(overrun),
|
.overrun(overrun),
|
.info_empty(info_empty),
|
.info_empty(info_empty),
|
.info_cnt(rx_message_counter)
|
.info_cnt(rx_message_counter)
|
|
|
`ifdef CAN_BIST
|
`ifdef CAN_BIST
|
,
|
,
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
.scanb_si(scanb_si),
|
.scanb_si(scanb_si),
|
.scanb_so(scanb_so),
|
.scanb_so(scanb_so),
|
.scanb_en(scanb_en)
|
.scanb_en(scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
|
|
// Transmitting error frame.
|
// Transmitting error frame.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_frame <= 1'b0;
|
error_frame <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
error_frame <=#Tp 1'b0;
|
error_frame <=#Tp 1'b0;
|
else if (go_error_frame)
|
else if (go_error_frame)
|
error_frame <=#Tp 1'b1;
|
error_frame <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (sample_point)
|
if (sample_point)
|
error_frame_q <=#Tp error_frame;
|
error_frame_q <=#Tp error_frame;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt1 <= 1'b0;
|
error_cnt1 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt1 <=#Tp 1'b0;
|
error_cnt1 <=#Tp 1'b0;
|
else if (error_frame & tx_point & (error_cnt1 < 7))
|
else if (error_frame & tx_point & (error_cnt1 < 7))
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 7) | node_error_passive & sample_point & (passive_cnt == 5)) & (~enable_error_cnt2);
|
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 7) | node_error_passive & sample_point & (passive_cnt == 5)) & (~enable_error_cnt2);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_flag_over_blocked <= 1'b0;
|
error_flag_over_blocked <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_flag_over_blocked <=#Tp 1'b0;
|
error_flag_over_blocked <=#Tp 1'b0;
|
else if (error_flag_over)
|
else if (error_flag_over)
|
error_flag_over_blocked <=#Tp 1'b1;
|
error_flag_over_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_error_cnt2 <= 1'b0;
|
enable_error_cnt2 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
enable_error_cnt2 <=#Tp 1'b0;
|
enable_error_cnt2 <=#Tp 1'b0;
|
else if (error_frame & (error_flag_over & sampled_bit))
|
else if (error_frame & (error_flag_over & sampled_bit))
|
enable_error_cnt2 <=#Tp 1'b1;
|
enable_error_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt2 <= 0;
|
error_cnt2 <= 0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt2 <=#Tp 0;
|
error_cnt2 <=#Tp 0;
|
else if (enable_error_cnt2 & tx_point)
|
else if (enable_error_cnt2 & tx_point)
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
delayed_dominant_cnt <= 0;
|
delayed_dominant_cnt <= 0;
|
else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
|
else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
|
delayed_dominant_cnt <=#Tp 0;
|
delayed_dominant_cnt <=#Tp 0;
|
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 7) | (overload_cnt1 == 7)))
|
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 7) | (overload_cnt1 == 7)))
|
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
|
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
// passive_cnt
|
// passive_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
passive_cnt <= 0;
|
passive_cnt <= 0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
passive_cnt <=#Tp 0;
|
passive_cnt <=#Tp 0;
|
else if (sample_point & (passive_cnt < 5))
|
else if (sample_point & (passive_cnt < 5))
|
begin
|
begin
|
if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
else
|
else
|
passive_cnt <=#Tp 0;
|
passive_cnt <=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
// Transmitting overload frame.
|
// Transmitting overload frame.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_frame <= 1'b0;
|
overload_frame <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
overload_frame <=#Tp 1'b0;
|
overload_frame <=#Tp 1'b0;
|
else if (go_overload_frame)
|
else if (go_overload_frame)
|
overload_frame <=#Tp 1'b1;
|
overload_frame <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt1 <= 1'b0;
|
overload_cnt1 <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt1 <=#Tp 1'b0;
|
overload_cnt1 <=#Tp 1'b0;
|
else if (overload_frame & tx_point & (overload_cnt1 < 7))
|
else if (overload_frame & tx_point & (overload_cnt1 < 7))
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
end
|
end
|
|
|
|
|
assign overload_flag_over = sample_point & (overload_cnt1 == 7) & (~enable_overload_cnt2);
|
assign overload_flag_over = sample_point & (overload_cnt1 == 7) & (~enable_overload_cnt2);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_overload_cnt2 <= 1'b0;
|
enable_overload_cnt2 <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
enable_overload_cnt2 <=#Tp 1'b0;
|
enable_overload_cnt2 <=#Tp 1'b0;
|
else if (overload_frame & (overload_flag_over & sampled_bit))
|
else if (overload_frame & (overload_flag_over & sampled_bit))
|
enable_overload_cnt2 <=#Tp 1'b1;
|
enable_overload_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt2 <= 0;
|
overload_cnt2 <= 0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt2 <=#Tp 0;
|
overload_cnt2 <=#Tp 0;
|
else if (enable_overload_cnt2 & tx_point)
|
else if (enable_overload_cnt2 & tx_point)
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_frame_blocked <= 0;
|
overload_frame_blocked <= 0;
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
overload_frame_blocked <=#Tp 0;
|
overload_frame_blocked <=#Tp 0;
|
else if (go_overload_frame & overload_frame) // This is a second sequential overload
|
else if (go_overload_frame & overload_frame) // This is a second sequential overload
|
overload_frame_blocked <=#Tp 1'b1;
|
overload_frame_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
|
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx <= 1'b1;
|
tx <= 1'b1;
|
else if (reset_mode) // Reset
|
else if (reset_mode) // Reset
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
else if (tx_point)
|
else if (tx_point)
|
begin
|
begin
|
if (tx_state) // Transmitting message
|
if (tx_state) // Transmitting message
|
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
else if (send_ack) // Acknowledge
|
else if (send_ack) // Acknowledge
|
tx <=#Tp 1'b0;
|
tx <=#Tp 1'b0;
|
else if (overload_frame) // Transmitting overload frame
|
else if (overload_frame) // Transmitting overload frame
|
begin
|
begin
|
if (overload_cnt1 < 6)
|
if (overload_cnt1 < 6)
|
tx <=#Tp 1'b0;
|
tx <=#Tp 1'b0;
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
end
|
end
|
else if (error_frame) // Transmitting error frame
|
else if (error_frame) // Transmitting error frame
|
begin
|
begin
|
if (error_cnt1 < 6)
|
if (error_cnt1 < 6)
|
begin
|
begin
|
if (node_error_passive)
|
if (node_error_passive)
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
else
|
else
|
tx <=#Tp 1'b0;
|
tx <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (tx_point)
|
if (tx_point)
|
tx_q <=#Tp tx & (~go_early_tx_latched);
|
tx_q <=#Tp tx & (~go_early_tx_latched);
|
end
|
end
|
|
|
|
|
/* Delayed tx point */
|
/* Delayed tx point */
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
tx_point_q <=#Tp tx_point;
|
tx_point_q <=#Tp tx_point;
|
end
|
end
|
|
|
|
|
/* Changing bit order from [7:0] to [0:7] */
|
/* Changing bit order from [7:0] to [0:7] */
|
can_ibo i_ibo_tx_data_0 (.di(tx_data_0), .do(r_tx_data_0));
|
can_ibo i_ibo_tx_data_0 (.di(tx_data_0), .do(r_tx_data_0));
|
can_ibo i_ibo_tx_data_1 (.di(tx_data_1), .do(r_tx_data_1));
|
can_ibo i_ibo_tx_data_1 (.di(tx_data_1), .do(r_tx_data_1));
|
can_ibo i_ibo_tx_data_2 (.di(tx_data_2), .do(r_tx_data_2));
|
can_ibo i_ibo_tx_data_2 (.di(tx_data_2), .do(r_tx_data_2));
|
can_ibo i_ibo_tx_data_3 (.di(tx_data_3), .do(r_tx_data_3));
|
can_ibo i_ibo_tx_data_3 (.di(tx_data_3), .do(r_tx_data_3));
|
can_ibo i_ibo_tx_data_4 (.di(tx_data_4), .do(r_tx_data_4));
|
can_ibo i_ibo_tx_data_4 (.di(tx_data_4), .do(r_tx_data_4));
|
can_ibo i_ibo_tx_data_5 (.di(tx_data_5), .do(r_tx_data_5));
|
can_ibo i_ibo_tx_data_5 (.di(tx_data_5), .do(r_tx_data_5));
|
can_ibo i_ibo_tx_data_6 (.di(tx_data_6), .do(r_tx_data_6));
|
can_ibo i_ibo_tx_data_6 (.di(tx_data_6), .do(r_tx_data_6));
|
can_ibo i_ibo_tx_data_7 (.di(tx_data_7), .do(r_tx_data_7));
|
can_ibo i_ibo_tx_data_7 (.di(tx_data_7), .do(r_tx_data_7));
|
can_ibo i_ibo_tx_data_8 (.di(tx_data_8), .do(r_tx_data_8));
|
can_ibo i_ibo_tx_data_8 (.di(tx_data_8), .do(r_tx_data_8));
|
can_ibo i_ibo_tx_data_9 (.di(tx_data_9), .do(r_tx_data_9));
|
can_ibo i_ibo_tx_data_9 (.di(tx_data_9), .do(r_tx_data_9));
|
can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
|
can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
|
can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
|
can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
|
can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
|
can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
|
|
|
/* Changing bit order from [14:0] to [0:14] */
|
/* Changing bit order from [14:0] to [0:14] */
|
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
|
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
|
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
|
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
|
|
|
|
|
assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
|
assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
|
assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
|
assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
|
assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
|
assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
|
assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
|
assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
|
|
|
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
|
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
|
r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
|
r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
|
finish_msg)
|
finish_msg)
|
begin
|
begin
|
if (extended_mode)
|
if (extended_mode)
|
begin
|
begin
|
if (rx_data) // data stage
|
if (rx_data) // data stage
|
if (r_tx_data_0[0]) // Extended frame
|
if (r_tx_data_0[0]) // Extended frame
|
tx_bit = extended_chain_data_ext[tx_pointer];
|
tx_bit = extended_chain_data_ext[tx_pointer];
|
else
|
else
|
tx_bit = extended_chain_data_std[tx_pointer];
|
tx_bit = extended_chain_data_std[tx_pointer];
|
else if (rx_crc)
|
else if (rx_crc)
|
tx_bit = r_calculated_crc[tx_pointer];
|
tx_bit = r_calculated_crc[tx_pointer];
|
else if (finish_msg)
|
else if (finish_msg)
|
tx_bit = 1'b1;
|
tx_bit = 1'b1;
|
else
|
else
|
begin
|
begin
|
if (r_tx_data_0[0]) // Extended frame
|
if (r_tx_data_0[0]) // Extended frame
|
tx_bit = extended_chain_ext[tx_pointer];
|
tx_bit = extended_chain_ext[tx_pointer];
|
else
|
else
|
tx_bit = extended_chain_std[tx_pointer];
|
tx_bit = extended_chain_std[tx_pointer];
|
end
|
end
|
end
|
end
|
else // Basic mode
|
else // Basic mode
|
begin
|
begin
|
if (rx_data) // data stage
|
if (rx_data) // data stage
|
tx_bit = basic_chain_data[tx_pointer];
|
tx_bit = basic_chain_data[tx_pointer];
|
else if (rx_crc)
|
else if (rx_crc)
|
tx_bit = r_calculated_crc[tx_pointer];
|
tx_bit = r_calculated_crc[tx_pointer];
|
else if (finish_msg)
|
else if (finish_msg)
|
tx_bit = 1'b1;
|
tx_bit = 1'b1;
|
else
|
else
|
tx_bit = basic_chain[tx_pointer];
|
tx_bit = basic_chain[tx_pointer];
|
end
|
end
|
end
|
end
|
|
|
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 38 ) | // arbitration + control for extended format
|
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 38 ) | // arbitration + control for extended format
|
((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 18 ) | // arbitration + control for extended format
|
((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 18 ) | // arbitration + control for extended format
|
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
|
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
|
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
|
( tx_point & rx_crc_lim ) | // crc
|
( tx_point & rx_crc_lim ) | // crc
|
(go_rx_idle ) | // at the end
|
(go_rx_idle ) | // at the end
|
(reset_mode ) |
|
(reset_mode ) |
|
(overload_frame ) |
|
(overload_frame ) |
|
(error_frame ) ;
|
(error_frame ) ;
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_pointer <= 'h0;
|
tx_pointer <= 'h0;
|
else if (rst_tx_pointer)
|
else if (rst_tx_pointer)
|
tx_pointer <=#Tp 'h0;
|
tx_pointer <=#Tp 'h0;
|
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
|
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
|
tx_pointer <=#Tp tx_pointer + 1'b1;
|
tx_pointer <=#Tp tx_pointer + 1'b1;
|
end
|
end
|
|
|
|
|
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
|
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
need_to_tx <= 1'b0;
|
need_to_tx <= 1'b0;
|
else if (tx_successful | reset_mode | (abort_tx & (~transmitting)))
|
else if (tx_successful | reset_mode | (abort_tx & (~transmitting)))
|
need_to_tx <=#Tp 1'h0;
|
need_to_tx <=#Tp 1'h0;
|
else if (tx_request & sample_point)
|
else if (tx_request & sample_point)
|
need_to_tx <=#Tp 1'b1;
|
need_to_tx <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
|
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
|
|
|
|
|
// go_early_tx latched (for proper bit_de_stuff generation)
|
// go_early_tx latched (for proper bit_de_stuff generation)
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
go_early_tx_latched <= 1'b0;
|
go_early_tx_latched <= 1'b0;
|
else if (tx_point_q)
|
else if (tx_point_q)
|
go_early_tx_latched <=#Tp 1'b0;
|
go_early_tx_latched <=#Tp 1'b0;
|
else if (go_early_tx)
|
else if (go_early_tx)
|
go_early_tx_latched <=#Tp 1'b1;
|
go_early_tx_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Tx state
|
// Tx state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_state <= 1'b0;
|
tx_state <= 1'b0;
|
else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
|
else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
|
tx_state <=#Tp 1'b0;
|
tx_state <=#Tp 1'b0;
|
else if (go_tx)
|
else if (go_tx)
|
tx_state <=#Tp 1'b1;
|
tx_state <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Node is a transmitter
|
// Node is a transmitter
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmitter <= 1'b0;
|
transmitter <= 1'b0;
|
else if (go_tx)
|
else if (go_tx)
|
transmitter <=#Tp 1'b1;
|
transmitter <=#Tp 1'b1;
|
else if (reset_mode | go_rx_inter)
|
else if (reset_mode | go_rx_inter)
|
transmitter <=#Tp 1'b0;
|
transmitter <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
// Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
|
// Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
|
// Node might be both transmitter or receiver (sending error or overload frame)
|
// Node might be both transmitter or receiver (sending error or overload frame)
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmitting <= 1'b0;
|
transmitting <= 1'b0;
|
else if (go_error_frame | go_overload_frame | go_tx)
|
else if (go_error_frame | go_overload_frame | go_tx)
|
transmitting <=#Tp 1'b1;
|
transmitting <=#Tp 1'b1;
|
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
|
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
|
transmitting <=#Tp 1'b0;
|
transmitting <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
suspend <= 0;
|
suspend <= 0;
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
suspend <=#Tp 0;
|
suspend <=#Tp 0;
|
else if (go_rx_inter & transmitter & node_error_passive)
|
else if (go_rx_inter & transmitter & node_error_passive)
|
suspend <=#Tp 1'b1;
|
suspend <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
susp_cnt_en <= 0;
|
susp_cnt_en <= 0;
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
susp_cnt_en <=#Tp 0;
|
susp_cnt_en <=#Tp 0;
|
else if (suspend & sample_point & last_bit_of_inter)
|
else if (suspend & sample_point & last_bit_of_inter)
|
susp_cnt_en <=#Tp 1'b1;
|
susp_cnt_en <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
susp_cnt <= 0;
|
susp_cnt <= 0;
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
else if (reset_mode | (sample_point & (susp_cnt == 7)))
|
susp_cnt <=#Tp 0;
|
susp_cnt <=#Tp 0;
|
else if (susp_cnt_en & sample_point)
|
else if (susp_cnt_en & sample_point)
|
susp_cnt <=#Tp susp_cnt + 1'b1;
|
susp_cnt <=#Tp susp_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
finish_msg <= 1'b0;
|
finish_msg <= 1'b0;
|
else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
|
else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
|
finish_msg <=#Tp 1'b0;
|
finish_msg <=#Tp 1'b0;
|
else if (go_rx_crc_lim)
|
else if (go_rx_crc_lim)
|
finish_msg <=#Tp 1'b1;
|
finish_msg <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_lost <= 1'b0;
|
arbitration_lost <= 1'b0;
|
else if (go_rx_idle | error_frame | reset_mode)
|
else if (go_rx_idle | error_frame | reset_mode)
|
arbitration_lost <=#Tp 1'b0;
|
arbitration_lost <=#Tp 1'b0;
|
else if (tx_state & sample_point & tx & arbitration_field)
|
else if (tx_state & sample_point & tx & arbitration_field)
|
arbitration_lost <=#Tp (~sampled_bit);
|
arbitration_lost <=#Tp (~sampled_bit);
|
end
|
end
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
arbitration_lost_q <=#Tp arbitration_lost;
|
arbitration_lost_q <=#Tp arbitration_lost;
|
end
|
end
|
|
|
|
|
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
|
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_cnt_en <= 1'b0;
|
arbitration_cnt_en <= 1'b0;
|
else if (arbitration_blocked)
|
else if (arbitration_blocked)
|
arbitration_cnt_en <=#Tp 1'b0;
|
arbitration_cnt_en <=#Tp 1'b0;
|
else if (rx_id1 & sample_point & (~arbitration_blocked))
|
else if (rx_id1 & sample_point & (~arbitration_blocked))
|
arbitration_cnt_en <=#Tp 1'b1;
|
arbitration_cnt_en <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_blocked <= 1'b0;
|
arbitration_blocked <= 1'b0;
|
else if (read_arbitration_lost_capture_reg)
|
else if (read_arbitration_lost_capture_reg)
|
arbitration_blocked <=#Tp 1'b0;
|
arbitration_blocked <=#Tp 1'b0;
|
else if (set_arbitration_lost_irq)
|
else if (set_arbitration_lost_irq)
|
arbitration_blocked <=#Tp 1'b1;
|
arbitration_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_lost_capture <= 5'h0;
|
arbitration_lost_capture <= 5'h0;
|
else if (read_arbitration_lost_capture_reg)
|
else if (read_arbitration_lost_capture_reg)
|
arbitration_lost_capture <=#Tp 5'h0;
|
arbitration_lost_capture <=#Tp 5'h0;
|
else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
|
else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
|
arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
|
arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_err_cnt <= 'h0;
|
rx_err_cnt <= 'h0;
|
else if (we_rx_err_cnt & (~node_bus_off))
|
else if (we_rx_err_cnt & (~node_bus_off))
|
rx_err_cnt <=#Tp {1'b0, data_in};
|
rx_err_cnt <=#Tp {1'b0, data_in};
|
else if (set_reset_mode)
|
else if (set_reset_mode)
|
rx_err_cnt <=#Tp 'h0;
|
rx_err_cnt <=#Tp 'h0;
|
else
|
else
|
begin
|
begin
|
if (~listen_only_mode)
|
if (~listen_only_mode)
|
begin
|
begin
|
if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
|
if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
|
begin
|
begin
|
if (rx_err_cnt > 127)
|
if (rx_err_cnt > 127)
|
rx_err_cnt <=#Tp 127;
|
rx_err_cnt <=#Tp 127;
|
else
|
else
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
end
|
end
|
else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
|
else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
|
begin
|
begin
|
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
|
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
|
(go_error_frame & rule5 ) | // 5
|
(go_error_frame & rule5 ) | // 5
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
|
)
|
)
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_err_cnt <= 'h0;
|
tx_err_cnt <= 'h0;
|
else if (we_tx_err_cnt)
|
else if (we_tx_err_cnt)
|
tx_err_cnt <=#Tp {1'b0, data_in};
|
tx_err_cnt <=#Tp {1'b0, data_in};
|
else
|
else
|
begin
|
begin
|
if (set_reset_mode)
|
if (set_reset_mode)
|
tx_err_cnt <=#Tp 127;
|
tx_err_cnt <=#Tp 127;
|
else if ((tx_err_cnt > 0) & (tx_successful | bus_free))
|
else if ((tx_err_cnt > 0) & (tx_successful | bus_free))
|
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
else if (transmitter)
|
else if (transmitter)
|
begin
|
begin
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
|
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
)
|
)
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_err_cnt_blocked <= 1'b0;
|
rx_err_cnt_blocked <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended)
|
rx_err_cnt_blocked <=#Tp 1'b0;
|
rx_err_cnt_blocked <=#Tp 1'b0;
|
else if (sample_point & (error_cnt1 == 7))
|
else if (sample_point & (error_cnt1 == 7))
|
rx_err_cnt_blocked <=#Tp 1'b1;
|
rx_err_cnt_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
node_error_passive <= 1'b0;
|
node_error_passive <= 1'b0;
|
else if ((rx_err_cnt < 128) & (tx_err_cnt < 128) & error_frame_ended)
|
else if ((rx_err_cnt < 128) & (tx_err_cnt < 128) & error_frame_ended)
|
node_error_passive <=#Tp 1'b0;
|
node_error_passive <=#Tp 1'b0;
|
else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
|
else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
|
node_error_passive <=#Tp 1'b1;
|
node_error_passive <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
assign node_error_active = ~(node_error_passive | node_bus_off);
|
assign node_error_active = ~(node_error_passive | node_bus_off);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
node_bus_off <= 1'b0;
|
node_bus_off <= 1'b0;
|
else if ((rx_err_cnt == 0) & (tx_err_cnt == 0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 255)))
|
else if ((rx_err_cnt == 0) & (tx_err_cnt == 0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 255)))
|
node_bus_off <=#Tp 1'b0;
|
node_bus_off <=#Tp 1'b0;
|
else if ((tx_err_cnt >= 256) | (we_tx_err_cnt & (data_in == 255)))
|
else if ((tx_err_cnt >= 256) | (we_tx_err_cnt & (data_in == 255)))
|
node_bus_off <=#Tp 1'b1;
|
node_bus_off <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free_cnt <= 0;
|
bus_free_cnt <= 0;
|
else if (reset_mode)
|
else if (reset_mode)
|
bus_free_cnt <=#Tp 0;
|
bus_free_cnt <=#Tp 0;
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 10))
|
if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 10))
|
bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
|
bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
|
else
|
else
|
bus_free_cnt <=#Tp 0;
|
bus_free_cnt <=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free_cnt_en <= 1'b0;
|
bus_free_cnt_en <= 1'b0;
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
bus_free_cnt_en <=#Tp 1'b1;
|
bus_free_cnt_en <=#Tp 1'b1;
|
else if (sample_point & (bus_free_cnt==10) & (~node_bus_off))
|
else if (sample_point & (bus_free_cnt==10) & (~node_bus_off))
|
bus_free_cnt_en <=#Tp 1'b0;
|
bus_free_cnt_en <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free <= 1'b0;
|
bus_free <= 1'b0;
|
else if (sample_point & sampled_bit & (bus_free_cnt==10))
|
else if (sample_point & sampled_bit & (bus_free_cnt==10))
|
bus_free <=#Tp 1'b1;
|
bus_free <=#Tp 1'b1;
|
else
|
else
|
bus_free <=#Tp 1'b0;
|
bus_free <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
waiting_for_bus_free <= 1'b1;
|
waiting_for_bus_free <= 1'b1;
|
else if (bus_free & (~node_bus_off))
|
else if (bus_free & (~node_bus_off))
|
waiting_for_bus_free <=#Tp 1'b0;
|
waiting_for_bus_free <=#Tp 1'b0;
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
waiting_for_bus_free <=#Tp 1'b1;
|
waiting_for_bus_free <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
assign tx_oen = node_bus_off;
|
assign tx_oen = node_bus_off;
|
|
|
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
|
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
|
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
|
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
|
((rx_err_cnt >= 96) | (tx_err_cnt >= 96)) ;
|
((rx_err_cnt >= 96) | (tx_err_cnt >= 96)) ;
|
|
|
assign transmit_status = transmitting | (extended_mode & waiting_for_bus_free);
|
assign transmit_status = transmitting | (extended_mode & waiting_for_bus_free);
|
assign receive_status = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
|
assign receive_status = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
|
|
|
|
|
/* Error code capture register */
|
/* Error code capture register */
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_capture_code <= 8'h0;
|
error_capture_code <= 8'h0;
|
else if (read_error_code_capture_reg)
|
else if (read_error_code_capture_reg)
|
error_capture_code <=#Tp 8'h0;
|
error_capture_code <=#Tp 8'h0;
|
else if (set_bus_error_irq)
|
else if (set_bus_error_irq)
|
error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
|
error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
|
end
|
end
|
|
|
|
|
|
|
assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
|
assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
|
assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
|
assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
|
assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
|
assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
|
assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
|
assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
|
assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
|
assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
|
assign error_capture_code_direction = ~transmitting;
|
assign error_capture_code_direction = ~transmitting;
|
|
|
|
|
always @ (bit_err or form_err or stuff_err)
|
always @ (bit_err or form_err or stuff_err)
|
begin
|
begin
|
if (bit_err)
|
if (bit_err)
|
error_capture_code_type[7:6] <= 2'b00;
|
error_capture_code_type[7:6] <= 2'b00;
|
else if (form_err)
|
else if (form_err)
|
error_capture_code_type[7:6] <= 2'b01;
|
error_capture_code_type[7:6] <= 2'b01;
|
else if (stuff_err)
|
else if (stuff_err)
|
error_capture_code_type[7:6] <= 2'b10;
|
error_capture_code_type[7:6] <= 2'b10;
|
else
|
else
|
error_capture_code_type[7:6] <= 2'b11;
|
error_capture_code_type[7:6] <= 2'b11;
|
end
|
end
|
|
|
|
|
assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
|
assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_capture_code_blocked <= 1'b0;
|
error_capture_code_blocked <= 1'b0;
|
else if (read_error_code_capture_reg)
|
else if (read_error_code_capture_reg)
|
error_capture_code_blocked <=#Tp 1'b0;
|
error_capture_code_blocked <=#Tp 1'b0;
|
else if (set_bus_error_irq)
|
else if (set_bus_error_irq)
|
error_capture_code_blocked <=#Tp 1'b1;
|
error_capture_code_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|