//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_defines.v ////
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//// can_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// from Bosch. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2004/02/08 14:28:03 mohor
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// Header changed.
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//
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// Revision 1.12 2003/10/17 05:55:20 markom
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// Revision 1.12 2003/10/17 05:55:20 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.11 2003/09/05 12:46:42 mohor
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// Revision 1.11 2003/09/05 12:46:42 mohor
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// ALTERA_RAM supported.
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// ALTERA_RAM supported.
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//
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//
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// Revision 1.10 2003/08/14 16:04:52 simons
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// Revision 1.10 2003/08/14 16:04:52 simons
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// Artisan ram instances added.
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// Artisan ram instances added.
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//
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//
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// Revision 1.9 2003/06/27 20:56:15 simons
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// Revision 1.9 2003/06/27 20:56:15 simons
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// Virtual silicon ram instances added.
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// Virtual silicon ram instances added.
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//
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//
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// Revision 1.8 2003/06/09 11:32:36 mohor
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// Revision 1.8 2003/06/09 11:32:36 mohor
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// Ports added for the CAN_BIST.
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// Ports added for the CAN_BIST.
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//
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//
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// Revision 1.7 2003/03/20 16:51:55 mohor
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// Revision 1.7 2003/03/20 16:51:55 mohor
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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// Revision 1.6 2003/03/12 04:19:13 mohor
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// Revision 1.6 2003/03/12 04:19:13 mohor
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// 8051 interface added (besides WISHBONE interface). Selection is made in
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// 8051 interface added (besides WISHBONE interface). Selection is made in
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// can_defines.v file.
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// can_defines.v file.
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//
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//
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// Revision 1.5 2003/03/05 15:03:20 mohor
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// Revision 1.5 2003/03/05 15:03:20 mohor
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// Xilinx RAM added.
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// Xilinx RAM added.
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//
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//
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// Revision 1.4 2003/03/01 22:52:47 mohor
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// Revision 1.4 2003/03/01 22:52:47 mohor
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// Actel APA ram supported.
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// Actel APA ram supported.
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//
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//
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// Revision 1.3 2003/02/09 02:24:33 mohor
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// Revision 1.3 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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// still need to be fixed.
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//
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//
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// Revision 1.2 2002/12/27 00:12:52 mohor
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// Revision 1.2 2002/12/27 00:12:52 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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//
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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// Initial
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//
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//
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//
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//
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//
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//
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// Uncomment following line if you want to use WISHBONE interface. Otherwise
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// Uncomment following line if you want to use WISHBONE interface. Otherwise
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// 8051 interface is used.
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// 8051 interface is used.
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// `define CAN_WISHBONE_IF
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// `define CAN_WISHBONE_IF
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// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
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// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
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`define ACTEL_APA_RAM
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// `define ACTEL_APA_RAM
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// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
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// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
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// `define ALTERA_RAM
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// `define ALTERA_RAM
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// `define XILINX_RAM
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// `define XILINX_RAM
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// Uncomment the line for the ram used in ASIC implementation
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// Uncomment the line for the ram used in ASIC implementation
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// `define VIRTUALSILICON_RAM
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// `define VIRTUALSILICON_RAM
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// `define ARTISAN_RAM
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// `define ARTISAN_RAM
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
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//`define CAN_BIST // Bist (for ASIC implementation)
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//`define CAN_BIST // Bist (for ASIC implementation)
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/* width of MBIST control bus */
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/* width of MBIST control bus */
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`define CAN_MBIST_CTRL_WIDTH 3
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//`define CAN_MBIST_CTRL_WIDTH 3
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No newline at end of file
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No newline at end of file
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