//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_testbench.v ////
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//// can_testbench.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
|
//// ////
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//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/01/08 02:09:43 mohor
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|
// Acceptance filter added.
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//
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Backup version.
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// Backup version.
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//
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//
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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//
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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// Testbench define file added. Clock divider register added.
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//
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//
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// Revision 1.4 2002/12/26 01:33:01 mohor
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// Revision 1.4 2002/12/26 01:33:01 mohor
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// Tripple sampling supported.
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// Tripple sampling supported.
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//
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//
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// Revision 1.3 2002/12/25 23:44:12 mohor
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// Revision 1.3 2002/12/25 23:44:12 mohor
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// Commented lines removed.
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// Commented lines removed.
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//
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//
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// Revision 1.2 2002/12/25 14:16:54 mohor
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// Revision 1.2 2002/12/25 14:16:54 mohor
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// Synchronization working.
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// Synchronization working.
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//
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//
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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// Initial
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//
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "can_defines.v"
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`include "can_defines.v"
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`include "can_testbench_defines.v"
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`include "can_testbench_defines.v"
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module can_testbench();
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module can_testbench();
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parameter Tp = 1;
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parameter Tp = 1;
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parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
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parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
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reg clk;
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reg clk;
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reg rst;
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reg rst;
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reg [7:0] data_in;
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reg [7:0] data_in;
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wire [7:0] data_out;
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wire [7:0] data_out;
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reg cs, rw;
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reg cs, rw;
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reg [7:0] addr;
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reg [7:0] addr;
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reg rx;
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reg rx;
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integer start_tb;
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integer start_tb;
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reg [7:0] tmp_data;
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// Instantiate can_top module
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// Instantiate can_top module
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can_top i_can_top
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can_top i_can_top
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(
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(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.data_in(data_in),
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.data_in(data_in),
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.data_out(data_out),
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.data_out(data_out),
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.cs(cs),
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.cs(cs),
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.rw(rw),
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.rw(rw),
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.addr(addr),
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.addr(addr),
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.rx(rx)
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.rx(rx)
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);
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);
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// Generate clock signal 24 MHz
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// Generate clock signal 24 MHz
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initial
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initial
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begin
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begin
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clk=0;
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clk=0;
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forever #20 clk = ~clk;
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forever #20 clk = ~clk;
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end
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end
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initial
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initial
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begin
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begin
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start_tb = 0;
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start_tb = 0;
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data_in = 'hz;
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data_in = 'hz;
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cs = 0;
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cs = 0;
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rw = 'hz;
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rw = 'hz;
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addr = 'hz;
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addr = 'hz;
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rx = 1;
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rx = 1;
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rst = 1;
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rst = 1;
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#200 rst = 0;
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#200 rst = 0;
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#200 start_tb = 1;
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#200 start_tb = 1;
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end
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end
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// Main testbench
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// Main testbench
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initial
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initial
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begin
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begin
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wait(start_tb);
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wait(start_tb);
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// Set bus timing register 0
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// Set bus timing register 0
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write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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// Set bus timing register 1
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// Set bus timing register 1
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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// Set Clock Divider register
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// Set Clock Divider register
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write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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begin
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// Set Acceptance Code and Acceptance Mask registers
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// Set Acceptance Code and Acceptance Mask registers
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write_register(8'h16, 8'ha6); // acceptance code 0
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write_register(8'h16, 8'ha6); // acceptance code 0
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write_register(8'h17, 8'hb0); // acceptance code 1
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write_register(8'h17, 8'hb0); // acceptance code 1
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write_register(8'h18, 8'h12); // acceptance code 2
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write_register(8'h18, 8'h12); // acceptance code 2
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write_register(8'h19, 8'h34); // acceptance code 3
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write_register(8'h19, 8'h34); // acceptance code 3
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write_register(8'h20, 8'h0); // acceptance mask 0
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write_register(8'h20, 8'h0); // acceptance mask 0
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write_register(8'h21, 8'h0); // acceptance mask 1
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write_register(8'h21, 8'h0); // acceptance mask 1
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write_register(8'h22, 8'h0); // acceptance mask 2
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write_register(8'h22, 8'h0); // acceptance mask 2
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write_register(8'h23, 8'h0); // acceptance mask 3
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write_register(8'h23, 8'h0); // acceptance mask 3
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end
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end
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else
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else
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begin
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begin
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// Set Acceptance Code and Acceptance Mask registers
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// Set Acceptance Code and Acceptance Mask registers
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write_register(8'h4, 8'ha6); // acceptance code
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write_register(8'h4, 8'ha6); // acceptance code
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write_register(8'h5, 8'h00); // acceptance mask
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write_register(8'h5, 8'h00); // acceptance mask
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end
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end
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#10;
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#10;
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repeat (1000) @ (posedge clk);
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repeat (1000) @ (posedge clk);
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|
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// Switch-off reset mode
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// Switch-off reset mode
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write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
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write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
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repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
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repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
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// This difference is resynchronized later.
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// This difference is resynchronized later.
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repeat (7) send_bit(1); // Sending EOF
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repeat (7) send_bit(1); // Sending EOF
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// test_synchronization;
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// test_synchronization;
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
|
begin
|
send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
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// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
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end
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end
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else
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else
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begin
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begin
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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end
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end
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repeat (50000) @ (posedge clk);
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repeat (50000) @ (posedge clk);
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|
|
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read_register(8'h4);
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read_register(8'h20);
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read_register(8'h21);
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read_register(8'h22);
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read_register(8'h23);
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read_register(8'h24);
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read_register(8'h25);
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$display("CAN Testbench finished.");
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$display("CAN Testbench finished.");
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$stop;
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$stop;
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end
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end
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task read_register;
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input [7:0] reg_addr;
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begin
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@ (posedge clk);
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#1;
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addr = reg_addr;
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cs = 1;
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rw = 1;
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@ (posedge clk);
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$display("(%0t) Reading register [0x%0x] = 0x%0x", $time, addr, data_out);
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#1;
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addr = 'hz;
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cs = 0;
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rw = 'hz;
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end
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endtask
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task write_register;
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task write_register;
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input [7:0] reg_addr;
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input [7:0] reg_addr;
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input [7:0] reg_data;
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input [7:0] reg_data;
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|
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begin
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begin
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@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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addr = reg_addr;
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addr = reg_addr;
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data_in = reg_data;
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data_in = reg_data;
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cs = 1;
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cs = 1;
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rw = 0;
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rw = 0;
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@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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addr = 'hz;
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addr = 'hz;
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data_in = 'hz;
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data_in = 'hz;
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cs = 0;
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cs = 0;
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rw = 'hz;
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rw = 'hz;
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end
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end
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endtask
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endtask
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|
|
|
|
task test_synchronization;
|
task test_synchronization;
|
begin
|
begin
|
// Hard synchronization
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// Hard synchronization
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#1 rx=0;
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#1 rx=0;
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repeat (2*BRP) @ (posedge clk);
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repeat (2*BRP) @ (posedge clk);
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repeat (8*BRP) @ (posedge clk);
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repeat (8*BRP) @ (posedge clk);
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#1 rx=1;
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#1 rx=1;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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|
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// Resynchronization on time
|
// Resynchronization on time
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#1 rx=0;
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#1 rx=0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
|
#1 rx=1;
|
#1 rx=1;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
|
|
|
// Resynchronization late
|
// Resynchronization late
|
repeat (BRP) @ (posedge clk);
|
repeat (BRP) @ (posedge clk);
|
repeat (BRP) @ (posedge clk);
|
repeat (BRP) @ (posedge clk);
|
#1 rx=0;
|
#1 rx=0;
|
repeat (10*BRP) @ (posedge clk);
|
repeat (10*BRP) @ (posedge clk);
|
#1 rx=1;
|
#1 rx=1;
|
|
|
// Resynchronization early
|
// Resynchronization early
|
repeat (8*BRP) @ (posedge clk); // two frames too early
|
repeat (8*BRP) @ (posedge clk); // two frames too early
|
#1 rx=0;
|
#1 rx=0;
|
repeat (10*BRP) @ (posedge clk);
|
repeat (10*BRP) @ (posedge clk);
|
#1 rx=1;
|
#1 rx=1;
|
repeat (10*BRP) @ (posedge clk);
|
repeat (10*BRP) @ (posedge clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task send_bit;
|
task send_bit;
|
input bit;
|
input bit;
|
integer cnt;
|
integer cnt;
|
begin
|
begin
|
#1 rx=bit;
|
#1 rx=bit;
|
repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
|
repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task send_frame;
|
task send_frame;
|
input mode;
|
input mode;
|
input remote_trans_req;
|
input remote_trans_req;
|
input [28:0] id;
|
input [28:0] id;
|
input [3:0] length;
|
input [3:0] length;
|
input [14:0] crc;
|
input [14:0] crc;
|
integer cnt;
|
integer cnt;
|
|
|
reg [28:0] data;
|
reg [28:0] data;
|
reg [3:0] len;
|
reg [3:0] len;
|
begin
|
begin
|
|
|
data = id;
|
data = id;
|
len = length;
|
len = length;
|
|
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
|
|
if(mode) // Extended format
|
if(mode) // Extended format
|
begin
|
begin
|
for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
|
for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
|
begin
|
begin
|
send_bit(data[28]);
|
send_bit(data[28]);
|
data=data<<1;
|
data=data<<1;
|
end
|
end
|
send_bit(1); // SRR
|
send_bit(1); // SRR
|
send_bit(1); // IDE
|
send_bit(1); // IDE
|
|
|
for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID
|
for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID
|
begin
|
begin
|
send_bit(data[28]);
|
send_bit(data[28]);
|
data=data<<1;
|
data=data<<1;
|
end
|
end
|
|
|
send_bit(remote_trans_req);
|
send_bit(remote_trans_req);
|
send_bit(0); // r1 (reserved 1)
|
send_bit(0); // r1 (reserved 1)
|
send_bit(0); // r0 (reserved 0)
|
send_bit(0); // r0 (reserved 0)
|
|
|
for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
|
for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
|
begin
|
begin
|
send_bit(len[3]);
|
send_bit(len[3]);
|
len=len<<1;
|
len=len<<1;
|
end
|
end
|
end
|
end
|
else // Standard format
|
else // Standard format
|
begin
|
begin
|
for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
|
for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
|
begin
|
begin
|
send_bit(data[10]);
|
send_bit(data[10]);
|
data=data<<1;
|
data=data<<1;
|
end
|
end
|
send_bit(remote_trans_req);
|
send_bit(remote_trans_req);
|
send_bit(0); // IDE
|
send_bit(0); // IDE
|
send_bit(0); // r0 (reserved 0)
|
send_bit(0); // r0 (reserved 0)
|
|
|
for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
|
for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
|
begin
|
begin
|
send_bit(len[3]);
|
send_bit(len[3]);
|
len=len<<1;
|
len=len<<1;
|
end
|
end
|
end // End header
|
end // End header
|
|
|
|
|
if(length) // Send data if length is > 0
|
if(length) // Send data if length is > 0
|
begin
|
begin
|
for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
|
for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
|
begin
|
begin
|
send_bit(cnt[3]);
|
send_bit(cnt[3]);
|
send_bit(cnt[2]);
|
send_bit(cnt[2]);
|
send_bit(cnt[1]);
|
send_bit(cnt[1]);
|
send_bit(cnt[0]);
|
send_bit(cnt[0]);
|
end
|
end
|
end
|
end
|
|
|
// Send CRC
|
// Send CRC
|
data[14:0] = crc[14:0];
|
data[14:0] = crc[14:0];
|
for (cnt=0; cnt<15; cnt=cnt+1) // 15 bit CRC
|
for (cnt=0; cnt<15; cnt=cnt+1) // 15 bit CRC
|
begin
|
begin
|
send_bit(data[14]);
|
send_bit(data[14]);
|
data=data<<1;
|
data=data<<1;
|
end
|
end
|
|
|
// Send CRC delimiter
|
// Send CRC delimiter
|
send_bit(1);
|
send_bit(1);
|
|
|
// Send ACK slot
|
// Send ACK slot
|
send_bit(1);
|
send_bit(1);
|
|
|
// Send Ack delimiter
|
// Send Ack delimiter
|
send_bit(1);
|
send_bit(1);
|
|
|
|
|
// Nothing send after the data (just recessive bit)
|
// Nothing send after the data (just recessive bit)
|
send_bit(1);
|
send_bit(1);
|
|
|
|
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// State machine monitor (btl)
|
// State machine monitor (btl)
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
|
if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
|
can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
|
can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
|
begin
|
begin
|
$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
|
$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
|
#1000;
|
#1000;
|
$stop;
|
$stop;
|
end
|
end
|
|
|
if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
|
if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
|
can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
|
can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
|
begin
|
begin
|
$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
|
$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
|
#1000;
|
#1000;
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
/* stuff_error monitor (bsp)
|
/* stuff_error monitor (bsp)
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if(can_testbench.i_can_top.i_can_bsp.stuff_error)
|
if(can_testbench.i_can_top.i_can_bsp.stuff_error)
|
begin
|
begin
|
$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
|
$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
|
$stop; After everything is finished add another condition (something like & (~idle)) and enable stop
|
$stop; After everything is finished add another condition (something like & (~idle)) and enable stop
|
end
|
end
|
end
|
end
|
*/
|
*/
|
|
|
|
|
endmodule
|
endmodule
|
|
|