//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_testbench_defines.v ////
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//// can_testbench_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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// Revision 1.1 2002/12/26 16:00:29 mohor
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// Revision 1.1 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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// Testbench define file added. Clock divider register added.
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//
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//
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//
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//
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//
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//
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//
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//
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// Mode register
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`define CAN_MODE_RESET 1'h1 // Reset mode
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// Bit Timing 0 register value
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// Bit Timing 0 register value
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`define CAN_TIMING0_BRP 6'h1 // Baud rate prescaler (2*(value+1))
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`define CAN_TIMING0_BRP 6'h1 // Baud rate prescaler (2*(value+1))
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`define CAN_TIMING0_SJW 2'h2 // SJW (value+1)
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`define CAN_TIMING0_SJW 2'h2 // SJW (value+1)
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// Bit Timing 1 register value
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// Bit Timing 1 register value
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`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
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`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
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`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
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`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
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`define CAN_TIMING1_SAM 1'h0 // Triple sampling
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`define CAN_TIMING1_SAM 1'h0 // Triple sampling
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