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---------------------------------------------------------------------------------------------------
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--
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--
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-- Title : blockram
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-- Title : blockram
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-- Design : cfft
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-- Design : cfft
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-- Author : MENG Lin
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-- Author : MENG Lin
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-- email :
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-- email :
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- File : blockram.vhd
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-- File : blockram.vhd
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-- Generated : unknown
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-- Generated : unknown
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--
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--
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description : Dual port ram
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-- Description : Dual port ram
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--
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library synplify;
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library synplify;
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use synplify.attributes.all;
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use synplify.attributes.all;
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entity blockdram is
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entity blockdram is
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generic(
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generic(
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depth: integer;
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depth: integer;
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Dwidth: integer;
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Dwidth: integer;
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Awidth: integer
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Awidth: integer
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);
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);
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port(
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port(
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addra: IN std_logic_VECTOR(Awidth-1 downto 0);
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addra: IN std_logic_VECTOR(Awidth-1 downto 0);
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clka: IN std_logic;
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clka: IN std_logic;
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addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
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addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
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clkb: IN std_logic;
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clkb: IN std_logic;
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dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
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dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
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wea: IN std_logic;
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wea: IN std_logic;
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dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
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dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
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end blockdram;
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end blockdram;
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architecture arch_blockdram of blockdram is
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architecture arch_blockdram of blockdram is
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type ram_memtype is array (depth-1 downto 0) of std_logic_vector
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type ram_memtype is array (depth-1 downto 0) of std_logic_vector
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(Dwidth-1 downto 0);
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(Dwidth-1 downto 0);
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signal mem : ram_memtype := (others => (others => '0'));
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signal mem : ram_memtype := (others => (others => '0'));
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attribute syn_ramstyle of mem : signal is "block_ram";
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attribute syn_ramstyle of mem : signal is "block_ram";
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signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
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signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
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begin
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begin
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wr: process( clka )
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wr: process( clka )
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begin
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begin
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if rising_edge(clka) then
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if rising_edge(clka) then
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if wea = '1' then
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if wea = '1' then
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mem(conv_integer(addra)) <= dia;
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mem(conv_integer(addra)) <= dia;
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end if;
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end if;
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end if;
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end if;
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end process wr;
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end process wr;
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rd: process( clkb )
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rd: process( clkb )
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begin
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begin
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if rising_edge(clkb) then
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if rising_edge(clkb) then
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addrb_reg <= addrb;
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addrb_reg <= addrb;
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end if;
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end if;
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end process rd;
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end process rd;
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dob <= mem(conv_integer(addrb_reg));
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dob <= mem(conv_integer(addrb_reg));
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end arch_blockdram;
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end arch_blockdram;
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