---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Title : cfft
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-- Title : cfft
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-- Design : cfft
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-- Design : cfft
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-- Author : ZHAO Ming
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-- Author : ZHAO Ming
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-- email : sradio@opencores.org
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-- email : sradio@opencores.org
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- File : cfft.vhd
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-- File : cfft.vhd
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-- Generated : Thu Oct 3 03:03:58 2002
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-- Generated : Thu Oct 3 03:03:58 2002
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description : 4-based 1024 point FFT input 12 bit Output 14 bit with
|
-- Description : 4-based 1024 point FFT input 12 bit Output 14 bit with
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-- limit and overfall processing internal
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-- limit and overfall processing internal
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--
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--
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-- The gain is 0.0287 for FFT and 29.4 for IFFT
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-- The gain is 0.0287 for FFT and 29.4 for IFFT
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--
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--
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-- The output is 4-based reversed ordered, it means
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-- The output is 4-based reversed ordered, it means
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-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
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-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
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--
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--
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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|
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|
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- port :
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-- port :
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-- clk : main clk -- I have test 90M with Xilinx virtex600E
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-- clk : main clk -- I have test 90M with Xilinx virtex600E
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-- rst : globe reset -- '1' for reset
|
-- rst : globe reset -- '1' for reset
|
-- start : start fft -- one clock '1' before data input
|
-- start : start fft -- one clock '1' before data input
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-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
|
-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
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-- Iin,Qin : data input-- following start immediately, input data
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-- Iin,Qin : data input-- following start immediately, input data
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-- -- power should not be too big
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-- -- power should not be too big
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-- inputbusy : if it change to '0' then next fft is enable
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-- inputbusy : if it change to '0' then next fft is enable
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-- outdataen : when it is '1', the valid data is output
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-- outdataen : when it is '1', the valid data is output
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-- Iout,Qout : fft data output when outdataen is '1'
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-- Iout,Qout : fft data output when outdataen is '1'
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
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-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 1.1.0
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-- Version : 1.1.0
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-- Date : Oct 17 2002
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-- Date : Oct 17 2002
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-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : Data width configurable
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-- Desccription : Data width configurable
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
|
-- Revision Number : 2
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-- Revision Number : 2
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-- Version : 1.2.0
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-- Version : 1.2.0
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-- Date : Oct 18 2002
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-- Date : Oct 18 2002
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-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
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-- Desccription : Point configurable
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-- Desccription : Point configurable
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-- FFT Gain IFFT GAIN
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-- FFT Gain IFFT GAIN
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-- 256 0.0698 17.9
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-- 256 0.0698 17.9
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-- 1024 0.0287 29.4
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-- 1024 0.0287 29.4
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-- 4096 0.0118 48.2742
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-- 4096 0.0118 48.2742
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--
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--
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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|
|
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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|
|
entity cfft is
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entity cfft is
|
generic (
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generic (
|
WIDTH : Natural;
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WIDTH : Natural;
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POINT : Natural;
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POINT : Natural;
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STAGE : Natural -- STAGE=log4(POINT)
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STAGE : Natural -- STAGE=log4(POINT)
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);
|
);
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port(
|
port(
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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inv : in std_logic;
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inv : in std_logic;
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Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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inputbusy : out STD_LOGIC;
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inputbusy : out STD_LOGIC;
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outdataen : out STD_LOGIC;
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outdataen : out STD_LOGIC;
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
|
);
|
);
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end cfft;
|
end cfft;
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|
|
|
|
architecture cfft of cfft is
|
architecture cfft of cfft is
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|
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component address
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component address
|
generic (
|
generic (
|
WIDTH : Natural;
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WIDTH : Natural;
|
POINT : Natural;
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POINT : Natural;
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STAGE : Natural
|
STAGE : Natural
|
);
|
);
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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Iin : in std_logic_vector( WIDTH-1 downto 0 );
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Iin : in std_logic_vector( WIDTH-1 downto 0 );
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Qin : in std_logic_vector( WIDTH-1 downto 0 );
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Qin : in std_logic_vector( WIDTH-1 downto 0 );
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fftI : in std_logic_vector( WIDTH-1 downto 0 );
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fftI : in std_logic_vector( WIDTH-1 downto 0 );
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fftQ : in std_logic_vector( WIDTH-1 downto 0 );
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fftQ : in std_logic_vector( WIDTH-1 downto 0 );
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wdataI : out std_logic_vector( WIDTH-1 downto 0 );
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wdataI : out std_logic_vector( WIDTH-1 downto 0 );
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wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
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wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
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raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
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wen : out std_logic;
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wen : out std_logic;
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factorstart : out STD_LOGIC;
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factorstart : out STD_LOGIC;
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cfft4start : out STD_LOGIC;
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cfft4start : out STD_LOGIC;
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outdataen : out std_logic;
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outdataen : out std_logic;
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inputbusy : out std_logic
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inputbusy : out std_logic
|
);
|
);
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end component;
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end component;
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|
|
component blockdram
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component blockdram
|
generic(
|
generic(
|
depth: integer;
|
depth: integer;
|
Dwidth: integer;
|
Dwidth: integer;
|
Awidth: integer
|
Awidth: integer
|
);
|
);
|
port(
|
port(
|
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
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addra: IN std_logic_VECTOR(Awidth-1 downto 0);
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clka: IN std_logic;
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clka: IN std_logic;
|
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
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addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
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clkb: IN std_logic;
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clkb: IN std_logic;
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dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
|
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
|
wea: IN std_logic;
|
wea: IN std_logic;
|
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
|
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
|
end component;
|
end component;
|
|
|
component cfft4
|
component cfft4
|
generic (
|
generic (
|
WIDTH : Natural
|
WIDTH : Natural
|
);
|
);
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
start : in STD_LOGIC;
|
start : in STD_LOGIC;
|
inv : in std_logic;
|
inv : in std_logic;
|
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
|
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
|
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
|
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
|
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
|
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
|
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
|
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component div4limit
|
component div4limit
|
generic (
|
generic (
|
WIDTH : Natural
|
WIDTH : Natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
|
D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
|
Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
|
Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component mulfactor
|
component mulfactor
|
generic (
|
generic (
|
WIDTH : Natural;
|
WIDTH : Natural;
|
STAGE : Natural
|
STAGE : Natural
|
);
|
);
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
angle : in signed(2*STAGE-1 downto 0);
|
angle : in signed(2*STAGE-1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Qout : out signed(WIDTH+3 downto 0)
|
Qout : out signed(WIDTH+3 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component rofactor
|
component rofactor
|
generic (
|
generic (
|
POINT : Natural;
|
POINT : Natural;
|
STAGE : Natural
|
STAGE : Natural
|
);
|
);
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
start : in STD_LOGIC;
|
start : in STD_LOGIC;
|
inv : in std_logic;
|
inv : in std_logic;
|
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
|
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
signal wea,cfft4start,factorstart:std_logic:='0';
|
signal wea,cfft4start,factorstart:std_logic:='0';
|
signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
|
signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
|
signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
|
signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
|
signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
|
signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
|
signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
|
signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
|
signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
|
signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
|
signal inv_reg:std_logic:='0';
|
signal inv_reg:std_logic:='0';
|
|
|
begin
|
begin
|
|
|
Aaddress:address
|
Aaddress:address
|
generic map (
|
generic map (
|
WIDTH=>WIDTH,
|
WIDTH=>WIDTH,
|
POINT=>POINT,
|
POINT=>POINT,
|
STAGE=>STAGE
|
STAGE=>STAGE
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
rst=>rst,
|
rst=>rst,
|
start=>start,
|
start=>start,
|
Iin=>Iin,
|
Iin=>Iin,
|
Qin=>Qin,
|
Qin=>Qin,
|
fftI=>fftI,
|
fftI=>fftI,
|
fftQ=>fftQ,
|
fftQ=>fftQ,
|
wdataI=>wdataI,
|
wdataI=>wdataI,
|
wdataQ=>wdataQ,
|
wdataQ=>wdataQ,
|
raddr=>raddr,
|
raddr=>raddr,
|
waddr=>waddr,
|
waddr=>waddr,
|
wen=>wea,
|
wen=>wea,
|
factorstart=>factorstart,
|
factorstart=>factorstart,
|
cfft4start=>cfft4start,
|
cfft4start=>cfft4start,
|
outdataen=>outdataen,
|
outdataen=>outdataen,
|
inputbusy=>inputbusy
|
inputbusy=>inputbusy
|
);
|
);
|
|
|
Iram:blockdram
|
Iram:blockdram
|
generic map (
|
generic map (
|
depth=>POINT,
|
depth=>POINT,
|
Dwidth=>WIDTH,
|
Dwidth=>WIDTH,
|
Awidth=>2*STAGE
|
Awidth=>2*STAGE
|
)
|
)
|
port map (
|
port map (
|
addra=>waddr,
|
addra=>waddr,
|
clka=>clk,
|
clka=>clk,
|
addrb=>raddr,
|
addrb=>raddr,
|
clkb=>clk,
|
clkb=>clk,
|
dia=>wdataI,
|
dia=>wdataI,
|
wea=>wea,
|
wea=>wea,
|
dob=>Iramout
|
dob=>Iramout
|
);
|
);
|
|
|
Qram:blockdram
|
Qram:blockdram
|
generic map (
|
generic map (
|
depth=>POINT,
|
depth=>POINT,
|
Dwidth=>WIDTH,
|
Dwidth=>WIDTH,
|
Awidth=>2*STAGE
|
Awidth=>2*STAGE
|
)
|
)
|
port map (
|
port map (
|
addra=>waddr,
|
addra=>waddr,
|
clka=>clk,
|
clka=>clk,
|
addrb=>raddr,
|
addrb=>raddr,
|
clkb=>clk,
|
clkb=>clk,
|
dia=>wdataQ,
|
dia=>wdataQ,
|
wea=>wea,
|
wea=>wea,
|
dob=>Qramout
|
dob=>Qramout
|
);
|
);
|
|
|
acfft4:cfft4
|
acfft4:cfft4
|
generic map (
|
generic map (
|
WIDTH=>WIDTH
|
WIDTH=>WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
rst=>rst,
|
rst=>rst,
|
start=>cfft4start,
|
start=>cfft4start,
|
inv=>inv_reg,
|
inv=>inv_reg,
|
I=>Iramout,
|
I=>Iramout,
|
Q=>Qramout,
|
Q=>Qramout,
|
Iout=>Icfft4out,
|
Iout=>Icfft4out,
|
Qout=>Qcfft4out
|
Qout=>Qcfft4out
|
);
|
);
|
|
|
Iout<=Icfft4out;
|
Iout<=Icfft4out;
|
Qout<=Qcfft4out;
|
Qout<=Qcfft4out;
|
|
|
Ilimit:div4limit
|
Ilimit:div4limit
|
generic map (
|
generic map (
|
WIDTH=>WIDTH
|
WIDTH=>WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
D=>std_logic_vector(Imulout),
|
D=>std_logic_vector(Imulout),
|
Q=>fftI
|
Q=>fftI
|
);
|
);
|
Qlimit:div4limit
|
Qlimit:div4limit
|
generic map (
|
generic map (
|
WIDTH=>WIDTH
|
WIDTH=>WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
D=>std_logic_vector(Qmulout),
|
D=>std_logic_vector(Qmulout),
|
Q=>fftQ
|
Q=>fftQ
|
);
|
);
|
|
|
amulfactor:mulfactor
|
amulfactor:mulfactor
|
generic map (
|
generic map (
|
WIDTH=>WIDTH,
|
WIDTH=>WIDTH,
|
STAGE=>STAGE
|
STAGE=>STAGE
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
rst=>rst,
|
rst=>rst,
|
angle=>signed(angle),
|
angle=>signed(angle),
|
I=>signed(Icfft4out),
|
I=>signed(Icfft4out),
|
Q=>signed(Qcfft4out),
|
Q=>signed(Qcfft4out),
|
Iout=>Imulout,
|
Iout=>Imulout,
|
Qout=>Qmulout
|
Qout=>Qmulout
|
);
|
);
|
|
|
arofactor:rofactor
|
arofactor:rofactor
|
generic map (
|
generic map (
|
POINT=>POINT,
|
POINT=>POINT,
|
STAGE=>STAGE
|
STAGE=>STAGE
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
rst=>rst,
|
rst=>rst,
|
start=>factorstart,
|
start=>factorstart,
|
inv=>inv_reg,
|
inv=>inv_reg,
|
angle=>angle
|
angle=>angle
|
);
|
);
|
|
|
process( clk, rst )
|
process( clk, rst )
|
begin
|
begin
|
if rst='1' then
|
if rst='1' then
|
inv_reg<='0';
|
inv_reg<='0';
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
if start='1' then
|
if start='1' then
|
inv_reg<=inv;
|
inv_reg<=inv;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
end cfft;
|
end cfft;
|
|
|
