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--
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--
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-- Title : test bench
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-- Title : test bench
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-- Design : cfft
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-- Design : cfft
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-- Author : henning larsen
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-- Author : henning larsen
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-- email :
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-- email :
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- File : tb_cfft1024x12.vhd
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-- File : tb_cfft1024x12.vhd
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description :
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-- Description :
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--
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--
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-- Simple "testbench" for cfft1024x12. It is realy just an excitation of inputs
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-- Simple "testbench" for cfft1024x12. It is realy just an excitation of inputs
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-- The output has to be evaluated manually. run for 125 us with current settings.
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-- The output has to be evaluated manually. run for 125 us with current settings.
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-- Input is a dual sinsoid with constant amplitudes, and a DC value.
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-- Input is a dual sinsoid with constant amplitudes, and a DC value.
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-- Input is real valued only. A calculation of the power spectrum, and a frequency bin
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-- Input is real valued only. A calculation of the power spectrum, and a frequency bin
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-- counter is included, but no reordering of output sequence is performed.
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-- counter is included, but no reordering of output sequence is performed.
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-- Frequencies are easy to select such that a minimum of spill into side bins is obtained.
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-- Frequencies are easy to select such that a minimum of spill into side bins is obtained.
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-- Beware of the posibilty of saturation in the output. For single sinsoide,the saturation limit
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-- Beware of the posibilty of saturation in the output. For single sinsoide,the saturation limit
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-- is 2^14/29.4=557 units of input amplitude.
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-- is 2^14/29.4=557 units of input amplitude.
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--
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--
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-- henning larsen
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-- henning larsen
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
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-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 1.1.0
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-- Version : 1.1.0
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-- Date : Nov 21 2002
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-- Date : Nov 21 2002
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-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : init release
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-- Desccription : init release
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-- compare output position
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-- compare output position
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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USE ieee.math_real.all;
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USE ieee.math_real.all;
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USE ieee.std_logic_signed.all;
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USE ieee.std_logic_signed.all;
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ENTITY cfft1024x12_tester1 IS
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ENTITY cfft1024x12_tester1 IS
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END cfft1024x12_tester1 ;
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END cfft1024x12_tester1 ;
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ARCHITECTURE tester OF cfft1024x12_tester1 IS
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ARCHITECTURE tester OF cfft1024x12_tester1 IS
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-- Component Declarations
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-- Component Declarations
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COMPONENT cfft1024X12
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COMPONENT cfft1024X12
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PORT (
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PORT (
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clk : IN STD_LOGIC ;
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clk : IN STD_LOGIC ;
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rst : IN STD_LOGIC ;
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rst : IN STD_LOGIC ;
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start : IN STD_LOGIC ;
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start : IN STD_LOGIC ;
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invert : IN std_logic ;
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invert : IN std_logic ;
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Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
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Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
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Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
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Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
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inputbusy : OUT STD_LOGIC ;
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inputbusy : OUT STD_LOGIC ;
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outdataen : OUT STD_LOGIC ;
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outdataen : OUT STD_LOGIC ;
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Iout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
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Iout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
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Qout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
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Qout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
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OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
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OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
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);
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);
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END COMPONENT;
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END COMPONENT;
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constant Tck_half : time:=10 ns;
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constant Tck_half : time:=10 ns;
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constant Tckhalf : real:=10.0e-9;-- real value eqv of time, there is some conversion function
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constant Tckhalf : real:=10.0e-9;-- real value eqv of time, there is some conversion function
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-- for this but could not find/remember.
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-- for this but could not find/remember.
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constant ampl1 : real:=100.0;-- max amplitude is roughly 550=2^14/29.4 to avoid sturation in output
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constant ampl1 : real:=100.0;-- max amplitude is roughly 550=2^14/29.4 to avoid sturation in output
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constant ampl2 : real:=200.0; -- .. but see intro comments
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constant ampl2 : real:=200.0; -- .. but see intro comments
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constant f1 : real := 100.0/TckHalf/2.0/1024.0;-- bin number =100
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constant f1 : real := 100.0/TckHalf/2.0/1024.0;-- bin number =100
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constant f2 : real := 33.0/TckHalf/2.0/1024.0;-- bin number =33
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constant f2 : real := 33.0/TckHalf/2.0/1024.0;-- bin number =33
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constant dc : real:=100.0;--bin number=0
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constant dc : real:=100.0;--bin number=0
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signal c1,c2,cout: real;
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signal c1,c2,cout: real;
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signal clock : std_logic:='0';
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signal clock : std_logic:='0';
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signal reset : std_logic:='0';
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signal reset : std_logic:='0';
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signal start : std_logic:='0';
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signal start : std_logic:='0';
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signal invert : std_logic ;
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signal invert : std_logic ;
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signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
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signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
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signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
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signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
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signal inputbusy : STD_LOGIC:='0' ;
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signal inputbusy : STD_LOGIC:='0' ;
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signal outdataen : STD_LOGIC:='0' ;
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signal outdataen : STD_LOGIC:='0' ;
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signal Iout : STD_LOGIC_VECTOR (13 DOWNTO 0);
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signal Iout : STD_LOGIC_VECTOR (13 DOWNTO 0);
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signal Qout : STD_LOGIC_VECTOR (13 DOWNTO 0);
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signal Qout : STD_LOGIC_VECTOR (13 DOWNTO 0);
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signal amp : real; -- power spectrum
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signal amp : real; -- power spectrum
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signal bitRev : STD_LOGIC_VECTOR (9 DOWNTO 0);-- bin counter
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signal bitRev : STD_LOGIC_VECTOR (9 DOWNTO 0);-- bin counter
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signal OutPosition : STD_LOGIC_VECTOR( 9 downto 0 );
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signal OutPosition : STD_LOGIC_VECTOR( 9 downto 0 );
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BEGIN
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BEGIN
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-- Instance port mappings.
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-- Instance port mappings.
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I0 : cfft1024X12
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I0 : cfft1024X12
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PORT MAP (
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PORT MAP (
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clk => clock,
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clk => clock,
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rst => reset,
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rst => reset,
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start => start,
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start => start,
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invert => invert,
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invert => invert,
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Iin => Iin,
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Iin => Iin,
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Qin => Qin,
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Qin => Qin,
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inputbusy => inputbusy,
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inputbusy => inputbusy,
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outdataen => outdataen,
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outdataen => outdataen,
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Iout => Iout,
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Iout => Iout,
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Qout => Qout,
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Qout => Qout,
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OutPosition => OutPosition
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OutPosition => OutPosition
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);
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);
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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--
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--
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-- control signals ,setup
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-- control signals ,setup
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clock <= not clock after Tck_half;
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clock <= not clock after Tck_half;
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reset <= '1', '0' after 2*Tck_half;
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reset <= '1', '0' after 2*Tck_half;
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start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only one FFT is done
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start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only one FFT is done
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invert <= '0';-- FFT
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invert <= '0';-- FFT
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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--
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--
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sin_gen: process(clock, reset)
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sin_gen: process(clock, reset)
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variable tid : real;
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variable tid : real;
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variable TM : real :=0.0 ;
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variable TM : real :=0.0 ;
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begin
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begin
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if Reset = '1' then
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if Reset = '1' then
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c1 <= 0.0;
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c1 <= 0.0;
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c2 <= 0.0;
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c2 <= 0.0;
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Iin<="000000000000" ;
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Iin<="000000000000" ;
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Qin<="000000000000" ;
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Qin<="000000000000" ;
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TM := 0.0;
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TM := 0.0;
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tid := TM;
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tid := TM;
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else
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else
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if clock'event and clock = '1' then
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if clock'event and clock = '1' then
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TM := TM + Tckhalf*2.0;
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TM := TM + Tckhalf*2.0;
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tid := TM;
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tid := TM;
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c1 <= (ampl1 * sin(2.0*math_pi*f1*tid));
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c1 <= (ampl1 * sin(2.0*math_pi*f1*tid));
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c2 <= (ampl2 * sin(2.0*math_pi*f2*tid));
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c2 <= (ampl2 * sin(2.0*math_pi*f2*tid));
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cout <= c1+c2+dc;
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cout <= c1+c2+dc;
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Iin <= conv_std_logic_vector(integer(cout),Iin'length);
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Iin <= conv_std_logic_vector(integer(cout),Iin'length);
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Qin <="000000000000" ;
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Qin <="000000000000" ;
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end if;
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end if;
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end if;
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end if;
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end process sin_gen;
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end process sin_gen;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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--
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--
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--Output power spectrum, normalized with the gain of 29.4
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--Output power spectrum, normalized with the gain of 29.4
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amp <= sqrt(real(CONV_integer(Iout)) * real(CONV_integer(Iout))
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amp <= sqrt(real(CONV_integer(Iout)) * real(CONV_integer(Iout))
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+ real(CONV_integer(Qout)) * real(CONV_integer(Qout)))/29.4;
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+ real(CONV_integer(Qout)) * real(CONV_integer(Qout)))/29.4;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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--
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--
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-- radix 4 bit reversed counter
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-- radix 4 bit reversed counter
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radix4cnt: process (clock)
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radix4cnt: process (clock)
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variable cntr: std_logic_vector ( 9 downto 0);
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variable cntr: std_logic_vector ( 9 downto 0);
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begin
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begin
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if rising_edge(clock) then
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if rising_edge(clock) then
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if outdataen='1' then
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if outdataen='1' then
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cntr:=unsigned(cntr)+1;
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cntr:=unsigned(cntr)+1;
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else
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else
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cntr:=(others => '0');
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cntr:=(others => '0');
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end if;
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end if;
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for k in 1 to ((10) / 2) loop
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for k in 1 to ((10) / 2) loop
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bitRev(2*k-2)<= cntr(10-2*k);
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bitRev(2*k-2)<= cntr(10-2*k);
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bitRev(2*k-1)<= cntr(10-(-1+2*k));
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bitRev(2*k-1)<= cntr(10-(-1+2*k));
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end loop;
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end loop;
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end if;
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end if;
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end process radix4cnt;
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end process radix4cnt;
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END tester;
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END tester;
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