//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Generic Single-Port Synchronous RAM ////
|
//// Generic Single-Port Synchronous RAM ////
|
//// ////
|
//// ////
|
//// This file is part of memory library available from ////
|
//// This file is part of memory library available from ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// This block is a wrapper with common single-port ////
|
//// This block is a wrapper with common single-port ////
|
//// synchronous memory interface for different ////
|
//// synchronous memory interface for different ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// interface it also provides a behavioral model of generic ////
|
//// interface it also provides a behavioral model of generic ////
|
//// single-port synchronous RAM. ////
|
//// single-port synchronous RAM. ////
|
//// It also contains a synthesizeable model for FPGAs. ////
|
//// It also contains a synthesizeable model for FPGAs. ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// portable accross different target technologies and ////
|
//// portable accross different target technologies and ////
|
//// independent of target memory. ////
|
//// independent of target memory. ////
|
//// ////
|
//// ////
|
//// Supported ASIC RAMs are: ////
|
//// Supported ASIC RAMs are: ////
|
//// - Artisan Single-Port Sync RAM ////
|
//// - Artisan Single-Port Sync RAM ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Generic FPGA (VENDOR_FPGA) ////
|
//// - Generic FPGA (VENDOR_FPGA) ////
|
//// Tested RAMs: Altera, Xilinx ////
|
//// Tested RAMs: Altera, Xilinx ////
|
//// Synthesis tools: LeonardoSpectrum, Synplicity ////
|
//// Synthesis tools: LeonardoSpectrum, Synplicity ////
|
//// - Xilinx (VENDOR_XILINX) ////
|
//// - Xilinx (VENDOR_XILINX) ////
|
//// - Altera (VENDOR_ALTERA) ////
|
//// - Altera (VENDOR_ALTERA) ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - fix avant! two-port ram ////
|
//// - fix avant! two-port ram ////
|
//// - add additional RAMs ////
|
//// - add additional RAMs ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Richard Herveille, richard@asics.ws ////
|
//// - Richard Herveille, richard@asics.ws ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Adding empty directories required by HDL coding guidelines
|
// Adding empty directories required by HDL coding guidelines
|
//
|
//
|
//
|
//
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
|
|
//`define VENDOR_XILINX
|
//`define VENDOR_XILINX
|
//`define VENDOR_ALTERA
|
//`define VENDOR_ALTERA
|
`define VENDOR_FPGA
|
`define VENDOR_FPGA
|
|
|
module generic_spram(
|
module generic_spram(
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
clk, rst, ce, we, oe, addr, di, do
|
clk, rst, ce, we, oe, addr, di, do
|
);
|
);
|
|
|
//
|
//
|
// Default address and data buses width
|
// Default address and data buses width
|
//
|
//
|
parameter aw = 6; //number of address-bits
|
parameter aw = 6; //number of address-bits
|
parameter dw = 8; //number of data-bits
|
parameter dw = 8; //number of data-bits
|
|
|
//
|
//
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
//
|
//
|
input clk; // Clock, rising edge
|
input clk; // Clock, rising edge
|
input rst; // Reset, active high
|
input rst; // Reset, active high
|
input ce; // Chip enable input, active high
|
input ce; // Chip enable input, active high
|
input we; // Write enable input, active high
|
input we; // Write enable input, active high
|
input oe; // Output enable input, active high
|
input oe; // Output enable input, active high
|
input [aw-1:0] addr; // address bus inputs
|
input [aw-1:0] addr; // address bus inputs
|
input [dw-1:0] di; // input data bus
|
input [dw-1:0] di; // input data bus
|
output [dw-1:0] do; // output data bus
|
output [dw-1:0] do; // output data bus
|
|
|
//
|
//
|
// Module body
|
// Module body
|
//
|
//
|
|
|
`ifdef VENDOR_FPGA
|
`ifdef VENDOR_FPGA
|
//
|
//
|
// Instantiation synthesizeable FPGA memory
|
// Instantiation synthesizeable FPGA memory
|
//
|
//
|
// This code has been tested using LeonardoSpectrum and Synplicity.
|
// This code has been tested using LeonardoSpectrum and Synplicity.
|
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
|
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
|
//
|
//
|
reg [dw-1 :0] mem [(1<<aw) -1:0];
|
reg [dw-1 :0] mem [(1<<aw) -1:0];
|
reg [aw-1:0] raddr;
|
reg [aw-1:0] raddr;
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
// read operation
|
// read operation
|
raddr <= #1 addr; // read address needs to be registered to read clock
|
raddr <= #1 addr; // read address needs to be registered to read clock
|
|
|
// write operation
|
// write operation
|
if (we && ce)
|
if (we && ce)
|
mem[addr] <= #1 di;
|
mem[addr] <= #1 di;
|
end
|
end
|
|
|
assign #1 do = mem[raddr];
|
assign #1 do = mem[raddr];
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_XILINX
|
`ifdef VENDOR_XILINX
|
|
|
wire [dw-1:0] q; // output from xilinx ram
|
wire [dw-1:0] q; // output from xilinx ram
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Virtex/Spartan2 BlockRAMs
|
// Virtex/Spartan2 BlockRAMs
|
//
|
//
|
xilinx_ram_sp xilinx_ram(
|
xilinx_ram_sp xilinx_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.addr(addr),
|
.addr(addr),
|
.di(di),
|
.di(di),
|
.en(ce),
|
.en(ce),
|
.we(we),
|
.we(we),
|
.do(do)
|
.do(do)
|
);
|
);
|
|
|
defparam
|
defparam
|
xilinx_ram.dwidth = dw,
|
xilinx_ram.dwidth = dw,
|
xilinx_ram.awidth = aw;
|
xilinx_ram.awidth = aw;
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_ALTERA
|
`ifdef VENDOR_ALTERA
|
|
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Altera FLEX EABs
|
// Altera FLEX EABs
|
//
|
//
|
|
|
altera_ram_sp altera_ram(
|
altera_ram_sp altera_ram(
|
.inclock(clk),
|
.inclock(clk),
|
.address(addr),
|
.address(addr),
|
.data(di),
|
.data(di),
|
.we(we && ce),
|
.we(we && ce),
|
.q(do)
|
.q(do)
|
);
|
);
|
|
|
defparam
|
defparam
|
altera_ram.dwidth = dw,
|
altera_ram.dwidth = dw,
|
altera_ram.awidth = aw;
|
altera_ram.awidth = aw;
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_ARTISAN
|
`ifdef VENDOR_ARTISAN
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Artisan Synchronous Single-Port RAM (ra1sh)
|
// Artisan Synchronous Single-Port RAM (ra1sh)
|
//
|
//
|
artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
|
artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
|
.CLK(clk),
|
.CLK(clk),
|
.CEN(~ce),
|
.CEN(~ce),
|
.WEN(~we),
|
.WEN(~we),
|
.A(addr),
|
.A(addr),
|
.D(di),
|
.D(di),
|
.OEN(~oe),
|
.OEN(~oe),
|
.Q(do)
|
.Q(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_AVANT
|
`ifdef VENDOR_AVANT
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Avant! Asynchronous Two-Port RAM
|
// Avant! Asynchronous Two-Port RAM
|
//
|
//
|
avant_atp avant_atp(
|
avant_atp avant_atp(
|
.web(~we),
|
.web(~we),
|
.reb(),
|
.reb(),
|
.oeb(~oe),
|
.oeb(~oe),
|
.rcsb(),
|
.rcsb(),
|
.wcsb(),
|
.wcsb(),
|
.ra(addr),
|
.ra(addr),
|
.wa(addr),
|
.wa(addr),
|
.di(di),
|
.di(di),
|
.do(do)
|
.do(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_VIRAGE
|
`ifdef VENDOR_VIRAGE
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virage Synchronous 1-port R/W RAM
|
// Virage Synchronous 1-port R/W RAM
|
//
|
//
|
virage_ssp virage_ssp(
|
virage_ssp virage_ssp(
|
.clk(clk),
|
.clk(clk),
|
.adr(addr),
|
.adr(addr),
|
.d(di),
|
.d(di),
|
.we(we),
|
.we(we),
|
.oe(oe),
|
.oe(oe),
|
.me(ce),
|
.me(ce),
|
.q(do)
|
.q(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_VIRTUALSILICON
|
`ifdef VENDOR_VIRTUALSILICON
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virtual Silicon Single-Port Synchronous SRAM
|
// Virtual Silicon Single-Port Synchronous SRAM
|
//
|
//
|
virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
|
virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di),
|
.DI(di),
|
.WEN(~we),
|
.WEN(~we),
|
.CEN(~ce),
|
.CEN(~ce),
|
.OEN(~oe),
|
.OEN(~oe),
|
.DOUT(do)
|
.DOUT(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// Generic single-port synchronous RAM model
|
// Generic single-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
// Generic RAM's registers and wires
|
// Generic RAM's registers and wires
|
//
|
//
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
wire [dw-1:0] q; // RAM output
|
wire [dw-1:0] q; // RAM output
|
reg [aw-1:0] raddr; // RAM read address
|
reg [aw-1:0] raddr; // RAM read address
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do = (oe) ? q : {dw{1'bz}};
|
assign do = (oe) ? q : {dw{1'bz}};
|
|
|
//
|
//
|
// RAM read and write
|
// RAM read and write
|
//
|
//
|
|
|
// read operation
|
// read operation
|
always@(posedge clk)
|
always@(posedge clk)
|
if (ce) // && !we)
|
if (ce) // && !we)
|
raddr <= #1 addr; // read address needs to be registered to read clock
|
raddr <= #1 addr; // read address needs to be registered to read clock
|
|
|
assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
|
assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
|
|
|
// write operation
|
// write operation
|
always@(posedge clk)
|
always@(posedge clk)
|
if (ce && we)
|
if (ce && we)
|
mem[addr] <= #1 di;
|
mem[addr] <= #1 di;
|
|
|
|
|
`endif // !VIRTUALSILICON_SSP
|
`endif // !VIRTUALSILICON_SSP
|
`endif // !VIRAGE_SSP
|
`endif // !VIRAGE_SSP
|
`endif // !AVANT_ATP
|
`endif // !AVANT_ATP
|
`endif // !ARTISAN_SSP
|
`endif // !ARTISAN_SSP
|
`endif // !VENDOR_ALTERA
|
`endif // !VENDOR_ALTERA
|
`endif // !VENDOR_XILINX
|
`endif // !VENDOR_XILINX
|
`endif // !VENDOR_FPGA
|
`endif // !VENDOR_FPGA
|
|
|
endmodule
|
endmodule
|
|
|
|
|
//
|
//
|
// Black-box modules
|
// Black-box modules
|
//
|
//
|
|
|
`ifdef VENDOR_ALTERA
|
`ifdef VENDOR_ALTERA
|
module altera_ram_sp (
|
module altera_ram_sp (
|
address,
|
address,
|
inclock,
|
inclock,
|
we,
|
we,
|
data,
|
data,
|
q) /* synthesis black_box */;
|
q) /* synthesis black_box */;
|
|
|
parameter awidth = 7;
|
parameter awidth = 7;
|
parameter dwidth = 8;
|
parameter dwidth = 8;
|
|
|
input [awidth -1:0] address;
|
input [awidth -1:0] address;
|
input inclock;
|
input inclock;
|
input we;
|
input we;
|
input [dwidth -1:0] data;
|
input [dwidth -1:0] data;
|
output [dwidth -1:0] q;
|
output [dwidth -1:0] q;
|
|
|
// synopsis translate_off
|
// synopsis translate_off
|
// exemplar translate_off
|
// exemplar translate_off
|
|
|
syn_ram_irou #(
|
syn_ram_irou #(
|
"UNUSED",
|
"UNUSED",
|
dwidth,
|
dwidth,
|
awidth,
|
awidth,
|
1 << awidth
|
1 << awidth
|
)
|
)
|
altera_spram_model (
|
altera_spram_model (
|
.Inclock(inclock),
|
.Inclock(inclock),
|
.Address(address),
|
.Address(address),
|
.Data(data),
|
.Data(data),
|
.WE(we),
|
.WE(we),
|
.Q(q)
|
.Q(q)
|
);
|
);
|
|
|
// exemplar translate_on
|
// exemplar translate_on
|
// synopsis translate_on
|
// synopsis translate_on
|
|
|
endmodule
|
endmodule
|
`endif // VENDOR_ALTERA
|
`endif // VENDOR_ALTERA
|
|
|
`ifdef VENDOR_XILINX
|
`ifdef VENDOR_XILINX
|
module xilinx_ram_sp (
|
module xilinx_ram_sp (
|
clk,
|
clk,
|
rst,
|
rst,
|
addr,
|
addr,
|
di,
|
di,
|
en,
|
en,
|
we,
|
we,
|
do) /* synthesis black_box */ ;
|
do) /* synthesis black_box */ ;
|
|
|
parameter awidth = 7;
|
parameter awidth = 7;
|
parameter dwidth = 8;
|
parameter dwidth = 8;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input [awidth -1:0] addr;
|
input [awidth -1:0] addr;
|
input [dwidth -1:0] di;
|
input [dwidth -1:0] di;
|
input en;
|
input en;
|
input we;
|
input we;
|
output [dwidth -1:0] do;
|
output [dwidth -1:0] do;
|
|
|
// insert simulation model
|
// insert simulation model
|
|
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// exemplar translate_off
|
// exemplar translate_off
|
|
|
C_MEM_SP_BLOCK_V1_0 #(
|
C_MEM_SP_BLOCK_V1_0 #(
|
awidth,
|
awidth,
|
1,
|
1,
|
"0",
|
"0",
|
1 << awidth,
|
1 << awidth,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
"",
|
"",
|
16,
|
16,
|
0,
|
0,
|
0,
|
0,
|
1,
|
1,
|
1,
|
1,
|
dwidth
|
dwidth
|
)
|
)
|
xilinx_spram_model (
|
xilinx_spram_model (
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR(addr),
|
.ADDR(addr),
|
.DI(di),
|
.DI(di),
|
.EN(en),
|
.EN(en),
|
.WE(we),
|
.WE(we),
|
.DO(do)
|
.DO(do)
|
);
|
);
|
|
|
// exemplar translate_on
|
// exemplar translate_on
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
endmodule
|
endmodule
|
`endif // VENDOR_XILINX
|
`endif // VENDOR_XILINX
|
|
|
|
|
