//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Generic Dual-Port Synchronous RAM ////
|
//// Generic Dual-Port Synchronous RAM ////
|
//// ////
|
//// ////
|
//// This file is part of memory library available from ////
|
//// This file is part of memory library available from ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// This block is a wrapper with common dual-port ////
|
//// This block is a wrapper with common dual-port ////
|
//// synchronous memory interface for different ////
|
//// synchronous memory interface for different ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// types of ASIC and FPGA RAMs. Beside universal memory ////
|
//// interface it also provides behavioral model of generic ////
|
//// interface it also provides behavioral model of generic ////
|
//// dual-port synchronous RAM. ////
|
//// dual-port synchronous RAM. ////
|
//// It also contains a fully synthesizeable model for FPGAs. ////
|
//// It also contains a fully synthesizeable model for FPGAs. ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// It should be used in all OPENCORES designs that want to be ////
|
//// portable accross different target technologies and ////
|
//// portable accross different target technologies and ////
|
//// independent of target memory. ////
|
//// independent of target memory. ////
|
//// ////
|
//// ////
|
//// Supported ASIC RAMs are: ////
|
//// Supported ASIC RAMs are: ////
|
//// - Artisan Dual-Port Sync RAM ////
|
//// - Artisan Dual-Port Sync RAM ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Virage 2-port Sync RAM ////
|
//// - Virage 2-port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Generic FPGA (VENDOR_FPGA) ////
|
//// - Generic FPGA (VENDOR_FPGA) ////
|
//// Tested RAMs: Altera, Xilinx ////
|
//// Tested RAMs: Altera, Xilinx ////
|
//// Synthesis tools: LeonardoSpectrum, Synplicity ////
|
//// Synthesis tools: LeonardoSpectrum, Synplicity ////
|
//// - Xilinx (VENDOR_XILINX) ////
|
//// - Xilinx (VENDOR_XILINX) ////
|
//// - Altera (VENDOR_ALTERA) ////
|
//// - Altera (VENDOR_ALTERA) ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - fix Avant! ////
|
//// - fix Avant! ////
|
//// - add additional RAMs (VS etc) ////
|
//// - add additional RAMs (VS etc) ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Richard Herveille, richard@asics.ws ////
|
//// - Richard Herveille, richard@asics.ws ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.3 2001/11/09 00:34:18 samg
|
// Revision 1.3 2001/11/09 00:34:18 samg
|
// minor changes: unified with all common rams
|
// minor changes: unified with all common rams
|
//
|
//
|
// Revision 1.2 2001/11/08 19:11:31 samg
|
// Revision 1.2 2001/11/08 19:11:31 samg
|
// added valid checks to behvioral model
|
// added valid checks to behvioral model
|
//
|
//
|
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
|
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
|
// Major cleanup.
|
// Major cleanup.
|
// Files are now compliant to Altera & Xilinx memories.
|
// Files are now compliant to Altera & Xilinx memories.
|
// Memories are now compatible, i.e. drop-in replacements.
|
// Memories are now compatible, i.e. drop-in replacements.
|
// Added synthesizeable generic FPGA description.
|
// Added synthesizeable generic FPGA description.
|
// Created "generic_memories" cvs entry.
|
// Created "generic_memories" cvs entry.
|
//
|
//
|
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
|
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
|
// *** empty log message ***
|
// *** empty log message ***
|
//
|
//
|
// Revision 1.1 2001/08/20 18:23:20 damjan
|
// Revision 1.1 2001/08/20 18:23:20 damjan
|
// Initial revision
|
// Initial revision
|
//
|
//
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
// Major clean-up.
|
// Major clean-up.
|
//
|
//
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Revision 1.2 2001/07/30 05:38:02 lampret
|
// Adding empty directories required by HDL coding guidelines
|
// Adding empty directories required by HDL coding guidelines
|
//
|
//
|
//
|
//
|
|
|
//`include "timescale.v"
|
//`include "timescale.v"
|
|
|
//`define VENDOR_FPGA
|
//`define VENDOR_FPGA
|
//`define VENDOR_XILINX
|
//`define VENDOR_XILINX
|
//`define VENDOR_ALTERA
|
//`define VENDOR_ALTERA
|
|
|
module generic_dpram(
|
module generic_dpram(
|
// Generic synchronous dual-port RAM interface
|
// Generic synchronous dual-port RAM interface
|
rclk, rrst, rce, oe, raddr, do,
|
rclk, rrst, rce, oe, raddr, do,
|
wclk, wrst, wce, we, waddr, di
|
wclk, wrst, wce, we, waddr, di
|
);
|
);
|
|
|
//
|
//
|
// Default address and data buses width
|
// Default address and data buses width
|
//
|
//
|
parameter aw = 5; // number of bits in address-bus
|
parameter aw = 5; // number of bits in address-bus
|
parameter dw = 16; // number of bits in data-bus
|
parameter dw = 16; // number of bits in data-bus
|
|
|
//
|
//
|
// Generic synchronous double-port RAM interface
|
// Generic synchronous double-port RAM interface
|
//
|
//
|
// read port
|
// read port
|
input rclk; // read clock, rising edge trigger
|
input rclk; // read clock, rising edge trigger
|
input rrst; // read port reset, active high
|
input rrst; // read port reset, active high
|
input rce; // read port chip enable, active high
|
input rce; // read port chip enable, active high
|
input oe; // output enable, active high
|
input oe; // output enable, active high
|
input [aw-1:0] raddr; // read address
|
input [aw-1:0] raddr; // read address
|
output [dw-1:0] do; // data output
|
output [dw-1:0] do; // data output
|
|
|
// write port
|
// write port
|
input wclk; // write clock, rising edge trigger
|
input wclk; // write clock, rising edge trigger
|
input wrst; // write port reset, active high
|
input wrst; // write port reset, active high
|
input wce; // write port chip enable, active high
|
input wce; // write port chip enable, active high
|
input we; // write enable, active high
|
input we; // write enable, active high
|
input [aw-1:0] waddr; // write address
|
input [aw-1:0] waddr; // write address
|
input [dw-1:0] di; // data input
|
input [dw-1:0] di; // data input
|
|
|
//
|
//
|
// Module body
|
// Module body
|
//
|
//
|
|
|
`ifdef VENDOR_FPGA
|
`ifdef VENDOR_FPGA
|
//
|
//
|
// Instantiation synthesizeable FPGA memory
|
// Instantiation synthesizeable FPGA memory
|
//
|
//
|
// This code has been tested using LeonardoSpectrum and Synplicity.
|
// This code has been tested using LeonardoSpectrum and Synplicity.
|
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
|
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
|
//
|
//
|
reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory
|
reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory
|
reg [aw-1:0] ra; // register read address
|
reg [aw-1:0] ra; // register read address
|
|
|
// read operation
|
// read operation
|
always @(posedge rclk)
|
always @(posedge rclk)
|
if (rce)
|
if (rce)
|
ra <= #1 raddr;
|
ra <= #1 raddr;
|
|
|
assign do = mem[ra];
|
assign do = mem[ra];
|
|
|
// write operation
|
// write operation
|
always@(posedge wclk)
|
always@(posedge wclk)
|
if (we && wce)
|
if (we && wce)
|
mem[waddr] <= #1 di;
|
mem[waddr] <= #1 di;
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_XILINX
|
`ifdef VENDOR_XILINX
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Virtex/Spartan2 BlockRAMs
|
// Virtex/Spartan2 BlockRAMs
|
//
|
//
|
xilinx_ram_dp xilinx_ram(
|
xilinx_ram_dp xilinx_ram(
|
// read port
|
// read port
|
.CLKA(rclk),
|
.CLKA(rclk),
|
.RSTA(rrst),
|
.RSTA(rrst),
|
.ENA(rce),
|
.ENA(rce),
|
.ADDRA(raddr),
|
.ADDRA(raddr),
|
.DIA( {dw{1'b0}} ),
|
.DIA( {dw{1'b0}} ),
|
.WEA(1'b0),
|
.WEA(1'b0),
|
.DOA(do),
|
.DOA(do),
|
|
|
// write port
|
// write port
|
.CLKB(wclk),
|
.CLKB(wclk),
|
.RSTB(wrst),
|
.RSTB(wrst),
|
.ENB(wce),
|
.ENB(wce),
|
.ADDRB(waddr),
|
.ADDRB(waddr),
|
.DIB(di),
|
.DIB(di),
|
.WEB(we),
|
.WEB(we),
|
.DOB()
|
.DOB()
|
);
|
);
|
|
|
defparam
|
defparam
|
xilinx_ram.dwidth = dw,
|
xilinx_ram.dwidth = dw,
|
xilinx_ram.awidth = aw;
|
xilinx_ram.awidth = aw;
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_ALTERA
|
`ifdef VENDOR_ALTERA
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
// Altera FLEX/APEX EABs
|
// Altera FLEX/APEX EABs
|
//
|
//
|
altera_ram_dp altera_ram(
|
altera_ram_dp altera_ram(
|
// read port
|
// read port
|
.rdclock(rclk),
|
.rdclock(rclk),
|
.rdclocken(rce),
|
.rdclocken(rce),
|
.rdaddress(raddr),
|
.rdaddress(raddr),
|
.q(do),
|
.q(do),
|
|
|
// write port
|
// write port
|
.wrclock(wclk),
|
.wrclock(wclk),
|
.wrclocken(wce),
|
.wrclocken(wce),
|
.wren(we),
|
.wren(we),
|
.wraddress(waddr),
|
.wraddress(waddr),
|
.data(di)
|
.data(di)
|
);
|
);
|
|
|
defparam
|
defparam
|
altera_ram.dwidth = dw,
|
altera_ram.dwidth = dw,
|
altera_ram.awidth = aw;
|
altera_ram.awidth = aw;
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_ARTISAN
|
`ifdef VENDOR_ARTISAN
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Artisan Synchronous Double-Port RAM (ra2sh)
|
// Artisan Synchronous Double-Port RAM (ra2sh)
|
//
|
//
|
art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
|
art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
|
// read port
|
// read port
|
.qa(do),
|
.qa(do),
|
.clka(rclk),
|
.clka(rclk),
|
.cena(~rce),
|
.cena(~rce),
|
.wena(1'b1),
|
.wena(1'b1),
|
.aa(raddr),
|
.aa(raddr),
|
.da( {dw{1'b0}} ),
|
.da( {dw{1'b0}} ),
|
.oena(~oe),
|
.oena(~oe),
|
|
|
// write port
|
// write port
|
.qb(),
|
.qb(),
|
.clkb(wclk),
|
.clkb(wclk),
|
.cenb(~wce),
|
.cenb(~wce),
|
.wenb(~we),
|
.wenb(~we),
|
.ab(waddr),
|
.ab(waddr),
|
.db(di),
|
.db(di),
|
.oenb(1'b1)
|
.oenb(1'b1)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_AVANT
|
`ifdef VENDOR_AVANT
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Avant! Asynchronous Two-Port RAM
|
// Avant! Asynchronous Two-Port RAM
|
//
|
//
|
avant_atp avant_atp(
|
avant_atp avant_atp(
|
.web(~we),
|
.web(~we),
|
.reb(),
|
.reb(),
|
.oeb(~oe),
|
.oeb(~oe),
|
.rcsb(),
|
.rcsb(),
|
.wcsb(),
|
.wcsb(),
|
.ra(raddr),
|
.ra(raddr),
|
.wa(waddr),
|
.wa(waddr),
|
.di(di),
|
.di(di),
|
.do(do)
|
.do(do)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef VENDOR_VIRAGE
|
`ifdef VENDOR_VIRAGE
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virage Synchronous 2-port R/W RAM
|
// Virage Synchronous 2-port R/W RAM
|
//
|
//
|
virage_stp virage_stp(
|
virage_stp virage_stp(
|
// read port
|
// read port
|
.CLKA(rclk),
|
.CLKA(rclk),
|
.MEA(rce_a),
|
.MEA(rce_a),
|
.ADRA(raddr),
|
.ADRA(raddr),
|
.DA( {dw{1'b0}} ),
|
.DA( {dw{1'b0}} ),
|
.WEA(1'b0),
|
.WEA(1'b0),
|
.OEA(oe),
|
.OEA(oe),
|
.QA(do),
|
.QA(do),
|
|
|
// write port
|
// write port
|
.CLKB(wclk),
|
.CLKB(wclk),
|
.MEB(wce),
|
.MEB(wce),
|
.ADRB(waddr),
|
.ADRB(waddr),
|
.DB(di),
|
.DB(di),
|
.WEB(we),
|
.WEB(we),
|
.OEB(1'b1),
|
.OEB(1'b1),
|
.QB()
|
.QB()
|
);
|
);
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// Generic dual-port synchronous RAM model
|
// Generic dual-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
// Generic RAM's registers and wires
|
// Generic RAM's registers and wires
|
//
|
//
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
|
reg [dw-1:0] do_reg; // RAM data output register
|
reg [dw-1:0] do_reg; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do = (oe & rce) ? do_reg : {dw{1'bz}};
|
assign do = (oe & rce) ? do_reg : {dw{1'bz}};
|
|
|
// read operation
|
// read operation
|
always @(posedge rclk)
|
always @(posedge rclk)
|
if (rce)
|
if (rce)
|
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
|
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
|
|
|
// write operation
|
// write operation
|
always @(posedge wclk)
|
always @(posedge wclk)
|
if (wce && we)
|
if (wce && we)
|
mem[waddr] <= #1 di;
|
mem[waddr] <= #1 di;
|
|
|
|
|
// Task prints range of memory
|
// Task prints range of memory
|
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
|
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
|
task print_ram;
|
task print_ram;
|
input [aw-1:0] start;
|
input [aw-1:0] start;
|
input [aw-1:0] finish;
|
input [aw-1:0] finish;
|
integer rnum;
|
integer rnum;
|
begin
|
begin
|
for (rnum=start;rnum<=finish;rnum=rnum+1)
|
for (rnum=start;rnum<=finish;rnum=rnum+1)
|
$display("Addr %h = %h",rnum,mem[rnum]);
|
$display("Addr %h = %h",rnum,mem[rnum]);
|
end
|
end
|
endtask
|
endtask
|
|
|
`endif // !VENDOR_VIRAGE
|
`endif // !VENDOR_VIRAGE
|
`endif // !VENDOR_AVANT
|
`endif // !VENDOR_AVANT
|
`endif // !VENDOR_ARTISAN
|
`endif // !VENDOR_ARTISAN
|
`endif // !VENDOR_ALTERA
|
`endif // !VENDOR_ALTERA
|
`endif // !VENDOR_XILINX
|
`endif // !VENDOR_XILINX
|
`endif // !VENDOR_FPGA
|
`endif // !VENDOR_FPGA
|
|
|
endmodule
|
endmodule
|
|
|
//
|
//
|
// Black-box modules
|
// Black-box modules
|
//
|
//
|
|
|
`ifdef VENDOR_ALTERA
|
`ifdef VENDOR_ALTERA
|
module altera_ram_dp(
|
module altera_ram_dp(
|
data,
|
data,
|
wraddress,
|
wraddress,
|
rdaddress,
|
rdaddress,
|
wren,
|
wren,
|
wrclock,
|
wrclock,
|
wrclocken,
|
wrclocken,
|
rdclock,
|
rdclock,
|
rdclocken,
|
rdclocken,
|
q) /* synthesis black_box */;
|
q) /* synthesis black_box */;
|
|
|
parameter awidth = 7;
|
parameter awidth = 7;
|
parameter dwidth = 8;
|
parameter dwidth = 8;
|
|
|
input [dwidth -1:0] data;
|
input [dwidth -1:0] data;
|
input [awidth -1:0] wraddress;
|
input [awidth -1:0] wraddress;
|
input [awidth -1:0] rdaddress;
|
input [awidth -1:0] rdaddress;
|
input wren;
|
input wren;
|
input wrclock;
|
input wrclock;
|
input wrclocken;
|
input wrclocken;
|
input rdclock;
|
input rdclock;
|
input rdclocken;
|
input rdclocken;
|
output [dwidth -1:0] q;
|
output [dwidth -1:0] q;
|
|
|
// synopsis translate_off
|
// synopsis translate_off
|
// exemplar translate_off
|
// exemplar translate_off
|
|
|
syn_dpram_rowr #(
|
syn_dpram_rowr #(
|
"UNUSED",
|
"UNUSED",
|
dwidth,
|
dwidth,
|
awidth,
|
awidth,
|
1 << awidth
|
1 << awidth
|
)
|
)
|
altera_dpram_model (
|
altera_dpram_model (
|
// read port
|
// read port
|
.RdClock(rdclock),
|
.RdClock(rdclock),
|
.RdClken(rdclocken),
|
.RdClken(rdclocken),
|
.RdAddress(rdaddress),
|
.RdAddress(rdaddress),
|
.RdEn(1'b1),
|
.RdEn(1'b1),
|
.Q(q),
|
.Q(q),
|
|
|
// write port
|
// write port
|
.WrClock(wrclock),
|
.WrClock(wrclock),
|
.WrClken(wrclocken),
|
.WrClken(wrclocken),
|
.WrAddress(wraddress),
|
.WrAddress(wraddress),
|
.WrEn(wren),
|
.WrEn(wren),
|
.Data(data)
|
.Data(data)
|
);
|
);
|
|
|
// exemplar translate_on
|
// exemplar translate_on
|
// synopsis translate_on
|
// synopsis translate_on
|
|
|
endmodule
|
endmodule
|
`endif // VENDOR_ALTERA
|
`endif // VENDOR_ALTERA
|
|
|
`ifdef VENDOR_XILINX
|
`ifdef VENDOR_XILINX
|
module xilinx_ram_dp (
|
module xilinx_ram_dp (
|
ADDRA,
|
ADDRA,
|
CLKA,
|
CLKA,
|
ADDRB,
|
ADDRB,
|
CLKB,
|
CLKB,
|
DIA,
|
DIA,
|
WEA,
|
WEA,
|
DIB,
|
DIB,
|
WEB,
|
WEB,
|
ENA,
|
ENA,
|
ENB,
|
ENB,
|
RSTA,
|
RSTA,
|
RSTB,
|
RSTB,
|
DOA,
|
DOA,
|
DOB) /* synthesis black_box */ ;
|
DOB) /* synthesis black_box */ ;
|
|
|
parameter awidth = 7;
|
parameter awidth = 7;
|
parameter dwidth = 8;
|
parameter dwidth = 8;
|
|
|
// port_a
|
// port_a
|
input CLKA;
|
input CLKA;
|
input RSTA;
|
input RSTA;
|
input ENA;
|
input ENA;
|
input [awidth-1:0] ADDRA;
|
input [awidth-1:0] ADDRA;
|
input [dwidth-1:0] DIA;
|
input [dwidth-1:0] DIA;
|
input WEA;
|
input WEA;
|
output [dwidth-1:0] DOA;
|
output [dwidth-1:0] DOA;
|
|
|
// port_b
|
// port_b
|
input CLKB;
|
input CLKB;
|
input RSTB;
|
input RSTB;
|
input ENB;
|
input ENB;
|
input [awidth-1:0] ADDRB;
|
input [awidth-1:0] ADDRB;
|
input [dwidth-1:0] DIB;
|
input [dwidth-1:0] DIB;
|
input WEB;
|
input WEB;
|
output [dwidth-1:0] DOB;
|
output [dwidth-1:0] DOB;
|
|
|
// insert simulation model
|
// insert simulation model
|
|
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// exemplar translate_off
|
// exemplar translate_off
|
|
|
C_MEM_DP_BLOCK_V1_0 #(
|
C_MEM_DP_BLOCK_V1_0 #(
|
awidth,
|
awidth,
|
awidth,
|
awidth,
|
1,
|
1,
|
1,
|
1,
|
"0",
|
"0",
|
1 << awidth,
|
1 << awidth,
|
1 << awidth,
|
1 << awidth,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
"",
|
"",
|
16,
|
16,
|
0,
|
0,
|
0,
|
0,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
dwidth,
|
dwidth,
|
dwidth)
|
dwidth)
|
xilinx_dpram_model (
|
xilinx_dpram_model (
|
.ADDRA(ADDRA),
|
.ADDRA(ADDRA),
|
.CLKA(CLKA),
|
.CLKA(CLKA),
|
.ADDRB(ADDRB),
|
.ADDRB(ADDRB),
|
.CLKB(CLKB),
|
.CLKB(CLKB),
|
.DIA(DIA),
|
.DIA(DIA),
|
.WEA(WEA),
|
.WEA(WEA),
|
.DIB(DIB),
|
.DIB(DIB),
|
.WEB(WEB),
|
.WEB(WEB),
|
.ENA(ENA),
|
.ENA(ENA),
|
.ENB(ENB),
|
.ENB(ENB),
|
.RSTA(RSTA),
|
.RSTA(RSTA),
|
.RSTB(RSTB),
|
.RSTB(RSTB),
|
.DOA(DOA),
|
.DOA(DOA),
|
.DOB(DOB));
|
.DOB(DOB));
|
|
|
// exemplar translate_on
|
// exemplar translate_on
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
endmodule
|
endmodule
|
`endif // VENDOR_XILINX
|
`endif // VENDOR_XILINX
|
|
|
