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-- Author: Raj Thilak Rajan : rajan at astron.nl: Nov 2009
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--
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-- Copyright (C) 2009-2010
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy)
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This file is part of the UniBoard software suite.
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- The file is free software: you can redistribute it and/or modify
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-- you may not use this file except in compliance with the License.
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-- it under the terms of the GNU General Public License as published by
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-- You may obtain a copy of the License at
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-- the Free Software Foundation, either version 3 of the License, or
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--
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-- (at your option) any later version.
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- Unless required by applicable law or agreed to in writing, software
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- GNU General Public License for more details.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- Purpose: Shift register for data
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-- Purpose: Shift register for data
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-- Description:
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-- Description:
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-- Delays input data by g_depth. The delay line shifts when in_val is
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-- Delays input data by g_depth. The delay line shifts when in_val is
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-- indicates an active clock cycle.
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-- indicates an active clock cycle.
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library ieee;
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library ieee;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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entity common_delay is
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entity common_delay is
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generic (
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generic (
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g_dat_w : NATURAL := 8; -- need g_dat_w to be able to use (others=>'') assignments for two dimensional unconstraint vector arrays
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g_dat_w : NATURAL := 8; -- need g_dat_w to be able to use (others=>'') assignments for two dimensional unconstraint vector arrays
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g_depth : NATURAL := 16
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g_depth : NATURAL := 16
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);
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);
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port (
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port (
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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in_val : in STD_LOGIC := '1';
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in_val : in STD_LOGIC := '1';
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in_dat : in STD_LOGIC_VECTOR(g_dat_w-1 downto 0);
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in_dat : in STD_LOGIC_VECTOR(g_dat_w-1 downto 0);
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out_dat : out STD_LOGIC_VECTOR(g_dat_w-1 downto 0)
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out_dat : out STD_LOGIC_VECTOR(g_dat_w-1 downto 0)
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);
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);
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end entity common_delay;
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end entity common_delay;
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architecture rtl of common_delay is
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architecture rtl of common_delay is
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-- Use index (0) as combinatorial input and index(1:g_depth) for the shift
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-- Use index (0) as combinatorial input and index(1:g_depth) for the shift
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-- delay, in this way the t_dly_arr type can support all g_depth >= 0
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-- delay, in this way the t_dly_arr type can support all g_depth >= 0
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type t_dly_arr is array (0 to g_depth) of STD_LOGIC_VECTOR(g_dat_w-1 downto 0);
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type t_dly_arr is array (0 to g_depth) of STD_LOGIC_VECTOR(g_dat_w-1 downto 0);
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signal shift_reg : t_dly_arr := (others=>(others=>'0'));
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signal shift_reg : t_dly_arr := (others=>(others=>'0'));
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begin
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begin
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shift_reg(0) <= in_dat;
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shift_reg(0) <= in_dat;
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out_dat <= shift_reg(g_depth);
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out_dat <= shift_reg(g_depth);
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gen_reg : if g_depth>0 generate
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gen_reg : if g_depth>0 generate
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p_clk : process(clk)
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p_clk : process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if in_val='1' then
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if in_val='1' then
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shift_reg(1 to g_depth) <= shift_reg(0 to g_depth-1);
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shift_reg(1 to g_depth) <= shift_reg(0 to g_depth-1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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end rtl;
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end rtl;
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