-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2012
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE work.common_components_pkg.ALL;
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USE work.common_components_pkg.ALL;
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-- Purpose: Select symbol from input data stream
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-- Purpose: Select symbol from input data stream
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-- Description:
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-- Description:
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-- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
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-- The in_data is a concatenation of g_nof_symbols, that are each g_symbol_w
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-- bits wide. The symbol with index set by in_sel is passed on to the output
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-- bits wide. The symbol with index set by in_sel is passed on to the output
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-- out_dat.
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-- out_dat.
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-- Remarks:
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-- Remarks:
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-- . If the in_select index is too large for g_nof_input range then the output
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-- . If the in_select index is too large for g_nof_input range then the output
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-- passes on symbol 0.
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-- passes on symbol 0.
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ENTITY common_select_symbol IS
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ENTITY common_select_symbol IS
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GENERIC (
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GENERIC (
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g_pipeline_in : NATURAL := 0;
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g_pipeline_in : NATURAL := 0;
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g_pipeline_out : NATURAL := 1;
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g_pipeline_out : NATURAL := 1;
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g_nof_symbols : NATURAL := 4;
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g_nof_symbols : NATURAL := 4;
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g_symbol_w : NATURAL := 16;
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g_symbol_w : NATURAL := 16;
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g_sel_w : NATURAL := 2
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g_sel_w : NATURAL := 2
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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in_data : IN STD_LOGIC_VECTOR(g_nof_symbols*g_symbol_w-1 DOWNTO 0);
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in_data : IN STD_LOGIC_VECTOR(g_nof_symbols*g_symbol_w-1 DOWNTO 0);
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in_val : IN STD_LOGIC := '0';
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in_val : IN STD_LOGIC := '0';
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in_sop : IN STD_LOGIC := '0';
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in_sop : IN STD_LOGIC := '0';
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in_eop : IN STD_LOGIC := '0';
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in_eop : IN STD_LOGIC := '0';
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in_sync : IN STD_LOGIC := '0';
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in_sync : IN STD_LOGIC := '0';
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in_sel : IN STD_LOGIC_VECTOR(g_sel_w-1 DOWNTO 0);
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in_sel : IN STD_LOGIC_VECTOR(g_sel_w-1 DOWNTO 0);
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out_sel : OUT STD_LOGIC_VECTOR(g_sel_w-1 DOWNTO 0); -- pipelined in_sel, use range to allow leaving it OPEN
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out_sel : OUT STD_LOGIC_VECTOR(g_sel_w-1 DOWNTO 0); -- pipelined in_sel, use range to allow leaving it OPEN
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out_symbol : OUT STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
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out_symbol : OUT STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
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out_val : OUT STD_LOGIC; -- pipelined in_val
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out_val : OUT STD_LOGIC; -- pipelined in_val
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out_sop : OUT STD_LOGIC; -- pipelined in_sop
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out_sop : OUT STD_LOGIC; -- pipelined in_sop
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out_eop : OUT STD_LOGIC; -- pipelined in_eop
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out_eop : OUT STD_LOGIC; -- pipelined in_eop
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out_sync : OUT STD_LOGIC -- pipelined in_sync
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out_sync : OUT STD_LOGIC -- pipelined in_sync
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);
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);
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END common_select_symbol;
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END common_select_symbol;
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ARCHITECTURE rtl OF common_select_symbol IS
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ARCHITECTURE rtl OF common_select_symbol IS
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CONSTANT c_pipeline : NATURAL := g_pipeline_in + g_pipeline_out;
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CONSTANT c_pipeline : NATURAL := g_pipeline_in + g_pipeline_out;
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SIGNAL in_data_reg : STD_LOGIC_VECTOR(in_data'RANGE);
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SIGNAL in_data_reg : STD_LOGIC_VECTOR(in_data'RANGE);
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SIGNAL in_sel_reg : STD_LOGIC_VECTOR(in_sel'RANGE);
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SIGNAL in_sel_reg : STD_LOGIC_VECTOR(in_sel'RANGE);
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SIGNAL sel_symbol : STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
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SIGNAL sel_symbol : STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
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BEGIN
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BEGIN
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-- pipeline input
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-- pipeline input
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u_pipe_in_data : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_in, 0, in_data'LENGTH, in_data'LENGTH) PORT MAP (rst, clk, '1', '0', '1', in_data, in_data_reg);
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u_pipe_in_data : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_in, 0, in_data'LENGTH, in_data'LENGTH) PORT MAP (rst, clk, '1', '0', '1', in_data, in_data_reg);
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u_pipe_in_sel : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_in, 0, g_sel_w, g_sel_w) PORT MAP (rst, clk, '1', '0', '1', in_sel, in_sel_reg);
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u_pipe_in_sel : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_in, 0, g_sel_w, g_sel_w) PORT MAP (rst, clk, '1', '0', '1', in_sel, in_sel_reg);
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no_sel : IF g_nof_symbols=1 GENERATE
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no_sel : IF g_nof_symbols=1 GENERATE
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sel_symbol <= in_data_reg;
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sel_symbol <= in_data_reg;
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END GENERATE;
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END GENERATE;
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gen_sel : IF g_nof_symbols>1 GENERATE
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gen_sel : IF g_nof_symbols>1 GENERATE
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-- Default pass on symbol 0 else if supported pass on the selected symbol
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-- Default pass on symbol 0 else if supported pass on the selected symbol
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p_sel : PROCESS(in_sel_reg, in_data_reg)
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p_sel : PROCESS(in_sel_reg, in_data_reg)
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BEGIN
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BEGIN
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sel_symbol <= in_data_reg(g_symbol_w-1 DOWNTO 0);
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sel_symbol <= in_data_reg(g_symbol_w-1 DOWNTO 0);
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FOR I IN g_nof_symbols-1 DOWNTO 0 LOOP
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FOR I IN g_nof_symbols-1 DOWNTO 0 LOOP
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IF TO_UINT(in_sel_reg)=I THEN
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IF TO_UINT(in_sel_reg)=I THEN
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sel_symbol <= in_data_reg((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w);
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sel_symbol <= in_data_reg((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w);
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END IF;
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END IF;
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END LOOP;
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END LOOP;
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END PROCESS;
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END PROCESS;
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END GENERATE;
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END GENERATE;
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-- pipeline selected symbol output and control outputs
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-- pipeline selected symbol output and control outputs
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u_pipe_out_symbol : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_out, 0, g_symbol_w, g_symbol_w) PORT MAP (rst, clk, '1', '0', '1', sel_symbol, out_symbol);
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u_pipe_out_symbol : common_pipeline GENERIC MAP ("SIGNED", g_pipeline_out, 0, g_symbol_w, g_symbol_w) PORT MAP (rst, clk, '1', '0', '1', sel_symbol, out_symbol);
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u_pipe_out_sel : common_pipeline GENERIC MAP ("SIGNED", c_pipeline, 0, in_sel'LENGTH, in_sel'LENGTH) PORT MAP (rst, clk, '1', '0', '1', in_sel, out_sel);
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u_pipe_out_sel : common_pipeline GENERIC MAP ("SIGNED", c_pipeline, 0, in_sel'LENGTH, in_sel'LENGTH) PORT MAP (rst, clk, '1', '0', '1', in_sel, out_sel);
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u_pipe_out_val : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_val, out_val);
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u_pipe_out_val : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_val, out_val);
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u_pipe_out_sop : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_sop, out_sop);
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u_pipe_out_sop : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_sop, out_sop);
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u_pipe_out_eop : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_eop, out_eop);
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u_pipe_out_eop : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_eop, out_eop);
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u_pipe_out_sync : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_sync, out_sync);
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u_pipe_out_sync : common_pipeline_sl GENERIC MAP (c_pipeline, 0, FALSE) PORT MAP (rst, clk, '1', '0', '1', in_sync, out_sync);
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END rtl;
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END rtl;
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