-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2009
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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ENTITY tb_common_switch IS
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ENTITY tb_common_switch IS
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END tb_common_switch;
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END tb_common_switch;
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-- Usage:
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-- Usage:
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-- > as 10
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-- > as 10
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-- > run -all
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-- > run -all
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-- . expand out_level in the Wave window to check the behaviour of the 16 possible BOOLEAN generic setttings
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-- . expand out_level in the Wave window to check the behaviour of the 16 possible BOOLEAN generic setttings
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-- . for expected Wave window see tb_common_switch.jpg
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-- . for expected Wave window see tb_common_switch.jpg
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--
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--
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-- Description:
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-- Description:
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-- Runs 8 instances in parallel to try all combinations of:
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-- Runs 8 instances in parallel to try all combinations of:
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-- . g_priority_lo
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-- . g_priority_lo
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-- . g_or_high
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-- . g_or_high
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-- . g_and_low
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-- . g_and_low
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ARCHITECTURE tb OF tb_common_switch IS
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ARCHITECTURE tb OF tb_common_switch IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_nof_generics : NATURAL := 3;
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CONSTANT c_nof_generics : NATURAL := 3;
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CONSTANT c_nof_dut : NATURAL := 2**c_nof_generics;
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CONSTANT c_nof_dut : NATURAL := 2**c_nof_generics;
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CONSTANT c_generics_matrix : t_boolean_matrix(0 TO c_nof_dut-1, 0 TO c_nof_generics-1) := ((FALSE, FALSE, FALSE),
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CONSTANT c_generics_matrix : t_boolean_matrix(0 TO c_nof_dut-1, 0 TO c_nof_generics-1) := ((FALSE, FALSE, FALSE),
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(FALSE, FALSE, TRUE),
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(FALSE, FALSE, TRUE),
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(FALSE, TRUE, FALSE),
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(FALSE, TRUE, FALSE),
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(FALSE, TRUE, TRUE),
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(FALSE, TRUE, TRUE),
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( TRUE, FALSE, FALSE),
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( TRUE, FALSE, FALSE),
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( TRUE, FALSE, TRUE),
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( TRUE, FALSE, TRUE),
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( TRUE, TRUE, FALSE),
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( TRUE, TRUE, FALSE),
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( TRUE, TRUE, TRUE));
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( TRUE, TRUE, TRUE));
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-- View constants in Wave window
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-- View constants in Wave window
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SIGNAL dbg_c_generics_matrix : t_boolean_matrix(0 TO c_nof_dut-1, 0 TO c_nof_generics-1) := c_generics_matrix;
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SIGNAL dbg_c_generics_matrix : t_boolean_matrix(0 TO c_nof_dut-1, 0 TO c_nof_generics-1) := c_generics_matrix;
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SIGNAL dbg_state : NATURAL;
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SIGNAL dbg_state : NATURAL;
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SIGNAL rst : STD_LOGIC;
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL in_hi : STD_LOGIC;
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SIGNAL in_hi : STD_LOGIC;
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SIGNAL in_lo : STD_LOGIC;
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SIGNAL in_lo : STD_LOGIC;
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SIGNAL dbg_prio_lo : STD_LOGIC;
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SIGNAL dbg_prio_lo : STD_LOGIC;
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SIGNAL dbg_prio_lo_and : STD_LOGIC;
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SIGNAL dbg_prio_lo_and : STD_LOGIC;
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SIGNAL dbg_prio_lo_or : STD_LOGIC;
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SIGNAL dbg_prio_lo_or : STD_LOGIC;
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SIGNAL dbg_prio_lo_or_and : STD_LOGIC;
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SIGNAL dbg_prio_lo_or_and : STD_LOGIC;
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SIGNAL dbg_prio_hi : STD_LOGIC;
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SIGNAL dbg_prio_hi : STD_LOGIC;
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SIGNAL dbg_prio_hi_and : STD_LOGIC;
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SIGNAL dbg_prio_hi_and : STD_LOGIC;
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SIGNAL dbg_prio_hi_or : STD_LOGIC;
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SIGNAL dbg_prio_hi_or : STD_LOGIC;
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SIGNAL dbg_prio_hi_or_and : STD_LOGIC;
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SIGNAL dbg_prio_hi_or_and : STD_LOGIC;
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SIGNAL out_level : STD_LOGIC_VECTOR(0 TO c_nof_dut-1);
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SIGNAL out_level : STD_LOGIC_VECTOR(0 TO c_nof_dut-1);
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BEGIN
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BEGIN
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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p_in_stimuli : PROCESS
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p_in_stimuli : PROCESS
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BEGIN
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BEGIN
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dbg_state <= 0;
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dbg_state <= 0;
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rst <= '1';
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rst <= '1';
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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rst <= '0';
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rst <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 1) Single hi pulse
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-- 1) Single hi pulse
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dbg_state <= 1;
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dbg_state <= 1;
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 2) Second hi pulse during active lo gets ignored
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-- 2) Second hi pulse during active lo gets ignored
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dbg_state <= 2;
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dbg_state <= 2;
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 3) Second hi pulse while lo is just active, should be recognized as second out pulse
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-- 3) Second hi pulse while lo is just active, should be recognized as second out pulse
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dbg_state <= 3;
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dbg_state <= 3;
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 4) Continue active hi with single lo pulse
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-- 4) Continue active hi with single lo pulse
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dbg_state <= 4;
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dbg_state <= 4;
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 3);
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proc_common_wait_some_cycles(clk, 3);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 3);
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proc_common_wait_some_cycles(clk, 3);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 5) Active hi immediately after active lo
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-- 5) Active hi immediately after active lo
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dbg_state <= 5;
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dbg_state <= 5;
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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in_hi <= '1';
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in_hi <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 6) Simultaneous hi pulse and lo pulse
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-- 6) Simultaneous hi pulse and lo pulse
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dbg_state <= 6;
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dbg_state <= 6;
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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-- 7) Multiple simultaneous hi pulse and lo pulse
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-- 7) Multiple simultaneous hi pulse and lo pulse
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dbg_state <= 7;
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dbg_state <= 7;
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_hi <= '1';
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in_hi <= '1';
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in_lo <= '1';
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in_lo <= '1';
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_hi <= '0';
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in_hi <= '0';
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 5);
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proc_common_wait_some_cycles(clk, 5);
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in_lo <= '1'; -- ensure low output if it was still high
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in_lo <= '1'; -- ensure low output if it was still high
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proc_common_wait_some_cycles(clk, 1);
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proc_common_wait_some_cycles(clk, 1);
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in_lo <= '0';
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in_lo <= '0';
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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dbg_state <= 255;
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dbg_state <= 255;
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proc_common_wait_some_cycles(clk, 10);
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proc_common_wait_some_cycles(clk, 10);
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tb_end <= '1';
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tb_end <= '1';
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WAIT;
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WAIT;
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END PROCESS;
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END PROCESS;
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dbg_prio_lo <= out_level(4);
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dbg_prio_lo <= out_level(4);
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dbg_prio_lo_and <= out_level(5);
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dbg_prio_lo_and <= out_level(5);
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dbg_prio_lo_or <= out_level(6);
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dbg_prio_lo_or <= out_level(6);
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dbg_prio_lo_or_and <= out_level(7);
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dbg_prio_lo_or_and <= out_level(7);
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dbg_prio_hi <= out_level(0);
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dbg_prio_hi <= out_level(0);
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dbg_prio_hi_and <= out_level(1);
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dbg_prio_hi_and <= out_level(1);
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dbg_prio_hi_or <= out_level(2);
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dbg_prio_hi_or <= out_level(2);
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dbg_prio_hi_or_and <= out_level(3);
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dbg_prio_hi_or_and <= out_level(3);
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gen_dut : FOR I IN 0 TO c_nof_dut-1 GENERATE
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gen_dut : FOR I IN 0 TO c_nof_dut-1 GENERATE
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u_switch : ENTITY work.common_switch
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u_switch : ENTITY work.common_switch
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GENERIC MAP (
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GENERIC MAP (
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g_rst_level => '0', -- output level at reset.
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g_rst_level => '0', -- output level at reset.
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--g_rst_level => '1',
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--g_rst_level => '1',
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g_priority_lo => c_generics_matrix(I,0),
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g_priority_lo => c_generics_matrix(I,0),
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g_or_high => c_generics_matrix(I,1),
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g_or_high => c_generics_matrix(I,1),
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g_and_low => c_generics_matrix(I,2)
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g_and_low => c_generics_matrix(I,2)
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)
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)
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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switch_high => in_hi,
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switch_high => in_hi,
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switch_low => in_lo,
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switch_low => in_lo,
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out_level => out_level(I)
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out_level => out_level(I)
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);
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);
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END GENERATE;
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END GENERATE;
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END tb;
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END tb;
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