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-----------------------------------------------------------------------------
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-- Wishbone UART ------------------------------------------------------------
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-- (c) 2007 Joerg Bornschein (jb@capsec.org)
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--
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-- All files under GPLv2 -- please contact me if you use this component
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-----------------------------------------------------------------------------
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-- Wishbone UART ------------------------------------------------------------
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entity wb_uart is
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- Wishbone slave
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wb_adr_i : in std_logic_vector(31 downto 0);
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_sel_i : in std_logic_vector( 3 downto 0);
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wb_cyc_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_we_i : in std_logic;
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wb_rxirq_o : out std_logic;
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wb_txirq_o : out std_logic;
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-- Serial I/O ports
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uart_rx : in std_logic;
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uart_tx : out std_logic );
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end wb_uart;
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-----------------------------------------------------------------------------
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-- 0x00 Status Register
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-- 0x04 Divisor Register
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-- 0x08 RX / TX Data
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--
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-- Status Register:
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--
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-- +-------------+----------+----------+---------+---------+
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-- | ... 0 ... | TX_IRQEN | RX_IRQEN | TX_BUSY | RX_FULL |
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-- +-------------+----------+----------+---------+---------+
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--
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-- Divisor Register:
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-- Example: 115200 Baud with clk beeing 50MHz: 50MHz/115200 = 434
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--
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-----------------------------------------------------------------------------
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-- Implementation -----------------------------------------------------------
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architecture rtl of wb_uart is
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-----------------------------------------------------------------------------
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-- Components ---------------------------------------------------------------
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component myuart is
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port (
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clk : in std_logic;
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reset : in std_logic;
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--
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divisor : in std_logic_vector(15 downto 0);
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txdata : in std_logic_vector( 7 downto 0);
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rxdata : out std_logic_vector( 7 downto 0);
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wr : in std_logic;
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rd : in std_logic;
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tx_avail : out std_logic;
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tx_busy : out std_logic;
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rx_avail : out std_logic;
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rx_full : out std_logic;
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rx_error : out std_logic;
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--
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uart_rxd : in std_logic;
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uart_txd : out std_logic );
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end component;
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-----------------------------------------------------------------------------
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-- Local Signals ------------------------------------------------------------
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constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');
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signal active : std_logic;
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signal activeLast : std_logic;
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signal ack : std_logic;
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signal wr : std_logic;
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signal rd : std_logic;
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signal rx_avail : std_logic;
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signal tx_avail : std_logic;
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signal rxdata : std_logic_vector(7 downto 0);
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signal txdata : std_logic_vector(7 downto 0);
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signal status_reg : std_logic_vector(31 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal div_reg : std_logic_vector(31 downto 0);
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signal tx_irqen : std_logic;
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signal rx_irqen : std_logic;
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signal divisor : std_logic_vector(15 downto 0);
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begin
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-- Instantiate actual UART engine
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uart0: myuart
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port map (
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clk => clk,
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reset => reset,
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-- Sync Interface
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divisor => divisor,
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txdata => txdata,
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rxdata => rxdata,
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wr => wr,
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rd => rd,
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tx_avail => tx_avail,
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tx_busy => open,
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rx_avail => rx_avail,
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rx_full => open,
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rx_error => open,
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-- Async Interface
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uart_txd => uart_tx,
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uart_rxd => uart_rx );
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-- Status & divisor register + Wishbine glue logic
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status_reg <= ZEROS(31 downto 4) & tx_irqen & rx_irqen & not tx_avail & rx_avail;
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data_reg <= ZEROS(31 downto 8) & rxdata;
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div_reg <= ZEROS(31 downto 16) & divisor;
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-- Bus cycle?
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active <= wb_stb_i and wb_cyc_i;
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wb_dat_o <= status_reg when wb_we_i='0' and (active='1' or ack='1') and wb_adr_i(3 downto 0)=x"0" else
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div_reg when wb_we_i='0' and (active='1' or ack='1') and wb_adr_i(3 downto 0)=x"4" else
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data_reg when wb_we_i='0' and (active='1' or ack='1') and wb_adr_i(3 downto 0)=x"8" else
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(others => '0');
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rd <= '1' when (active='1' or ack='1') and wb_adr_i(3 downto 0)=x"8" and wb_we_i='0' else
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'0';
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wr <= '1' when (active='1' or ack='1') and wb_adr_i(3 downto 0)=x"8" and wb_we_i='1' else
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'0';
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txdata <= wb_dat_i(7 downto 0);
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wb_ack_o <= ack;
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-- Handle Wishbone write request (and reset condition)
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proc: process(reset, clk) is
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begin
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if clk'event and clk='1' then
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if reset='1' then
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tx_irqen <= '0';
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rx_irqen <= '0';
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divisor <= (others => '1');
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else
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if active='1' then
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if activeLast='0' then
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activeLast <= '1';
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ack <= '0';
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else
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activeLast <= '0';
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ack <= '1';
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end if;
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else
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ack <= '0';
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activeLast <= '0';
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end if;
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if active='1' and wb_we_i='1' then
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if wb_adr_i(3 downto 0)=x"0" then -- write to status register
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tx_irqen <= wb_dat_i(3);
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rx_irqen <= wb_dat_i(2);
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elsif wb_adr_i(3 downto 0)=x"4" then -- write to divisor register
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divisor <= wb_dat_i(15 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Generate interrupts when enabled
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wb_rxirq_o <= rx_avail and rx_irqen;
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wb_txirq_o <= tx_avail and tx_irqen;
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end rtl;
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No newline at end of file
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No newline at end of file
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