library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity testbench_descrambler is
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entity testbench_descrambler is
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end entity testbench_descrambler;
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end entity testbench_descrambler;
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architecture tb_descrambler of testbench_descrambler is
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architecture tb_descrambler of testbench_descrambler is
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signal Clk : std_logic; -- Clock input
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signal Clk : std_logic; -- Interface clock
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signal Reset : std_logic; -- Reset decoder
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signal Reset : std_logic; -- Descrambler reset, use for initialization
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signal Data_In : std_logic_vector(63 downto 0); -- Data input
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signal Data_In : std_logic_vector(63 downto 0); -- Data input
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signal Data_Out : std_logic_vector(63 downto 0); -- Decoded 64-bit output
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signal Data_Out : std_logic_vector(63 downto 0); -- Data output
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signal Data_Control_In : std_logic; -- Indicates whether the word is data or control
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signal Data_Control_Out : std_logic; -- Indicates whether the word is data or control
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signal Lane_Number : std_logic_vector (3 downto 0); -- Each lane number starts with different scrambler word
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signal Lane_Number : std_logic_vector (3 downto 0);
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signal Data_Control_In : std_logic; -- Indicates a control word
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signal Data_Control_Out : std_logic; -- Output control word indication
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signal Data_Valid_In : std_logic; -- Only valid data will be processed
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signal Data_Valid_Out : std_logic;
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signal Lock : std_logic;
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signal Error_BadSync : std_logic;
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signal Error_BadSync : std_logic;
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signal Error_StateMismatch : std_logic;
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signal Error_StateMismatch : std_logic;
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signal Error_NoSync : std_logic;
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signal Error_NoSync : std_logic;
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signal Data_Valid_Out : std_logic;
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : entity work.Descrambler
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uut : entity work.Descrambler
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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Data_in => Data_in,
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Data_in => Data_in,
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Data_out => Data_out,
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Data_out => Data_out,
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Lane_Number => Lane_Number,
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Data_control_In => Data_control_In,
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Data_control_In => Data_control_In,
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Data_control_Out => Data_control_Out,
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Data_control_Out => Data_control_Out,
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Data_valid_in => Data_valid_in,
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Data_valid_out => Data_valid_out,
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Data_valid_out => Data_valid_out,
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Lock => Lock,
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Lane_Number => Lane_Number,
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Error_BadSync => Error_BadSync,
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Error_BadSync => Error_BadSync,
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Error_StateMismatch => Error_StateMismatch,
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Error_StateMismatch => Error_StateMismatch,
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Error_NoSync => Error_NoSync
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Error_NoSync => Error_NoSync
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);
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);
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Clk_process :process
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Clk_process :process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
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wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
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clk <= '0';
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clk <= '0';
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wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
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wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
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end process;
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end process;
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simulation : process
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simulation : process
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begin
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begin
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wait for 1 ps;
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wait for 1 ps;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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reset <= '1';
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reset <= '1';
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Lane_Number <= "0001";
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Lane_Number <= "0001";
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data_in <= (others=>'0');
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data_in <= (others=>'0');
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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reset <= '0';
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reset <= '0';
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Data_in <= X"1f5e5d5c5b5a5958";
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Data_in <= X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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Data_in <= X"78f6_78f6_78f6_78f6"; --1
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Data_in <= X"78f6_78f6_78f6_78f6"; --1
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"3f5e5d5c5b5a5958";
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data_in <= X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD*23;
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wait for CLK_PERIOD*23;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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Data_in <= X"78f6_78f6_78f6_78f6";--2
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Data_in <= X"78f6_78f6_78f6_78f6";--2
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"5f5e5a5c5b60f2a0";
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data_in <= X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD*23;
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wait for CLK_PERIOD*23;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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data_in <= X"78f6_78f6_78f6_78f6";--3
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data_in <= X"78f6_78f6_78f6_78f6";--3
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"70000FFF000000F0";
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data_in <= X"70000FFF000000F0";
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wait for CLK_PERIOD*23;
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wait for CLK_PERIOD*23;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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data_in <= X"78f6_78f6_78f6_78f6";--4 -> lock
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data_in <= X"78f6_78f6_78f6_78f6";--4 -> lock
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"5f5e5a5c5b60f2a0";
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data_in <= X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"70000FFF000000F0";
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data_in <= X"70000FFF000000F0";
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wait for CLK_PERIOD*21;
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wait for CLK_PERIOD*21;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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data_in <= X"78f6_78f6_78f6_78f6"; --Sync &
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data_in <= X"78f6_78f6_78f6_78f6"; --Sync &
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_In <= X"2Bfe_d100_19e0_1dbd";
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Data_In <= X"2Bfe_d100_19e0_1dbd";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"70000FFF000000F0";
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data_in <= X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD*2;
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Data_Control_In <= '1';
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Data_Control_In <= '1';
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Data_in <= X"2f5e5d5c5b5a5958";
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Data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control_In <= '0';
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Data_Control_In <= '0';
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data_in <= X"9486576758050505";
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data_in <= X"9486576758050505";
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wait for CLK_PERIOD*19;
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wait for CLK_PERIOD*19;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"8050505050050505";
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data_in <= X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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data_in <= X"9486576758050505";
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data_in <= X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"60b35d5dc4a582a7";
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data_in <= X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD*12;
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wait for CLK_PERIOD*12;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_in <= X"1f5e5d5c5b5a5958";
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Data_in <= X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_in <= X"2f5e5d5c5b5a5958";
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Data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"3f5e5d5c5b5a5958";
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data_in <= X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_in <= X"4f21a2a3a4a5a6a7";
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Data_in <= X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"5f5e5a5c5b60f2a0";
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data_in <= X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"635e22a3a4a5a7a7";
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data_in <= X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"5f5e5a5c5b60f2a0";
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data_in <= X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"635e22a3a4a5a7a7";
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data_in <= X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"70000FFF000000F0";
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data_in <= X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD*2;
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Data_in <= X"2f5e5d5c5b5a5958";
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Data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"8050505050050505";
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data_in <= X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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data_in <= X"9486576758050505";
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data_in <= X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"60b35d5dc4a582a7";
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data_in <= X"60b35d5dc4a582a7";
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wait for CLK_PERIOD*60;
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wait for CLK_PERIOD*60;
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data_in <= X"8050505050050505";
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data_in <= X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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data_in <= X"9486576758050505";
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data_in <= X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"60b35d5dc4a582a7";
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data_in <= X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD*12;
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wait for CLK_PERIOD*12;
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data_in <= X"2c8e5d5c5b5a5958";
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data_in <= X"2c8e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_in <= X"1f5e5d5c5b5a5958";
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Data_in <= X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD*26;
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wait for CLK_PERIOD*26;
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data_in <= X"2c8e5d5c5b5a5958";
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data_in <= X"2c8e5d5c5b5a5958";
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wait for CLK_PERIOD*18;
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wait for CLK_PERIOD*18;
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data_in <= X"1f5e5d5c5b5a5958";
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data_in <= X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait;
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wait;
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end process;
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end process;
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end architecture tb_descrambler;
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end architecture tb_descrambler;
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