library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity testbench_encoder is
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entity testbench_encoder is
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end entity testbench_encoder;
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end entity testbench_encoder;
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architecture tb_encoder of testbench_encoder is
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architecture tb_encoder of testbench_encoder is
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component Encoder is
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port (
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data_in : in std_logic_vector(63 downto 0);
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encoder_en : in std_logic;
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Data_Control : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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encoder_rst : in std_logic;
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offset : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(66 downto 0)
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);
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end component Encoder;
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for uut : line_encoder use entity work.line_encoder(encoder);
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signal clk : std_logic; -- Clock input
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signal Data_In : std_logic_vector(63 downto 0); -- Data input
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signal Data_Out : std_logic_vector(66 downto 0); -- Encoded 67-bit output
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signal Data_Control : std_logic:= '0'; -- Determines whether the word is data or control
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signal Data_valid_in : std_logic;
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signal Data_valid_out: std_logic;
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signal Encoder_En : std_logic := '0'; -- Enables the encoder
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signal Encoder_Rst : std_logic; -- Resets the encoder
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signal data_in : std_logic_vector(63 downto 0);
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--signal Offset : std_logic_vector(7 downto 0); -- Debug to see the average values of ones and zeros
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signal encoder_en : std_logic := '0';
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signal Gearboxready : std_logic;
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signal Data_Control : std_logic := '0';
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signal clk : std_logic;
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signal rst : std_logic := '0';
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signal encoder_rst : std_logic;
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signal offset : std_logic_vector(7 downto 0);
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signal data_out : std_logic_vector(66 downto 0);
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : Encoder
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uut : work.Encoder
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port map (
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port map (
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clk => clk,
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data_in => data_in,
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data_in => data_in,
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encoder_en => encoder_en,
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data_out => data_out,
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Data_Control => Data_Control,
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Data_Control => Data_Control,
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clk => clk,
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data_valid_in => data_valid_in,
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rst => rst,
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data_valid_out => data_valid_out,
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encoder_en => encoder_en,
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encoder_rst => encoder_rst,
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encoder_rst => encoder_rst,
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offset => offset,
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data_out => data_out
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--offset => offset,
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gearboxready => gearboxready
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);
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);
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Clk_process :process
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Clk_process :process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
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wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
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clk <= '0';
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clk <= '0';
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wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
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wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
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end process;
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end process;
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simulation : process
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simulation : process
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begin
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begin
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wait for 1 ps;
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wait for 1 ps;
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encoder_rst <= '1';
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encoder_rst <= '1';
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data_in <= (others=>'0');
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data_in <= (others=>'0');
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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encoder_rst <= '0';
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encoder_rst <= '0';
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encoder_en <= '1';
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encoder_en <= '1';
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data_in <= X"5f5e5d5c5b5a5958";
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data_in <= X"5f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"9f5e5d5c5b5a5958";
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data_in <= X"9f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"bf21a2a3a4a5a6a7";
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data_in <= X"bf21a2a3a4a5a6a7";
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encoder_rst <= '1';
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encoder_rst <= '1';
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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encoder_rst <= '0';
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encoder_rst <= '0';
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5a5c5b60f2a0";
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data_in <= X"2f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"635e22a3a4a5a7a7";
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data_in <= X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"00000FFF000000F0";
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data_in <= X"00000FFF000000F0";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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data_in <= X"5050505050050505";
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data_in <= X"5050505050050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"5486576758050505";
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data_in <= X"5486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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Data_Control <= '1';
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Data_Control <= '1';
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data_in <= X"60b35d5dc4a582a7";
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data_in <= X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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data_in <= X"2f5e5d5c5b5a5958";
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data_in <= X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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wait;
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wait;
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end process;
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end process;
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end architecture tb_line_encoder;
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end architecture tb_line_encoder;
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