URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [Makefile] - Diff between revs 2 and 4

Rev 2	Rev 4

`targets = sim`	`targets = sim`

`sim_target =`	`sim_target =`
`sim_files =`	`sim_files =`
`sim_hostcompile =`	`sim_hostcompile =`
`sim_subdirs = mem/cache/c_model peripherals/mem/c_model bus/c_model`	`sim_subdirs = mem/cache/c_model peripherals/mem/c_model bus/c_model`