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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- This file is a part of the LEON VHDL model
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-- This file is a part of the LEON VHDL model
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-- Copyright (C) 1999 European Space Agency (ESA)
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-- Copyright (C) 1999 European Space Agency (ESA)
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--
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--
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-- This library is free software; you can redistribute it and/or
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2 of the License, or (at your option) any later version.
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-- version 2 of the License, or (at your option) any later version.
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--
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--
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-- See the file COPYING.LGPL for the full details of the license.
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-- See the file COPYING.LGPL for the full details of the license.
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Entity: leon_pci
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-- Entity: leon_pci
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-- File: leon_pci.vhd
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-- File: leon_pci.vhd
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-- Author: Jiri Gaisler - ESA/ESTEC
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-- Author: Jiri Gaisler - ESA/ESTEC
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-- Description: Complete processor with PCI pads
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-- Description: Complete processor with PCI pads
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.leon_target.all;
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use work.leon_target.all;
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use work.leon_config.all;
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use work.leon_config.all;
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use work.leon_iface.all;
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use work.leon_iface.all;
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use work.tech_map.all;
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use work.tech_map.all;
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-- pragma translate_off
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-- pragma translate_off
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use work.debug.all;
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use work.debug.all;
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-- pragma translate_on
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-- pragma translate_on
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|
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entity leon_eth_pci is
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entity leon_eth_pci is
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port (
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port (
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resetn : in std_logic; -- system signals
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resetn : in std_logic; -- system signals
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clk : in std_logic;
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clk : in std_logic;
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pllref : in std_logic;
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pllref : in std_logic;
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plllock : out std_logic;
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plllock : out std_logic;
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|
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errorn : out std_logic;
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errorn : out std_logic;
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address : out std_logic_vector(27 downto 0); -- memory bus
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address : out std_logic_vector(27 downto 0); -- memory bus
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|
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data : inout std_logic_vector(31 downto 0);
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data : inout std_logic_vector(31 downto 0);
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|
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ramsn : out std_logic_vector(4 downto 0);
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ramsn : out std_logic_vector(4 downto 0);
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ramoen : out std_logic_vector(4 downto 0);
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ramoen : out std_logic_vector(4 downto 0);
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rwen : inout std_logic_vector(3 downto 0);
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rwen : inout std_logic_vector(3 downto 0);
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romsn : out std_logic_vector(1 downto 0);
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romsn : out std_logic_vector(1 downto 0);
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iosn : out std_logic;
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iosn : out std_logic;
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oen : out std_logic;
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oen : out std_logic;
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read : out std_logic;
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read : out std_logic;
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writen : inout std_logic;
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writen : inout std_logic;
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|
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brdyn : in std_logic;
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brdyn : in std_logic;
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bexcn : in std_logic;
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bexcn : in std_logic;
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-- sdram i/f
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-- sdram i/f
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sdcke : out std_logic_vector ( 1 downto 0); -- clk en
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sdcke : out std_logic_vector ( 1 downto 0); -- clk en
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sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
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sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
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sdwen : out std_logic; -- write en
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sdwen : out std_logic; -- write en
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sdrasn : out std_logic; -- row addr stb
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sdrasn : out std_logic; -- row addr stb
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sdcasn : out std_logic; -- col addr stb
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sdcasn : out std_logic; -- col addr stb
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sddqm : out std_logic_vector ( 3 downto 0); -- data i/o mask
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sddqm : out std_logic_vector ( 3 downto 0); -- data i/o mask
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sdclk : out std_logic;
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sdclk : out std_logic;
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pio : inout std_logic_vector(15 downto 0); -- I/O port
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pio : inout std_logic_vector(15 downto 0); -- I/O port
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|
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wdogn : out std_logic; -- watchdog output
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wdogn : out std_logic; -- watchdog output
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|
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dsuen : in std_logic;
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dsuen : in std_logic;
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dsutx : out std_logic;
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dsutx : out std_logic;
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dsurx : in std_logic;
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dsurx : in std_logic;
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dsubre : in std_logic;
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dsubre : in std_logic;
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dsuact : out std_logic;
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dsuact : out std_logic;
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test : in std_logic;
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test : in std_logic;
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pci_rst_in_n : in std_logic; -- PCI bus
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pci_rst_in_n : in std_logic; -- PCI bus
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pci_clk_in : in std_logic;
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pci_clk_in : in std_logic;
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pci_gnt_in_n : in std_logic;
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pci_gnt_in_n : in std_logic;
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pci_idsel_in : in std_logic; -- ignored in host bridge core
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pci_idsel_in : in std_logic; -- ignored in host bridge core
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pci_lock_n : inout std_logic; -- Phoenix core: input only
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pci_lock_n : inout std_logic; -- Phoenix core: input only
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_cbe_n : inout std_logic_vector(3 downto 0);
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pci_cbe_n : inout std_logic_vector(3 downto 0);
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pci_frame_n : inout std_logic;
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pci_frame_n : inout std_logic;
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pci_irdy_n : inout std_logic;
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pci_irdy_n : inout std_logic;
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pci_trdy_n : inout std_logic;
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pci_trdy_n : inout std_logic;
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pci_devsel_n : inout std_logic;
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pci_devsel_n : inout std_logic;
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pci_stop_n : inout std_logic;
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pci_stop_n : inout std_logic;
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pci_perr_n : inout std_logic;
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pci_perr_n : inout std_logic;
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pci_par : inout std_logic;
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pci_par : inout std_logic;
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pci_req_n : inout std_logic; -- tristate pad but never read
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pci_req_n : inout std_logic; -- tristate pad but never read
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pci_serr_n : inout std_logic; -- open drain output
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pci_serr_n : inout std_logic; -- open drain output
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pci_host : in std_logic;
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pci_host : in std_logic;
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pci_66 : in std_logic;
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pci_66 : in std_logic;
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pci_arb_req_n : in std_logic_vector(0 to 3);
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pci_arb_req_n : in std_logic_vector(0 to 3);
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pci_arb_gnt_n : out std_logic_vector(0 to 3);
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pci_arb_gnt_n : out std_logic_vector(0 to 3);
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power_state : out std_logic_vector(1 downto 0);
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power_state : out std_logic_vector(1 downto 0);
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pme_enable : out std_logic;
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pme_enable : out std_logic;
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pme_clear : out std_logic;
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pme_clear : out std_logic;
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pme_status : in std_logic;
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pme_status : in std_logic;
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-- ethernet
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-- ethernet
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emdio : inout std_logic;
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emdio : inout std_logic;
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etx_clk : in std_logic;
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etx_clk : in std_logic;
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erx_clk : in std_logic;
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erx_clk : in std_logic;
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erxd : in std_logic_vector(3 downto 0);
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erxd : in std_logic_vector(3 downto 0);
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erx_dv : in std_logic;
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erx_dv : in std_logic;
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erx_er : in std_logic;
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erx_er : in std_logic;
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erx_col : in std_logic;
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erx_col : in std_logic;
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erx_crs : in std_logic;
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erx_crs : in std_logic;
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etxd : out std_logic_vector(3 downto 0);
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etxd : out std_logic_vector(3 downto 0);
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etx_en : out std_logic;
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etx_en : out std_logic;
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etx_er : out std_logic;
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etx_er : out std_logic;
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emdc : out std_logic;
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emdc : out std_logic;
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emddis : out std_logic;
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emddis : out std_logic;
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epwrdwn : out std_logic;
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epwrdwn : out std_logic;
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ereset : out std_logic;
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ereset : out std_logic;
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esleep : out std_logic;
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esleep : out std_logic;
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epause : out std_logic
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epause : out std_logic
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);
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);
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end;
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end;
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architecture rtl of leon_eth_pci is
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architecture rtl of leon_eth_pci is
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component mcore
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component mcore
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port (
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port (
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resetn : in std_logic;
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resetn : in std_logic;
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clk : in clk_type;
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clk : in clk_type;
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clkn : in clk_type;
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clkn : in clk_type;
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pciclk : in clk_type;
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pciclk : in clk_type;
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memi : in memory_in_type;
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memi : in memory_in_type;
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memo : out memory_out_type;
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memo : out memory_out_type;
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ioi : in io_in_type;
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ioi : in io_in_type;
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ioo : out io_out_type;
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ioo : out io_out_type;
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pcii : in pci_in_type;
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pcii : in pci_in_type;
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pcio : out pci_out_type;
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pcio : out pci_out_type;
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dsi : in dsuif_in_type;
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dsi : in dsuif_in_type;
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dso : out dsuif_out_type;
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dso : out dsuif_out_type;
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sdo : out sdram_out_type;
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sdo : out sdram_out_type;
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ethi : in eth_in_type;
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ethi : in eth_in_type;
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etho : out eth_out_type;
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etho : out eth_out_type;
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cgo : in clkgen_out_type;
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cgo : in clkgen_out_type;
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test : in std_logic
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test : in std_logic
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);
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);
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end component;
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end component;
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signal vcc, gnd, clko, sdclkl, resetno : std_logic;
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signal vcc, gnd, clko, sdclkl, resetno : std_logic;
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signal clkm, clkn, pciclk : clk_type;
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signal clkm, clkn, pciclk : clk_type;
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signal memi : memory_in_type;
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal memo : memory_out_type;
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signal ioi : io_in_type;
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signal ioi : io_in_type;
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signal ioo : io_out_type;
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signal ioo : io_out_type;
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signal pcii : pci_in_type;
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signal pcii : pci_in_type;
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signal pcio : pci_out_type;
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signal pcio : pci_out_type;
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signal dsi : dsuif_in_type;
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signal dsi : dsuif_in_type;
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signal dso : dsuif_out_type;
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signal dso : dsuif_out_type;
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signal sdo : sdram_out_type;
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signal sdo : sdram_out_type;
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signal cgi : clkgen_in_type;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal cgo : clkgen_out_type;
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signal pci_aden : std_logic_vector(31 downto 0);
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signal pci_aden : std_logic_vector(31 downto 0);
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signal pci_cbeen : std_logic_vector(3 downto 0);
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signal pci_cbeen : std_logic_vector(3 downto 0);
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signal pci_frame_en : std_logic;
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signal pci_frame_en : std_logic;
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signal pci_irdy_en : std_logic;
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signal pci_irdy_en : std_logic;
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signal pci_trdy_en : std_logic;
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signal pci_trdy_en : std_logic;
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signal pci_devsel_en : std_logic;
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signal pci_devsel_en : std_logic;
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signal pci_stop_en : std_logic;
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signal pci_stop_en : std_logic;
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signal pci_perr_en : std_logic;
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signal pci_perr_en : std_logic;
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signal pci_par_en : std_logic;
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signal pci_par_en : std_logic;
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signal pci_req_en : std_logic;
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signal pci_req_en : std_logic;
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signal pci_serr_en : std_logic;
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signal pci_serr_en : std_logic;
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signal pci_lock_en : std_logic;
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signal pci_lock_en : std_logic;
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signal pci_lock_out : std_logic;
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signal pci_lock_out : std_logic;
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signal pci_req_in_dummy : std_logic;
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signal pci_req_in_dummy : std_logic;
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signal pci_clk : std_logic;
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signal pci_clk : std_logic;
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signal ethi : eth_in_type;
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signal ethi : eth_in_type;
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signal etho : eth_out_type;
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signal etho : eth_out_type;
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begin
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begin
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|
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gnd <= '0'; vcc <= '1';
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gnd <= '0'; vcc <= '1';
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cgi.pllctrl <= "00"; cgi.pllrst <= resetno; cgi.pllref <= pllref;
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cgi.pllctrl <= "00"; cgi.pllrst <= resetno; cgi.pllref <= pllref;
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-- main processor core
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-- main processor core
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mcore0 : mcore
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mcore0 : mcore
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port map (
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port map (
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resetn => resetno, clk => clkm, clkn => clkn, pciclk => pciclk,
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resetn => resetno, clk => clkm, clkn => clkn, pciclk => pciclk,
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memi => memi, memo => memo, ioi => ioi, ioo => ioo,
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memi => memi, memo => memo, ioi => ioi, ioo => ioo,
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pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, sdo => sdo,
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pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, sdo => sdo,
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ethi => ethi, etho => etho, cgo => cgo, test => test);
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ethi => ethi, etho => etho, cgo => cgo, test => test);
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|
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-- clock generator
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-- clock generator
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clkgen0 : clkgen
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clkgen0 : clkgen
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port map ( clko, pci_clk, clkm, clkn, sdclkl, pciclk, cgi, cgo);
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port map ( clko, pci_clk, clkm, clkn, sdclkl, pciclk, cgi, cgo);
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|
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-- pads
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-- pads
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-- clk_pad : inpad port map (clk, clko); -- clock
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-- clk_pad : inpad port map (clk, clko); -- clock
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clko <= clk; -- avoid buffering during synthesis
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clko <= clk; -- avoid buffering during synthesis
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reset_pad : smpad port map (resetn, resetno); -- reset
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reset_pad : smpad port map (resetn, resetno); -- reset
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brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
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brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
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bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
|
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
|
|
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ds : if DEBUG_UNIT generate
|
ds : if DEBUG_UNIT generate
|
dsuen_pad : inpad port map (dsuen, dsi.dsui.dsuen); -- DSU enable
|
dsuen_pad : inpad port map (dsuen, dsi.dsui.dsuen); -- DSU enable
|
dsutx_pad : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
|
dsutx_pad : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
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dsurx_pad : inpad port map (dsurx, dsi.dcomi.dsurx); -- DSU receive data
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dsurx_pad : inpad port map (dsurx, dsi.dcomi.dsurx); -- DSU receive data
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dsubre_pad : inpad port map (dsubre, dsi.dsui.dsubre); -- DSU break
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dsubre_pad : inpad port map (dsubre, dsi.dsui.dsubre); -- DSU break
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dsuact_pad : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
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dsuact_pad : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
|
end generate;
|
end generate;
|
|
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sd : if SDRAMEN generate
|
sd : if SDRAMEN generate
|
cs_pads: for i in 0 to 1 generate
|
cs_pads: for i in 0 to 1 generate
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sdcke_pad : outpad generic map (2) port map (sdo.sdcke(i), sdcke(i));
|
sdcke_pad : outpad generic map (2) port map (sdo.sdcke(i), sdcke(i));
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sdcsn_pad : outpad generic map (2) port map (sdo.sdcsn(i), sdcsn(i));
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sdcsn_pad : outpad generic map (2) port map (sdo.sdcsn(i), sdcsn(i));
|
end generate;
|
end generate;
|
sdwen_pad : outpad generic map (2) port map (sdo.sdwen, sdwen);
|
sdwen_pad : outpad generic map (2) port map (sdo.sdwen, sdwen);
|
sdrasn_pad : outpad generic map (2) port map (sdo.rasn, sdrasn);
|
sdrasn_pad : outpad generic map (2) port map (sdo.rasn, sdrasn);
|
sdcasn_pad : outpad generic map (2) port map (sdo.casn, sdcasn);
|
sdcasn_pad : outpad generic map (2) port map (sdo.casn, sdcasn);
|
dqm_pads: for i in 0 to 3 generate
|
dqm_pads: for i in 0 to 3 generate
|
sddqm_pad : outpad generic map (2) port map (sdo.dqm(i), sddqm(i));
|
sddqm_pad : outpad generic map (2) port map (sdo.dqm(i), sddqm(i));
|
end generate;
|
end generate;
|
-- sdclk_pad : outpad generic map (2) port map (sdclkl, sdclk);
|
-- sdclk_pad : outpad generic map (2) port map (sdclkl, sdclk);
|
sdclk <= sdclkl; -- disable pad for simulation
|
sdclk <= sdclkl; -- disable pad for simulation
|
end generate;
|
end generate;
|
|
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error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
|
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
|
|
|
d_pads: for i in 0 to 31 generate -- data bus
|
d_pads: for i in 0 to 31 generate -- data bus
|
d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
|
d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
|
end generate;
|
end generate;
|
|
|
|
|
pio_pads : for i in 0 to 15 generate -- parallel I/O port
|
pio_pads : for i in 0 to 15 generate -- parallel I/O port
|
pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
|
pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
|
end generate;
|
end generate;
|
|
|
rwen_pads : for i in 0 to 3 generate -- ram write strobe
|
rwen_pads : for i in 0 to 3 generate -- ram write strobe
|
rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
|
rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
|
end generate;
|
end generate;
|
|
|
-- I/O write strobe
|
-- I/O write strobe
|
writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
|
writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
|
|
|
a_pads : for i in 0 to 27 generate -- memory address
|
a_pads : for i in 0 to 27 generate -- memory address
|
a_pads : outpad generic map (3) port map (memo.address(i), address(i));
|
a_pads : outpad generic map (3) port map (memo.address(i), address(i));
|
end generate;
|
end generate;
|
|
|
ramsn_pads : for i in 0 to 4 generate -- ram oen/rasn
|
ramsn_pads : for i in 0 to 4 generate -- ram oen/rasn
|
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
|
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
|
end generate;
|
end generate;
|
|
|
ramoen_pads : for i in 0 to 4 generate -- ram chip select
|
ramoen_pads : for i in 0 to 4 generate -- ram chip select
|
ramoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
|
ramoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
|
end generate;
|
end generate;
|
|
|
romsn_pads : for i in 0 to 1 generate -- rom chip select
|
romsn_pads : for i in 0 to 1 generate -- rom chip select
|
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
|
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
|
end generate;
|
end generate;
|
|
|
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
|
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
|
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
|
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
|
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
|
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
|
|
|
wd : if WDOGEN generate
|
wd : if WDOGEN generate
|
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
|
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
|
end generate;
|
end generate;
|
|
|
pl : if TARGET_CLK /= gen generate
|
pl : if TARGET_CLK /= gen generate
|
plllock_pad : outpad generic map (2) port map (cgo.clklock, plllock);
|
plllock_pad : outpad generic map (2) port map (cgo.clklock, plllock);
|
end generate;
|
end generate;
|
|
|
pcictrl0 : if PCICORE /= opencores generate
|
pcictrl0 : if PCICORE /= opencores generate
|
pci_trdy_en <= pcio.pci_ctrl_en_n;
|
pci_trdy_en <= pcio.pci_ctrl_en_n;
|
pci_devsel_en <= pcio.pci_ctrl_en_n;
|
pci_devsel_en <= pcio.pci_ctrl_en_n;
|
pci_stop_en <= pcio.pci_ctrl_en_n;
|
pci_stop_en <= pcio.pci_ctrl_en_n;
|
end generate;
|
end generate;
|
|
|
pcictrl1 : if PCICORE = opencores generate
|
pcictrl1 : if PCICORE = opencores generate
|
pci_trdy_en <= pcio.pci_trdy_en_n;
|
pci_trdy_en <= pcio.pci_trdy_en_n;
|
pci_devsel_en <= pcio.pci_devsel_en_n;
|
pci_devsel_en <= pcio.pci_devsel_en_n;
|
pci_stop_en <= pcio.pci_stop_en_n;
|
pci_stop_en <= pcio.pci_stop_en_n;
|
|
|
end generate;
|
end generate;
|
|
|
pcictrl2 : if PCIEN generate
|
pcictrl2 : if PCIEN generate
|
pci_aden <= pcio.pci_aden_n;
|
pci_aden <= pcio.pci_aden_n;
|
pci_cbeen(0) <= pcio.pci_cbe0_en_n;
|
pci_cbeen(0) <= pcio.pci_cbe0_en_n;
|
pci_cbeen(1) <= pcio.pci_cbe1_en_n;
|
pci_cbeen(1) <= pcio.pci_cbe1_en_n;
|
pci_cbeen(2) <= pcio.pci_cbe2_en_n;
|
pci_cbeen(2) <= pcio.pci_cbe2_en_n;
|
pci_cbeen(3) <= pcio.pci_cbe3_en_n;
|
pci_cbeen(3) <= pcio.pci_cbe3_en_n;
|
pci_frame_en <= pcio.pci_frame_en_n;
|
pci_frame_en <= pcio.pci_frame_en_n;
|
pci_irdy_en <= pcio.pci_irdy_en_n;
|
pci_irdy_en <= pcio.pci_irdy_en_n;
|
pci_perr_en <= pcio.pci_perr_en_n;
|
pci_perr_en <= pcio.pci_perr_en_n;
|
pci_par_en <= pcio.pci_par_en_n;
|
pci_par_en <= pcio.pci_par_en_n;
|
pci_req_en <= pcio.pci_req_en_n;
|
pci_req_en <= pcio.pci_req_en_n;
|
pci_serr_en <= pcio.pci_serr_out_n; -- open drain pad!
|
pci_serr_en <= pcio.pci_serr_out_n; -- open drain pad!
|
pci_lock_en <= '1'; -- is-core has no lock output -> deactivate
|
pci_lock_en <= '1'; -- is-core has no lock output -> deactivate
|
pci_lock_out <= '0'; -- dont care this output
|
pci_lock_out <= '0'; -- dont care this output
|
end generate;
|
end generate;
|
|
|
pci_rst_in_n_pad : pciinpad port map(pci_rst_in_n, pcii.pci_rst_in_n);
|
pci_rst_in_n_pad : pciinpad port map(pci_rst_in_n, pcii.pci_rst_in_n);
|
-- pci_clk_in_pad : inpad port map(pci_clk_in, pci_clk);
|
-- pci_clk_in_pad : inpad port map(pci_clk_in, pci_clk);
|
pci_clk <= pci_clk_in;
|
pci_clk <= pci_clk_in;
|
pci_gnt_in_n_pad : pciinpad port map(pci_gnt_in_n, pcii.pci_gnt_in_n);
|
pci_gnt_in_n_pad : pciinpad port map(pci_gnt_in_n, pcii.pci_gnt_in_n);
|
pci_idsel_in_pad : pciinpad port map(pci_idsel_in, pcii.pci_idsel_in); -- ignored in host bridge core
|
pci_idsel_in_pad : pciinpad port map(pci_idsel_in, pcii.pci_idsel_in); -- ignored in host bridge core
|
-- pci_lock_in_n_pad : inpad port map(pci_lock_in_n, pcii.pci_lock_in_n); -- Phoenix core: input only
|
-- pci_lock_in_n_pad : inpad port map(pci_lock_in_n, pcii.pci_lock_in_n); -- Phoenix core: input only
|
pci_lock_n_pad : pciiopad port map(pci_lock_out, pci_lock_en, pcii.pci_lock_in_n, pci_lock_n);
|
pci_lock_n_pad : pciiopad port map(pci_lock_out, pci_lock_en, pcii.pci_lock_in_n, pci_lock_n);
|
|
|
|
|
|
|
pci_ad_pads : for i in 0 to 31 generate
|
pci_ad_pads : for i in 0 to 31 generate
|
pci_adio_pad : pciiopad
|
pci_adio_pad : pciiopad
|
port map(pcio.pci_adout(i), pci_aden(i), pcii.pci_adin(i), pci_ad(i));
|
port map(pcio.pci_adout(i), pci_aden(i), pcii.pci_adin(i), pci_ad(i));
|
end generate pci_ad_pads;
|
end generate pci_ad_pads;
|
|
|
pci_cbe_n_pads : for i in 0 to 3 generate
|
pci_cbe_n_pads : for i in 0 to 3 generate
|
pci_cbeio_n_pad : pciiopad
|
pci_cbeio_n_pad : pciiopad
|
port map(pcio.pci_cbeout_n(i), pci_cbeen(i), pcii.pci_cbein_n(i), pci_cbe_n(i));
|
port map(pcio.pci_cbeout_n(i), pci_cbeen(i), pcii.pci_cbein_n(i), pci_cbe_n(i));
|
end generate pci_cbe_n_pads;
|
end generate pci_cbe_n_pads;
|
|
|
pci_frame_io_n_pad : pciiopad port map
|
pci_frame_io_n_pad : pciiopad port map
|
(pcio.pci_frame_out_n, pci_frame_en, pcii.pci_frame_in_n, pci_frame_n);
|
(pcio.pci_frame_out_n, pci_frame_en, pcii.pci_frame_in_n, pci_frame_n);
|
|
|
pci_irdy_io_n_pad : pciiopad port map
|
pci_irdy_io_n_pad : pciiopad port map
|
(pcio.pci_irdy_out_n, pci_irdy_en, pcii.pci_irdy_in_n, pci_irdy_n);
|
(pcio.pci_irdy_out_n, pci_irdy_en, pcii.pci_irdy_in_n, pci_irdy_n);
|
|
|
pci_trdy_io_n_pad : pciiopad port map
|
pci_trdy_io_n_pad : pciiopad port map
|
(pcio.pci_trdy_out_n, pci_trdy_en, pcii.pci_trdy_in_n, pci_trdy_n);
|
(pcio.pci_trdy_out_n, pci_trdy_en, pcii.pci_trdy_in_n, pci_trdy_n);
|
pci_devsel_io_n_pad : pciiopad port map
|
pci_devsel_io_n_pad : pciiopad port map
|
(pcio.pci_devsel_out_n, pci_devsel_en, pcii.pci_devsel_in_n, pci_devsel_n);
|
(pcio.pci_devsel_out_n, pci_devsel_en, pcii.pci_devsel_in_n, pci_devsel_n);
|
pci_stop_io_n_pad : pciiopad port map
|
pci_stop_io_n_pad : pciiopad port map
|
(pcio.pci_stop_out_n, pci_stop_en, pcii.pci_stop_in_n, pci_stop_n);
|
(pcio.pci_stop_out_n, pci_stop_en, pcii.pci_stop_in_n, pci_stop_n);
|
|
|
pci_perr_io_n_pad : pciiopad port map
|
pci_perr_io_n_pad : pciiopad port map
|
(pcio.pci_perr_out_n, pci_perr_en, pcii.pci_perr_in_n, pci_perr_n);
|
(pcio.pci_perr_out_n, pci_perr_en, pcii.pci_perr_in_n, pci_perr_n);
|
|
|
pci_par_io_pad : pciiopad port map
|
pci_par_io_pad : pciiopad port map
|
(pcio.pci_par_out, pci_par_en, pcii.pci_par_in, pci_par);
|
(pcio.pci_par_out, pci_par_en, pcii.pci_par_in, pci_par);
|
|
|
pci_req_io_n_pad : pciiopad port map -- tristate pad but never read
|
pci_req_io_n_pad : pciiopad port map -- tristate pad but never read
|
(pcio.pci_req_out_n, pci_req_en, pci_req_in_dummy, pci_req_n);
|
(pcio.pci_req_out_n, pci_req_en, pci_req_in_dummy, pci_req_n);
|
|
|
-- open drain bidir
|
-- open drain bidir
|
pci_serr_n_pad : pciiodpad port map (pci_serr_en, pcii.pci_serr_in_n, pci_serr_n);
|
pci_serr_n_pad : pciiodpad port map (pci_serr_en, pcii.pci_serr_in_n, pci_serr_n);
|
|
|
-- PCI host select
|
-- PCI host select
|
pci_host_pad : inpad port map (pci_host, pcii.pci_host);
|
pci_host_pad : inpad port map (pci_host, pcii.pci_host);
|
|
|
-- Optional PCI arbiter
|
-- Optional PCI arbiter
|
|
|
parb1 : if PCIARBEN generate
|
parb1 : if PCIARBEN generate
|
pgnt : for i in 0 to 3 generate
|
pgnt : for i in 0 to 3 generate
|
pcignt : pcioutpad port map (ioo.pci_arb_gnt_n(i), pci_arb_gnt_n(i));
|
pcignt : pcioutpad port map (ioo.pci_arb_gnt_n(i), pci_arb_gnt_n(i));
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
|
|
parb2 : if PCIARBEN generate
|
parb2 : if PCIARBEN generate
|
preq : for i in 0 to 3 generate
|
preq : for i in 0 to 3 generate
|
pcireq : inpad port map (pci_arb_req_n(i), ioi.pci_arb_req_n(i));
|
pcireq : inpad port map (pci_arb_req_n(i), ioi.pci_arb_req_n(i));
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
-- Optional 66 MHz pad
|
-- Optional 66 MHz pad
|
p66 : if PCI66PADEN generate
|
p66 : if PCI66PADEN generate
|
pci_66_pad : inpad port map(pci_66, pcii.pci_66);
|
pci_66_pad : inpad port map(pci_66, pcii.pci_66);
|
end generate;
|
end generate;
|
np66 : if not PCI66PADEN generate
|
np66 : if not PCI66PADEN generate
|
pcii.pci_66 <= '0';
|
pcii.pci_66 <= '0';
|
end generate;
|
end generate;
|
|
|
-- Optional power control pads
|
-- Optional power control pads
|
|
|
pme : if PCIPMEEN generate
|
pme : if PCIPMEEN generate
|
pmes : for i in 1 downto 0 generate
|
pmes : for i in 1 downto 0 generate
|
power_state_pad : pcioutpad port map (pcio.power_state(i), power_state(i));
|
power_state_pad : pcioutpad port map (pcio.power_state(i), power_state(i));
|
end generate;
|
end generate;
|
pme_enable_pad : pcioutpad port map (pcio.pme_enable, pme_enable);
|
pme_enable_pad : pcioutpad port map (pcio.pme_enable, pme_enable);
|
pme_clear_pad : pcioutpad port map (pcio.pme_clear, pme_clear);
|
pme_clear_pad : pcioutpad port map (pcio.pme_clear, pme_clear);
|
pme_status_pad : inpad port map(pme_status, pcii.pme_status);
|
pme_status_pad : inpad port map(pme_status, pcii.pme_status);
|
end generate;
|
end generate;
|
npme : if not PCIPMEEN generate
|
npme : if not PCIPMEEN generate
|
pcii.pme_status <= '0';
|
pcii.pme_status <= '0';
|
end generate;
|
end generate;
|
|
|
eth_pads : if ETHEN generate
|
eth_pads : if ETHEN generate
|
emdio_pad : iopad generic map (2) port map (etho.mdio_o, etho.mdio_oe, ethi.mdio_i, emdio);
|
emdio_pad : iopad generic map (2) port map (etho.mdio_o, etho.mdio_oe, ethi.mdio_i, emdio);
|
etx_clk_pad : inpad port map (etx_clk, ethi.tx_clk);
|
etx_clk_pad : inpad port map (etx_clk, ethi.tx_clk);
|
erx_clk_pad : inpad port map (erx_clk, ethi.rx_clk);
|
erx_clk_pad : inpad port map (erx_clk, ethi.rx_clk);
|
erxd_pads: for i in 0 to 3 generate -- data bus
|
erxd_pads: for i in 0 to 3 generate -- data bus
|
erxd_pad : inpad port map (erxd(i), ethi.rxd(i));
|
erxd_pad : inpad port map (erxd(i), ethi.rxd(i));
|
end generate;
|
end generate;
|
erx_dv_pad : inpad port map (erx_dv, ethi.rx_dv);
|
erx_dv_pad : inpad port map (erx_dv, ethi.rx_dv);
|
erx_er_pad : inpad port map (erx_er, ethi.rx_er);
|
erx_er_pad : inpad port map (erx_er, ethi.rx_er);
|
erx_col_pad : inpad port map (erx_col, ethi.rx_col);
|
erx_col_pad : inpad port map (erx_col, ethi.rx_col);
|
erx_crs_pad : inpad port map (erx_crs, ethi.rx_crs);
|
erx_crs_pad : inpad port map (erx_crs, ethi.rx_crs);
|
etxd_pads: for i in 0 to 3 generate -- data bus
|
etxd_pads: for i in 0 to 3 generate -- data bus
|
etxd_pad : outpad generic map (1) port map (etho.txd(i), etxd(i));
|
etxd_pad : outpad generic map (1) port map (etho.txd(i), etxd(i));
|
end generate;
|
end generate;
|
etx_en_pad : outpad generic map (1) port map (etho.tx_en, etx_en);
|
etx_en_pad : outpad generic map (1) port map (etho.tx_en, etx_en);
|
etx_er_pad : outpad generic map (1) port map (etho.tx_er, etx_er);
|
etx_er_pad : outpad generic map (1) port map (etho.tx_er, etx_er);
|
emdc_pad : outpad generic map (1) port map (etho.mdc, emdc);
|
emdc_pad : outpad generic map (1) port map (etho.mdc, emdc);
|
|
|
emddis_pad : outpad generic map (1) port map (gnd, emddis);
|
emddis_pad : outpad generic map (1) port map (gnd, emddis);
|
epwrdwn_pad : outpad generic map (1) port map (gnd, epwrdwn);
|
epwrdwn_pad : outpad generic map (1) port map (gnd, epwrdwn);
|
ereset_pad : outpad generic map (1) port map (vcc, etho.reset);
|
ereset_pad : outpad generic map (1) port map (vcc, etho.reset);
|
esleep_pad : outpad generic map (1) port map (vcc, esleep);
|
esleep_pad : outpad generic map (1) port map (vcc, esleep);
|
epause_pad : outpad generic map (1) port map (gnd, epause);
|
epause_pad : outpad generic map (1) port map (gnd, epause);
|
end generate;
|
end generate;
|
|
|
end ;
|
end ;
|
|
|
|
|