/*
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/*
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* None pipelined, 3-state, 16-bit CPU
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* None pipelined, 3-state, 16-bit CPU
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*
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*
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* Copyright (C) 2019, Yvo Zoer
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* Copyright (C) 2019, Yvo Zoer
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* of the License, or (at your option) any later version.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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*/
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// comment this line out to use LE's (warning: size goes up dramatically to around 800LE's)
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`define USE_RAM_FOR_REGFILE
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module cpu16 (
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module cpu16 (
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clk,
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clk,
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reset_n,
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reset_n,
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clk_en,
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clk_en,
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address,
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address,
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din,
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din,
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dout,
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dout,
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cs_n,
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cs_n,
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oe_n,
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oe_n,
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we_n,
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we_n,
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ub_n,
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ub_n,
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lb_n,
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lb_n,
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irq, // combined interrupt request from intc
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irq, // combined interrupt request from intc
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busreq,
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busreq,
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busack
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busack
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);
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);
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input clk;
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input clk;
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input reset_n;
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input reset_n;
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output [15:0] address;
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output [15:0] address;
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input clk_en;
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input clk_en;
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input [15:0] din;
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input [15:0] din;
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output [15:0] dout;
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output [15:0] dout;
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output cs_n;
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output cs_n;
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output oe_n;
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output oe_n;
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output we_n;
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output we_n;
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output ub_n;
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output ub_n;
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output lb_n;
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output lb_n;
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input irq;
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input irq;
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input busreq;
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input busreq;
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output busack;
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output busack;
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// alu
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// alu
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parameter OP_SUB = 5'd0; // ok
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parameter OP_SUB = 5'd0; // ok
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parameter OP_SBC = 5'd1; // ok
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parameter OP_SBC = 5'd1; // ok
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parameter OP_ADD = 5'd2;
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parameter OP_ADD = 5'd2;
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parameter OP_ADC = 5'd3;
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parameter OP_ADC = 5'd3;
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parameter OP_CMP = 5'd4;
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parameter OP_CMP = 5'd4;
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parameter OP_AND = 5'd5; // ok
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parameter OP_AND = 5'd5; // ok
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parameter OP_OR = 5'd6; // ok
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parameter OP_OR = 5'd6; // ok
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parameter OP_XOR = 5'd7; // ok
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parameter OP_XOR = 5'd7; // ok
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// alu immediate
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// alu immediate
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parameter OP_SUBI = 5'd8; // ok
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parameter OP_SUBI = 5'd8; // ok
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parameter OP_SBCI = 5'd9; // ok
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parameter OP_SBCI = 5'd9; // ok
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parameter OP_ADDI = 5'd10; // ok
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parameter OP_ADDI = 5'd10; // ok
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parameter OP_ADCI = 5'd11; // ok
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parameter OP_ADCI = 5'd11; // ok
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parameter OP_CMPI = 5'd12;
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parameter OP_CMPI = 5'd12;
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parameter OP_ANDI = 5'd13; // ok
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parameter OP_ANDI = 5'd13; // ok
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parameter OP_ORI = 5'd14; // ok
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parameter OP_ORI = 5'd14; // ok
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parameter OP_XORI = 5'd15; // ok
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parameter OP_XORI = 5'd15; // ok
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// shifter + load
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// shifter + load
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parameter OP_MOV = 5'd16;
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parameter OP_MOV = 5'd16;
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parameter OP_SRAV = 5'd17;
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parameter OP_SRAV = 5'd17;
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parameter OP_SLLV = 5'd18;
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parameter OP_SLLV = 5'd18;
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parameter OP_LD = 5'd19;
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parameter OP_LD = 5'd19;
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// shifter immediate + store
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// shifter immediate + store
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parameter OP_LUI = 5'd20;
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parameter OP_LUI = 5'd20;
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parameter OP_SRA = 5'd21;
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parameter OP_SRA = 5'd21;
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parameter OP_SLL = 5'd22;
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parameter OP_SLL = 5'd22;
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parameter OP_ST = 5'd23;
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parameter OP_ST = 5'd23;
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// jump
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// jump
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parameter OP_J = 5'd24;
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parameter OP_J = 5'd24;
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parameter OP_JAL = 5'd25;
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parameter OP_JAL = 5'd25;
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parameter OP_JR = 5'd26;
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parameter OP_JR = 5'd26;
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parameter OP_JALR = 5'd27;
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parameter OP_JALR = 5'd27;
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// conditional branch
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// conditional branch
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parameter OP_BXX = 5'd28;
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parameter OP_BXX = 5'd28;
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parameter OP_MSR = 5'd29;
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parameter OP_MSR = 5'd29;
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parameter OP_RFE = 5'd30;
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parameter OP_RFE = 5'd30;
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parameter OP_SWI = 5'd31;
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parameter OP_SWI = 5'd31;
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// states
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// states
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parameter STATE_FETCH = 4'h0;
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parameter STATE_FETCH = 4'h0;
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parameter STATE_DECODE = 4'h1;
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parameter STATE_DECODE = 4'h1;
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parameter STATE_ALU = 4'h2;
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parameter STATE_ALU = 4'h2;
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parameter STATE_SHIFT = 4'h3;
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parameter STATE_SHIFT = 4'h3;
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parameter STATE_LOAD = 4'h4;
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parameter STATE_LOAD = 4'h4;
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parameter STATE_STORE = 4'h5;
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parameter STATE_STORE = 4'h5;
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parameter STATE_J = 4'h6;
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parameter STATE_J = 4'h6;
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parameter STATE_JAL = 4'h7;
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parameter STATE_JAL = 4'h7;
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parameter STATE_BRANCH = 4'h8;
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parameter STATE_BRANCH = 4'h8;
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parameter STATE_MOVSR = 4'h9;
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parameter STATE_MOVSR = 4'h9;
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parameter STATE_RFE = 4'ha;
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parameter STATE_RFE = 4'ha;
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parameter STATE_SWI = 4'hb;
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parameter STATE_SWI = 4'hb;
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parameter STATE_INTREQ = 4'hc;
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parameter STATE_INTREQ = 4'hc;
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parameter STATE_BUSREQ = 4'hd;
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parameter STATE_BUSREQ = 4'hd;
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// instruction register wires
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// instruction register wires
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wire [4:0] ir_opcode = ir[15:11];
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wire [4:0] ir_opcode = ir[15:11];
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wire [2:0] ir_dst = ir[10:8];
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wire [2:0] ir_dst = ir[10:8];
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wire [2:0] ir_src = ir[7:5];
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wire [2:0] ir_src = ir[7:5];
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wire ir_size = ir[4]; // byte/word flag
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wire ir_size = ir[4]; // byte/word flag
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wire [3:0] ir_imm4 = ir[3:0]; // load/store offset
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wire [3:0] ir_imm4 = ir[3:0]; // load/store offset
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wire [7:0] ir_imm8 = ir[7:0]; // immediate value / relative conditional branch
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wire [7:0] ir_imm8 = ir[7:0]; // immediate value / relative conditional branch
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wire [10:0] ir_imm11 = ir[10:0]; // unconditional branch
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wire [10:0] ir_imm11 = ir[10:0]; // unconditional branch
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// busack valid once we're in the busreq state
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// busack valid once we're in the busreq state
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reg busack;
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reg busack;
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always @(*)
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always @(*)
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if ( state == STATE_BUSREQ )
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if ( state == STATE_BUSREQ )
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busack = 1'b1;
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busack = 1'b1;
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else
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else
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busack = 1'b0;
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busack = 1'b0;
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// chip-select
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// chip-select
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reg cs_n;
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reg cs_n;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_FETCH,
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STATE_FETCH,
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STATE_LOAD,
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STATE_LOAD,
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STATE_STORE : cs_n = 1'b0;
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STATE_STORE : cs_n = 1'b0;
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default : cs_n = 1'b1;
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default : cs_n = 1'b1;
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endcase
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endcase
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// output enable
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// output enable
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reg oe_n;
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reg oe_n;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_FETCH,
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STATE_FETCH,
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STATE_LOAD : oe_n = 1'b0;
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STATE_LOAD : oe_n = 1'b0;
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default : oe_n = 1'b1;
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default : oe_n = 1'b1;
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endcase
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endcase
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// memory write signal
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// memory write signal
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reg we_n;
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reg we_n;
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always @(posedge clk)
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always @(posedge clk)
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if ( state == STATE_STORE )
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if ( state == STATE_STORE )
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we_n <= clk_en;
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we_n <= clk_en;
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else
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else
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we_n <= 1'b1;
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we_n <= 1'b1;
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// upper / lower byte write/read enable
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// upper / lower byte write/read enable
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// NOTE: could integrate dout here as well..
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// NOTE: could integrate dout here as well..
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reg ub_n;
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reg ub_n;
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reg lb_n;
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reg lb_n;
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always @(*)
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always @(*)
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if ( state == STATE_STORE )
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if ( state == STATE_STORE )
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begin
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begin
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if ( ir_size )
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if ( ir_size )
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begin // word
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begin // word
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ub_n = 1'b0;
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ub_n = 1'b0;
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lb_n = 1'b0;
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lb_n = 1'b0;
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end
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end
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else
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else
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begin // byte
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begin // byte
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if ( address[0] )
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if ( address[0] )
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begin
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begin
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ub_n = 1'b1;
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ub_n = 1'b1;
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lb_n = 1'b0;
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lb_n = 1'b0;
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end
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end
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else
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else
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begin
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begin
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ub_n = 1'b0;
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ub_n = 1'b0;
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lb_n = 1'b1;
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lb_n = 1'b1;
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end
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end
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end
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end
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end
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end
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else
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else
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begin // word access for everything else
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begin // word access for everything else
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ub_n = 1'b0;
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ub_n = 1'b0;
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lb_n = 1'b0;
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lb_n = 1'b0;
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end
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end
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// data output logic
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// data output logic
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reg [15:0] dout;
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reg [15:0] dout;
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always @(*)
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always @(*)
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if ( ir_size )
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if ( ir_size )
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dout = qa; // word
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dout = qa; // word
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else
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else
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begin
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begin
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if ( address[0] )
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if ( address[0] )
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dout = { 8'h00, qa[7:0] };
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dout = { 8'h00, qa[7:0] };
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else
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else
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dout = { qa[7:0], 8'h00 };
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dout = { qa[7:0], 8'h00 };
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end
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end
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// address mux
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// address mux
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reg [15:0] address;
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reg [15:0] address;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_LOAD,
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STATE_LOAD,
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STATE_STORE : address = qb + ir_imm4;
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STATE_STORE : address = qb + ir_imm4;
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default : address = pc; // { pc[15:1], 1'b0 };
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default : address = pc; // { pc[15:1], 1'b0 };
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endcase
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endcase
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// main state machine
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// main state machine
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reg [3:0] state, next_state;
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reg [3:0] state, next_state;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_FETCH : next_state = STATE_DECODE;
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STATE_FETCH : next_state = STATE_DECODE;
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STATE_DECODE : begin
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STATE_DECODE : begin
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casex (ir_opcode)
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casex (ir_opcode)
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5'b0xxxx : next_state = STATE_ALU; // sub/sbc/add/adc/and/or/xor/cmp
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5'b0xxxx : next_state = STATE_ALU; // sub/sbc/add/adc/and/or/xor/cmp
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5'b10x0x,
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5'b10x0x,
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5'b10x10 : next_state = STATE_SHIFT;
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5'b10x10 : next_state = STATE_SHIFT;
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5'b10011 : next_state = STATE_LOAD;
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5'b10011 : next_state = STATE_LOAD;
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5'b10111 : next_state = STATE_STORE;
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5'b10111 : next_state = STATE_STORE;
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5'b110x0 : next_state = STATE_J; // 24/26
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5'b110x0 : next_state = STATE_J; // 24/26
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5'b110x1 : next_state = STATE_JAL; // 25/27
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5'b110x1 : next_state = STATE_JAL; // 25/27
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5'b11100 : next_state = STATE_BRANCH;
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5'b11100 : next_state = STATE_BRANCH;
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5'b11101 : next_state = STATE_MOVSR;
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5'b11101 : next_state = STATE_MOVSR;
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5'b11110 : next_state = STATE_RFE;
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5'b11110 : next_state = STATE_RFE;
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5'b11111 : next_state = STATE_SWI;
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5'b11111 : next_state = STATE_SWI;
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default : next_state = STATE_FETCH;
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default : next_state = STATE_FETCH;
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endcase
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endcase
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end
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end
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STATE_INTREQ : next_state = STATE_FETCH;
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STATE_INTREQ : next_state = STATE_FETCH;
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STATE_BUSREQ : begin
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STATE_BUSREQ : begin
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if ( busreq )
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if ( busreq )
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next_state = STATE_BUSREQ;
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next_state = STATE_BUSREQ;
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else
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else
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next_state = STATE_FETCH; // will miss interrupt when coming out of busreq (STATE_NOP?)
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next_state = STATE_FETCH; // will miss interrupt when coming out of busreq (STATE_NOP?)
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end
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end
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default : begin
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default : begin
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if ( busreq )
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if ( busreq )
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next_state = STATE_BUSREQ;
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next_state = STATE_BUSREQ;
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else if ( irq & i ) // only fires when interrupt enable is set (i = 1)
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else if ( irq & i ) // only fires when interrupt enable is set (i = 1)
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next_state = STATE_INTREQ;
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next_state = STATE_INTREQ;
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else
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else
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next_state = STATE_FETCH;
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next_state = STATE_FETCH;
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end
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end
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endcase
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endcase
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// instruction register
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// instruction register
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reg [15:0] ir, next_ir;
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reg [15:0] ir, next_ir;
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always @(*)
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always @(*)
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if ( state == STATE_FETCH )
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if ( state == STATE_FETCH )
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next_ir = din;
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next_ir = din;
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else
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else
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next_ir = ir;
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next_ir = ir;
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// exception pc- and status register
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// exception pc- and status register
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reg [15:0] epc, next_epc;
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reg [15:0] epc, next_epc;
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reg [4:0] esr, next_esr;
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reg [4:0] esr, next_esr;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_INTREQ : begin
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STATE_INTREQ : begin
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next_epc = pc;
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next_epc = pc;
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next_esr = { i,n,v,z,c };
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next_esr = { i,n,v,z,c };
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end
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end
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default : begin
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default : begin
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next_epc = epc;
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next_epc = epc;
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next_esr = esr;
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next_esr = esr;
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end
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end
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endcase
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endcase
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// source data for program counter ( register / immediate )
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// source data for program counter ( register / immediate )
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reg [15:0] pc_data;
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reg [15:0] pc_data;
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always @(*)
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always @(*)
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if ( ir_opcode[1] ) // immediate for PC
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if ( ir_opcode[1] ) // immediate for PC
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pc_data = qb; //{ qb[15:1], 1'b0 }; // TEST: jr/jalr
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pc_data = qb; //{ qb[15:1], 1'b0 }; // TEST: jr/jalr
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else
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else
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pc_data = pc + { { 4 { ir_imm11[10] } }, ir_imm11[10:0], 1'b0 }; // TEST: j/jal doubled for jumps
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pc_data = pc + { { 4 { ir_imm11[10] } }, ir_imm11[10:0], 1'b0 }; // TEST: j/jal doubled for jumps
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// condition check
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// condition check
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reg condition_true;
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reg condition_true;
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always @(*)
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always @(*)
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case (ir_dst)
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case (ir_dst)
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3'd0 : condition_true = z;
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3'd0 : condition_true = z;
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3'd1 : condition_true = ~z;
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3'd1 : condition_true = ~z;
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3'd2 : condition_true = ~n;
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3'd2 : condition_true = ~n;
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3'd3 : condition_true = n;
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3'd3 : condition_true = n;
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3'd4 : condition_true = ~c;
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3'd4 : condition_true = ~c;
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3'd5 : condition_true = c;
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3'd5 : condition_true = c;
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3'd6 : condition_true = ~v;
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3'd6 : condition_true = ~v;
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3'd7 : condition_true = v;
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3'd7 : condition_true = v;
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endcase
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endcase
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// program counter
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// program counter
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reg [15:0] pc, next_pc;
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reg [15:0] pc, next_pc;
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always @(*)
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always @(*)
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case (state)
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case (state)
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STATE_FETCH : next_pc = pc + 16'd2;
|
STATE_FETCH : next_pc = pc + 16'd2;
|
STATE_SWI : next_pc = { ir_imm8, 1'b0 };
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STATE_SWI : next_pc = { ir_imm8, 1'b0 };
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STATE_J,
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STATE_J,
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STATE_JAL : next_pc = pc_data;
|
STATE_JAL : next_pc = pc_data;
|
STATE_BRANCH : begin
|
STATE_BRANCH : begin
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if ( condition_true )
|
if ( condition_true )
|
next_pc = pc + { { 7 { ir_imm8[7] } }, ir_imm8[7:0], 1'b0 };
|
next_pc = pc + { { 7 { ir_imm8[7] } }, ir_imm8[7:0], 1'b0 };
|
else
|
else
|
next_pc = pc;
|
next_pc = pc;
|
end
|
end
|
STATE_INTREQ : next_pc = 16'h0002; // interrupt vector appears at 0x0002
|
STATE_INTREQ : next_pc = 16'h0002; // interrupt vector appears at 0x0002
|
STATE_RFE : next_pc = epc;
|
STATE_RFE : next_pc = epc;
|
default : next_pc = pc;
|
default : next_pc = pc;
|
endcase
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endcase
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|
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// alu data mux
|
// alu data mux
|
reg [15:0] alu_data;
|
reg [15:0] alu_data;
|
always @(*)
|
always @(*)
|
if (ir_opcode[3]) // immediate
|
if (ir_opcode[3]) // immediate
|
alu_data = { 8'h00, ir_imm8 };
|
alu_data = { 8'h00, ir_imm8 };
|
else
|
else
|
alu_data = qb; // register
|
alu_data = qb; // register
|
|
|
// alu
|
// alu
|
wire [15:0] alu_result;
|
wire [15:0] alu_result;
|
wire alu_n;
|
wire alu_n;
|
wire alu_v;
|
wire alu_v;
|
wire alu_z;
|
wire alu_z;
|
wire alu_c;
|
wire alu_c;
|
alu i_alu (
|
alu i_alu (
|
.a(qa),
|
.a(qa),
|
.b(alu_data),
|
.b(alu_data),
|
.c_in(c),
|
.c_in(c),
|
.func(ir_opcode[2:0]),
|
.func(ir_opcode[2:0]),
|
.result(alu_result),
|
.result(alu_result),
|
.n(alu_n),
|
.n(alu_n),
|
.v(alu_v),
|
.v(alu_v),
|
.z(alu_z),
|
.z(alu_z),
|
.c(alu_c)
|
.c(alu_c)
|
);
|
);
|
|
|
// shifter data mux
|
// shifter data mux
|
reg [15:0] shifter_data;
|
reg [15:0] shifter_data;
|
always @(*)
|
always @(*)
|
if ( ir_opcode[2] ) // immediate
|
if ( ir_opcode[2] ) // immediate
|
shifter_data = { ir_imm8, 8'h00 }; // lui from instruction word
|
shifter_data = { ir_imm8, 8'h00 }; // lui from instruction word
|
else
|
else
|
shifter_data = qb; // mov
|
shifter_data = qb; // mov
|
|
|
// shifter distance -- roll into b argument inside shifter?
|
// shifter distance -- roll into b argument inside shifter?
|
reg [3:0] shift_distance;
|
reg [3:0] shift_distance;
|
always @(*)
|
always @(*)
|
if ( ir_opcode[2] )
|
if ( ir_opcode[2] )
|
shift_distance = ir_imm4;
|
shift_distance = ir_imm4;
|
else
|
else
|
shift_distance = qb[3:0];
|
shift_distance = qb[3:0];
|
|
|
// shifter
|
// shifter
|
wire [15:0] shifter_result;
|
wire [15:0] shifter_result;
|
wire shift_n;
|
wire shift_n;
|
wire shift_z;
|
wire shift_z;
|
wire shift_c;
|
wire shift_c;
|
wire shift_v;
|
wire shift_v;
|
shifter i_shifter (
|
shifter i_shifter (
|
.a(qa),
|
.a(qa),
|
.b(shifter_data),
|
.b(shifter_data),
|
.n_in(n),
|
.n_in(n),
|
.v_in(v),
|
.v_in(v),
|
.z_in(z),
|
.z_in(z),
|
.c_in(c),
|
.c_in(c),
|
.distance(shift_distance),
|
.distance(shift_distance),
|
.func(ir_opcode[1:0]),
|
.func(ir_opcode[1:0]),
|
.result(shifter_result),
|
.result(shifter_result),
|
.n(shift_n),
|
.n(shift_n),
|
.v(shift_v),
|
.v(shift_v),
|
.z(shift_z),
|
.z(shift_z),
|
.c(shift_c)
|
.c(shift_c)
|
);
|
);
|
|
|
// memory data mux for lw/lb
|
// memory data mux for lw/lb
|
reg [15:0] mem_data;
|
reg [15:0] mem_data;
|
always @(*)
|
always @(*)
|
if ( ir_size )
|
if ( ir_size )
|
mem_data = din;
|
mem_data = din;
|
else
|
else
|
begin
|
begin
|
if ( address[0] )
|
if ( address[0] )
|
mem_data = { 8'h00, din[7:0] };
|
mem_data = { 8'h00, din[7:0] };
|
else
|
else
|
mem_data = { 8'h00, din[15:8] };
|
mem_data = { 8'h00, din[15:8] };
|
end
|
end
|
|
|
// register data
|
// register data
|
reg [15:0] reg_data;
|
reg [15:0] reg_data;
|
always @(*)
|
always @(*)
|
case (state)
|
case (state)
|
STATE_ALU : reg_data = alu_result;
|
STATE_ALU : reg_data = alu_result;
|
STATE_SHIFT : reg_data = shifter_result;
|
STATE_SHIFT : reg_data = shifter_result;
|
STATE_JAL,
|
STATE_JAL,
|
STATE_SWI : reg_data = pc;
|
STATE_SWI : reg_data = pc;
|
default : reg_data = mem_data;
|
default : reg_data = mem_data;
|
endcase
|
endcase
|
|
|
// register writeback
|
// register writeback
|
reg reg_write;
|
reg reg_write;
|
always @(*)
|
always @(*)
|
case (state)
|
case (state)
|
STATE_ALU,
|
STATE_ALU,
|
STATE_SHIFT,
|
STATE_SHIFT,
|
STATE_LOAD,
|
STATE_LOAD,
|
STATE_JAL,
|
STATE_JAL,
|
STATE_SWI : reg_write = 1'b1;
|
STATE_SWI : reg_write = 1'b1;
|
default : reg_write = 1'b0;
|
default : reg_write = 1'b0;
|
endcase
|
endcase
|
|
|
// override dst address for JAL to save 3 bits
|
// override dst address for JAL to save 3 bits
|
reg [2:0] ra_dst;
|
reg [2:0] ra_dst;
|
always @(*)
|
always @(*)
|
if ( state == STATE_JAL )
|
if ( state == STATE_JAL )
|
ra_dst = 3'd6; // hard linked register
|
ra_dst = 3'd6; // hard linked register
|
else
|
else
|
ra_dst = ir_dst;
|
ra_dst = ir_dst;
|
|
|
// register file
|
// register file
|
|
`ifdef USE_RAM_FOR_REGFILE
|
wire [15:0] qa, qb;
|
wire [15:0] qa, qb;
|
regfile8x16 i_regfile (
|
regfile8x16 i_regfile (
|
.clock(clk),
|
.clock(clk),
|
.data(reg_data),
|
.data(reg_data),
|
.rdaddress_a(ir_dst),
|
.rdaddress_a(ir_dst),
|
.rdaddress_b(ir_src),
|
.rdaddress_b(ir_src),
|
.wraddress(ra_dst),
|
.wraddress(ra_dst),
|
.wren(reg_write&clk_en),
|
.wren(reg_write&clk_en),
|
.qa(qa),
|
.qa(qa),
|
.qb(qb)
|
.qb(qb)
|
);
|
);
|
|
`else
|
|
reg [15:0] regs[7:0];
|
|
always @(posedge clk)
|
|
if (reg_write&clk_en)
|
|
regs[ir_dst] <= reg_data;
|
|
wire [15:0] qa = regs[ir_dst];
|
|
wire [15:0] qb = regs[ir_src];
|
|
`endif
|
|
|
// flags
|
// flags
|
reg i, next_i;
|
reg i, next_i;
|
reg n, next_n;
|
reg n, next_n;
|
reg v, next_v;
|
reg v, next_v;
|
reg z, next_z;
|
reg z, next_z;
|
reg c, next_c;
|
reg c, next_c;
|
always @(*)
|
always @(*)
|
case (state)
|
case (state)
|
STATE_ALU : begin
|
STATE_ALU : begin
|
next_i = i;
|
next_i = i;
|
next_n = alu_n;
|
next_n = alu_n;
|
next_v = alu_v;
|
next_v = alu_v;
|
next_z = alu_z;
|
next_z = alu_z;
|
next_c = alu_c;
|
next_c = alu_c;
|
end
|
end
|
STATE_SHIFT : begin
|
STATE_SHIFT : begin
|
next_i = i;
|
next_i = i;
|
next_n = shift_n;
|
next_n = shift_n;
|
next_v = shift_v;
|
next_v = shift_v;
|
next_z = shift_z;
|
next_z = shift_z;
|
next_c = shift_c;
|
next_c = shift_c;
|
end
|
end
|
STATE_MOVSR : begin
|
STATE_MOVSR : begin
|
next_i = (i & ~ir_imm8[4]) | ( ir_imm8[7] & ir_imm8[4]);
|
next_i = (i & ~ir_imm8[4]) | ( ir_imm8[7] & ir_imm8[4]);
|
next_n = (n & ~ir_imm8[3]) | ( ir_imm8[7] & ir_imm8[3]);
|
next_n = (n & ~ir_imm8[3]) | ( ir_imm8[7] & ir_imm8[3]);
|
next_v = (v & ~ir_imm8[2]) | ( ir_imm8[7] & ir_imm8[2]);
|
next_v = (v & ~ir_imm8[2]) | ( ir_imm8[7] & ir_imm8[2]);
|
next_z = (z & ~ir_imm8[1]) | ( ir_imm8[7] & ir_imm8[1]);
|
next_z = (z & ~ir_imm8[1]) | ( ir_imm8[7] & ir_imm8[1]);
|
next_c = (c & ~ir_imm8[0]) | ( ir_imm8[7] & ir_imm8[0]);
|
next_c = (c & ~ir_imm8[0]) | ( ir_imm8[7] & ir_imm8[0]);
|
end
|
end
|
STATE_INTREQ : begin
|
STATE_INTREQ : begin
|
next_i = 1'b0; // disable interrupts
|
next_i = 1'b0; // disable interrupts
|
next_n = n;
|
next_n = n;
|
next_v = v;
|
next_v = v;
|
next_z = z;
|
next_z = z;
|
next_c = c;
|
next_c = c;
|
end
|
end
|
STATE_RFE : begin
|
STATE_RFE : begin
|
next_i = esr[4];
|
next_i = esr[4];
|
next_n = esr[3];
|
next_n = esr[3];
|
next_v = esr[2];
|
next_v = esr[2];
|
next_z = esr[1];
|
next_z = esr[1];
|
next_c = esr[0];
|
next_c = esr[0];
|
end
|
end
|
default : begin
|
default : begin
|
next_i = i;
|
next_i = i;
|
next_n = n;
|
next_n = n;
|
next_v = v;
|
next_v = v;
|
next_z = z;
|
next_z = z;
|
next_c = c;
|
next_c = c;
|
end
|
end
|
endcase
|
endcase
|
|
|
// synchronous writeback
|
// synchronous writeback
|
always @(posedge clk or negedge reset_n)
|
always @(posedge clk or negedge reset_n)
|
if (!reset_n)
|
if (!reset_n)
|
begin
|
begin
|
state <= STATE_FETCH;
|
state <= STATE_FETCH;
|
ir <= 16'd0;
|
ir <= 16'd0;
|
pc <= 16'd0;
|
pc <= 16'd0;
|
i <= 1'b1; // TEST: enable interrupts
|
i <= 1'b1; // TEST: enable interrupts
|
n <= 1'b0;
|
n <= 1'b0;
|
v <= 1'b0;
|
v <= 1'b0;
|
z <= 1'b0;
|
z <= 1'b0;
|
c <= 1'b0;
|
c <= 1'b0;
|
epc <= 16'd0;
|
epc <= 16'd0;
|
esr <= 5'd0;
|
esr <= 5'd0;
|
end
|
end
|
else if ( clk_en )
|
else if ( clk_en )
|
begin
|
begin
|
state <= next_state;
|
state <= next_state;
|
ir <= next_ir;
|
ir <= next_ir;
|
pc <= next_pc;
|
pc <= next_pc;
|
i <= next_i;
|
i <= next_i;
|
n <= next_n;
|
n <= next_n;
|
v <= next_v;
|
v <= next_v;
|
z <= next_z;
|
z <= next_z;
|
c <= next_c;
|
c <= next_c;
|
epc <= next_epc;
|
epc <= next_epc;
|
esr <= next_esr;
|
esr <= next_esr;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
