////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995-2003 Xilinx, Inc.
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// Copyright (c) 1995-2003 Xilinx, Inc.
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// All Right Reserved.
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// All Right Reserved.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// ____ ____
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// / /\/ /
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 8.2.02i
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// \ \ \/ Version : 8.2.02i
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// \ \ Application : ISE
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// \ \ Application : ISE
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// / / Filename : cpu_tbw.tfw
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// / / Filename : cpu_tbw.tfw
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// /___/ /\ Timestamp : Sat Oct 28 09:12:59 2006
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// /___/ /\ Timestamp : Sat Oct 28 09:12:59 2006
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// \ \ / \
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// \ \ / \
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// \___\/\___\
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// \___\/\___\
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//
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//
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//Command:
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//Command:
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//Design Name: cpu_tbw
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//Design Name: cpu_tbw
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//Device: Xilinx
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//Device: Xilinx
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//
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//
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module cpu_tbw;
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module cpu_tbw;
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wire [15:0] addr;
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wire [15:0] addr;
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reg [7:0] data$inout$reg = 8'bZ1Z00000;
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reg [7:0] data$inout$reg = 8'bZ1Z00000;
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wire [7:0] data = data$inout$reg;
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wire [7:0] data = data$inout$reg;
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wire readmem;
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wire readmem;
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wire writemem;
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wire writemem;
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wire readio;
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wire readio;
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wire writeio;
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wire writeio;
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wire intr;
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wire intr;
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wire inta;
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wire inta;
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reg waitr = 1'b0;
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reg waitr = 1'b0;
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wire [2:0] r;
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wire [2:0] r;
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wire [2:0] g;
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wire [2:0] g;
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wire [2:0] b;
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wire [2:0] b;
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wire hsync_n;
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wire hsync_n;
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wire vsync_n;
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wire vsync_n;
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reg reset = 1'b0;
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reg reset = 1'b0;
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reg clock = 1'b0;
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reg clock = 1'b0;
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parameter PERIOD = 200;
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parameter PERIOD = 200;
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parameter real DUTY_CYCLE = 0.5;
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parameter real DUTY_CYCLE = 0.5;
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parameter OFFSET = 0;
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parameter OFFSET = 0;
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initial // Clock process for clock
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initial // Clock process for clock
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begin
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begin
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#OFFSET;
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#OFFSET;
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forever
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forever
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begin
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begin
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clock = 1'b0;
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clock = 1'b0;
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#(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;
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#(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;
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#(PERIOD*DUTY_CYCLE);
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#(PERIOD*DUTY_CYCLE);
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end
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end
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end
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end
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testbench UUT (
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testbench UUT (
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.addr(addr),
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.addr(addr),
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.data(data),
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.data(data),
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.readmem(readmem),
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.readmem(readmem),
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.writemem(writemem),
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.writemem(writemem),
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.readio(readio),
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.readio(readio),
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.writeio(writeio),
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.writeio(writeio),
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.intr(intr),
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.intr(intr),
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.inta(inta),
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.inta(inta),
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.waitr(waitr),
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.waitr(waitr),
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.r(r),
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.r(r),
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.g(g),
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.g(g),
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.b(b),
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.b(b),
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.hsync_n(hsync_n),
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.hsync_n(hsync_n),
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.vsync_n(vsync_n),
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.vsync_n(vsync_n),
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.reset(reset),
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.reset(reset),
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.clock(clock));
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.clock(clock));
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integer TX_ERROR = 0;
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integer TX_ERROR = 0;
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initial begin // Open the results file...
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initial begin // Open the results file...
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#100200 // Final time: 100200 ns
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#100200 // Final time: 100200 ns
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if (TX_ERROR == 0) begin
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if (TX_ERROR == 0) begin
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$display("No errors or warnings.");
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$display("No errors or warnings.");
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end else begin
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end else begin
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$display("%d errors found in simulation.", TX_ERROR);
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$display("%d errors found in simulation.", TX_ERROR);
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end
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end
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$stop;
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$stop;
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end
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end
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initial begin
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initial begin
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// ------------- Current Time: 85ns
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// ------------- Current Time: 85ns
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#85;
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#85;
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reset = 1'b1;
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reset = 1'b1;
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data$inout$reg = 8'bZZZZZZZZ;
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data$inout$reg = 8'bZZZZZZZZ;
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// -------------------------------------
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// -------------------------------------
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// ------------- Current Time: 485ns
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// ------------- Current Time: 485ns
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#400;
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#400;
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reset = 1'b0;
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reset = 1'b0;
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// -------------------------------------
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// -------------------------------------
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end
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end
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task CHECK_addr;
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task CHECK_addr;
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input [15:0] NEXT_addr;
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input [15:0] NEXT_addr;
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#0 begin
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#0 begin
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if (NEXT_addr !== addr) begin
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if (NEXT_addr !== addr) begin
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$display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
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$display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_readmem;
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task CHECK_readmem;
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input NEXT_readmem;
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input NEXT_readmem;
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#0 begin
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#0 begin
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if (NEXT_readmem !== readmem) begin
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if (NEXT_readmem !== readmem) begin
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$display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
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$display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_writemem;
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task CHECK_writemem;
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input NEXT_writemem;
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input NEXT_writemem;
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#0 begin
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#0 begin
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if (NEXT_writemem !== writemem) begin
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if (NEXT_writemem !== writemem) begin
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$display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
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$display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_readio;
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task CHECK_readio;
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input NEXT_readio;
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input NEXT_readio;
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#0 begin
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#0 begin
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if (NEXT_readio !== readio) begin
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if (NEXT_readio !== readio) begin
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$display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);
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$display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_writeio;
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task CHECK_writeio;
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input NEXT_writeio;
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input NEXT_writeio;
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#0 begin
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#0 begin
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if (NEXT_writeio !== writeio) begin
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if (NEXT_writeio !== writeio) begin
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$display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);
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$display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_intr;
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task CHECK_intr;
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input NEXT_intr;
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input NEXT_intr;
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#0 begin
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#0 begin
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if (NEXT_intr !== intr) begin
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if (NEXT_intr !== intr) begin
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$display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);
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$display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_inta;
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task CHECK_inta;
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input NEXT_inta;
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input NEXT_inta;
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#0 begin
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#0 begin
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if (NEXT_inta !== inta) begin
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if (NEXT_inta !== inta) begin
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$display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);
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$display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_r;
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task CHECK_r;
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input [2:0] NEXT_r;
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input [2:0] NEXT_r;
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#0 begin
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#0 begin
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if (NEXT_r !== r) begin
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if (NEXT_r !== r) begin
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$display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);
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$display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_g;
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task CHECK_g;
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input [2:0] NEXT_g;
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input [2:0] NEXT_g;
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#0 begin
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#0 begin
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if (NEXT_g !== g) begin
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if (NEXT_g !== g) begin
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$display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);
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$display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_b;
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task CHECK_b;
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input [2:0] NEXT_b;
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input [2:0] NEXT_b;
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#0 begin
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#0 begin
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if (NEXT_b !== b) begin
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if (NEXT_b !== b) begin
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$display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);
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$display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_hsync_n;
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task CHECK_hsync_n;
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input NEXT_hsync_n;
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input NEXT_hsync_n;
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#0 begin
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#0 begin
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if (NEXT_hsync_n !== hsync_n) begin
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if (NEXT_hsync_n !== hsync_n) begin
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$display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);
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$display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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task CHECK_vsync_n;
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task CHECK_vsync_n;
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input NEXT_vsync_n;
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input NEXT_vsync_n;
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#0 begin
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#0 begin
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if (NEXT_vsync_n !== vsync_n) begin
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if (NEXT_vsync_n !== vsync_n) begin
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$display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);
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$display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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