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//////////////////////////////////////////////////////////////////
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////
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////
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//// CRCAHB CORE BLOCK
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////
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////
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////
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//// This file is part of the APB to I2C project
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////
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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//// Description
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////
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//// Implementation of APB IP core according to
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////
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//// crcahb IP core specification document.
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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//// Author(s): - Julio Cesar
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////
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/////////////////////////////////////////////////////////////////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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//// This source file may be used and distributed without
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////
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//// restriction provided that this copyright statement is not
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////
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////
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//// This source file is free software; you can redistribute it
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////
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//// and/or modify it under the terms of the GNU Lesser General
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////
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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////
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//// later version.
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////
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////
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////
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//// This source is distributed in the hope that it will be
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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////
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//// Public License along with this source; if not, download it
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////
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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///////////////////////////////////////////////////////////////////
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module crc_unit
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module crc_unit
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(
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(
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//OUTPUTS
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//OUTPUTS
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output [31:0] crc_poly_out,
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output [31:0] crc_poly_out,
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output [31:0] crc_out,
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output [31:0] crc_out,
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output [31:0] crc_init_out,
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output [31:0] crc_init_out,
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output [7:0] crc_idr_out,
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output [7:0] crc_idr_out,
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output buffer_full,
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output buffer_full,
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output read_wait,
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output read_wait,
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output reset_pending,
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output reset_pending,
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//INPUTS
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//INPUTS
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input [31:0] bus_wr,
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input [31:0] bus_wr,
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input [ 1:0] crc_poly_size,
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input [ 1:0] crc_poly_size,
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input [ 1:0] bus_size,
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input [ 1:0] bus_size,
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input [ 1:0] rev_in_type,
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input [ 1:0] rev_in_type,
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input rev_out_type,
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input rev_out_type,
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input crc_init_en,
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input crc_init_en,
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input crc_idr_en,
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input crc_idr_en,
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input crc_poly_en,
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input crc_poly_en,
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input buffer_write_en,
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input buffer_write_en,
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input reset_chain,
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input reset_chain,
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input clk,
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input clk,
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input rst_n
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input rst_n
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);
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);
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//Interconection signals
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//Interconection signals
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wire [ 1:0] size_in;
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wire [ 1:0] size_in;
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wire [ 1:0] byte_sel;
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wire [ 1:0] byte_sel;
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wire clear_crc_init;
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wire clear_crc_init;
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wire set_crc_init;
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wire set_crc_init;
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wire bypass_byte0;
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wire bypass_byte0;
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wire bypass_size;
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wire bypass_size;
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wire crc_out_en;
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wire crc_out_en;
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wire byte_en;
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wire byte_en;
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wire buffer_en;
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wire buffer_en;
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//The write in the buffer only occur if there is free space
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//The write in the buffer only occur if there is free space
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assign buffer_en = buffer_write_en && !buffer_full;
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assign buffer_en = buffer_write_en && !buffer_full;
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//Instance of the Datapath
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//Instance of the Datapath
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crc_datapath DATAPATH
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crc_datapath DATAPATH
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(
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(
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.crc_out ( crc_out ),
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.crc_out ( crc_out ),
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.size_out ( size_in ),
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.size_out ( size_in ),
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.crc_idr_out ( crc_idr_out ),
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.crc_idr_out ( crc_idr_out ),
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.crc_poly_out ( crc_poly_out ),
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.crc_poly_out ( crc_poly_out ),
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.crc_init_out ( crc_init_out ),
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.crc_init_out ( crc_init_out ),
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.bus_wr ( bus_wr ),
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.bus_wr ( bus_wr ),
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.rev_in_type ( rev_in_type ),
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.rev_in_type ( rev_in_type ),
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.rev_out_type ( rev_out_type ),
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.rev_out_type ( rev_out_type ),
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.buffer_en ( buffer_en ),
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.buffer_en ( buffer_en ),
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.byte_en ( byte_en ),
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.byte_en ( byte_en ),
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.crc_init_en ( crc_init_en ),
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.crc_init_en ( crc_init_en ),
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.crc_out_en ( crc_out_en ),
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.crc_out_en ( crc_out_en ),
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.crc_idr_en ( crc_idr_en ),
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.crc_idr_en ( crc_idr_en ),
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.crc_poly_en ( crc_poly_en ),
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.crc_poly_en ( crc_poly_en ),
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.buffer_rst ( clear_crc_init ),
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.buffer_rst ( clear_crc_init ),
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.bypass_byte0 ( bypass_byte0 ),
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.bypass_byte0 ( bypass_byte0 ),
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.bypass_size ( bypass_size ),
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.bypass_size ( bypass_size ),
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.byte_sel ( byte_sel ),
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.byte_sel ( byte_sel ),
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.size_in ( bus_size ),
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.size_in ( bus_size ),
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.clear_crc_init_sel ( clear_crc_init ),
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.clear_crc_init_sel ( clear_crc_init ),
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.set_crc_init_sel ( set_crc_init ),
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.set_crc_init_sel ( set_crc_init ),
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.crc_poly_size ( crc_poly_size ),
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.crc_poly_size ( crc_poly_size ),
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.clk ( clk ),
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.clk ( clk ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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//Instance of the Control unit
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//Instance of the Control unit
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crc_control_unit CONTROL_UNIT
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crc_control_unit CONTROL_UNIT
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(
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(
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.byte_en ( byte_en ),
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.byte_en ( byte_en ),
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.crc_out_en ( crc_out_en ),
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.crc_out_en ( crc_out_en ),
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.byte_sel ( byte_sel ),
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.byte_sel ( byte_sel ),
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.bypass_byte0 ( bypass_byte0 ),
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.bypass_byte0 ( bypass_byte0 ),
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.buffer_full ( buffer_full ),
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.buffer_full ( buffer_full ),
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.read_wait ( read_wait ),
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.read_wait ( read_wait ),
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.bypass_size ( bypass_size ),
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.bypass_size ( bypass_size ),
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.set_crc_init_sel ( set_crc_init ),
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.set_crc_init_sel ( set_crc_init ),
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.clear_crc_init_sel ( clear_crc_init ),
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.clear_crc_init_sel ( clear_crc_init ),
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.size_in ( size_in ),
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.size_in ( size_in ),
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.write ( buffer_write_en ),
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.write ( buffer_write_en ),
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.reset_chain ( reset_chain ),
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.reset_chain ( reset_chain ),
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.reset_pending ( reset_pending ),
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.reset_pending ( reset_pending ),
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.clk ( clk ),
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.clk ( clk ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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endmodule
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endmodule
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