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//////////////////////////////////////////////////////////////////
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////
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////
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//// CRCAHB CORE BLOCK
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////
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////
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////
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//// This file is part of the APB to I2C project
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////
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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//// Description
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////
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//// Implementation of APB IP core according to
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////
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//// crcahb IP core specification document.
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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//// Author(s): - Julio Cesar
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////
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/////////////////////////////////////////////////////////////////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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//// This source file may be used and distributed without
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////
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//// restriction provided that this copyright statement is not
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////
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////
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//// This source file is free software; you can redistribute it
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////
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//// and/or modify it under the terms of the GNU Lesser General
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////
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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////
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//// later version.
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////
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////
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////
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//// This source is distributed in the hope that it will be
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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////
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//// Public License along with this source; if not, download it
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////
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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///////////////////////////////////////////////////////////////////
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module host_interface
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module host_interface
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(
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(
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//OUTPUTS
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//OUTPUTS
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output [31:0] HRDATA,
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output [31:0] HRDATA,
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output HREADYOUT,
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output HREADYOUT,
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output HRESP,
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output HRESP,
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output [31:0] bus_wr,
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output [31:0] bus_wr,
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output [ 1:0] crc_poly_size,
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output [ 1:0] crc_poly_size,
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output [ 1:0] bus_size,
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output [ 1:0] bus_size,
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output [ 1:0] rev_in_type,
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output [ 1:0] rev_in_type,
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output rev_out_type,
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output rev_out_type,
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output crc_init_en,
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output crc_init_en,
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output crc_idr_en,
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output crc_idr_en,
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output crc_poly_en,
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output crc_poly_en,
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output buffer_write_en,
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output buffer_write_en,
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output reset_chain,
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output reset_chain,
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//INPUTS
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//INPUTS
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input [31:0] HWDATA,
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input [31:0] HWDATA,
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input [31:0] HADDR,
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input [31:0] HADDR,
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input [ 2:0] HSIZE,
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input [ 2:0] HSIZE,
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input [ 1:0] HTRANS,
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input [ 1:0] HTRANS,
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input HWRITE,
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input HWRITE,
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input HSElx,
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input HSElx,
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input HREADY,
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input HREADY,
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input HRESETn,
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input HRESETn,
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input HCLK,
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input HCLK,
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input [31:0] crc_poly_out,
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input [31:0] crc_poly_out,
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input [31:0] crc_out,
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input [31:0] crc_out,
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input [31:0] crc_init_out,
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input [31:0] crc_init_out,
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input [ 7:0] crc_idr_out,
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input [ 7:0] crc_idr_out,
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input buffer_full,
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input buffer_full,
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input reset_pending,
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input reset_pending,
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input read_wait
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input read_wait
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);
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);
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//Reset Values
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//Reset Values
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localparam RESET_CRC_CR = 6'h00;
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localparam RESET_CRC_CR = 6'h00;
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//CRC Register Map
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//CRC Register Map
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localparam CRC_DR = 3'h0;
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localparam CRC_DR = 3'h0;
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localparam CRC_IDR = 3'h1;
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localparam CRC_IDR = 3'h1;
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localparam CRC_CR = 3'h2;
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localparam CRC_CR = 3'h2;
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localparam CRC_INIT = 3'h4;
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localparam CRC_INIT = 3'h4;
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localparam CRC_POL = 3'h5;
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localparam CRC_POL = 3'h5;
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//Transfer Type Encoding
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//Transfer Type Encoding
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localparam IDLE = 2'b00;
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localparam IDLE = 2'b00;
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localparam BUSY = 2'b01;
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localparam BUSY = 2'b01;
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localparam NON_SEQ = 2'b10;
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localparam NON_SEQ = 2'b10;
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localparam SEQ = 2'b11;
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localparam SEQ = 2'b11;
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//HRESP Encoding
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//HRESP Encoding
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localparam OK = 1'b0;
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localparam OK = 1'b0;
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localparam ERROR = 1'b1;
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localparam ERROR = 1'b1;
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//Pipeline flops
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//Pipeline flops
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reg [2:0] haddr_pp;
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reg [2:0] haddr_pp;
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reg [2:0] hsize_pp;
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reg [2:0] hsize_pp;
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reg [1:0] htrans_pp;
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reg [1:0] htrans_pp;
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reg hwrite_pp;
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reg hwrite_pp;
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reg hselx_pp;
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reg hselx_pp;
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//Flops
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//Flops
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reg [4:0] crc_cr_ff;
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reg [4:0] crc_cr_ff;
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//Internal Signals
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//Internal Signals
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wire [31:0] crc_cr_rd;
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wire [31:0] crc_cr_rd;
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wire crc_dr_sel;
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wire crc_dr_sel;
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wire crc_init_sel;
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wire crc_init_sel;
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wire crc_idr_sel;
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wire crc_idr_sel;
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wire crc_poly_sel;
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wire crc_poly_sel;
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wire crc_cr_sel;
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wire crc_cr_sel;
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wire ahb_enable;
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wire ahb_enable;
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wire write_en;
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wire write_en;
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wire read_en;
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wire read_en;
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wire crc_cr_en;
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wire crc_cr_en;
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wire sample_bus;
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wire sample_bus;
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wire buffer_read_en;
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wire buffer_read_en;
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//Pipeline Registers for Address Phase of AHB Protocol
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//Pipeline Registers for Address Phase of AHB Protocol
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always @(posedge HCLK)
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always @(posedge HCLK)
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begin
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begin
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if(!HRESETn)
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if(!HRESETn)
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begin
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begin
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hselx_pp <= 1'b0;
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hselx_pp <= 1'b0;
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end
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end
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else
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else
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if(sample_bus)
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if(sample_bus)
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begin
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begin
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haddr_pp <= HADDR[4:2];
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haddr_pp <= HADDR[4:2];
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hsize_pp <= HSIZE;
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hsize_pp <= HSIZE;
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htrans_pp <= HTRANS;
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htrans_pp <= HTRANS;
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hwrite_pp <= HWRITE;
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hwrite_pp <= HWRITE;
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hselx_pp <= HSElx;
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hselx_pp <= HSElx;
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end
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end
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end
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end
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//Enable Signals
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//Enable Signals
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assign ahb_enable = (htrans_pp == NON_SEQ);
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assign ahb_enable = (htrans_pp == NON_SEQ);
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assign write_en = hselx_pp && hwrite_pp && ahb_enable;
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assign write_en = hselx_pp && hwrite_pp && ahb_enable;
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assign read_en = hselx_pp && !hwrite_pp && ahb_enable;
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assign read_en = hselx_pp && !hwrite_pp && ahb_enable;
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//Registers decoding
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//Registers decoding
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assign crc_dr_sel = (haddr_pp == CRC_DR );
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assign crc_dr_sel = (haddr_pp == CRC_DR );
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assign crc_init_sel = (haddr_pp == CRC_INIT);
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assign crc_init_sel = (haddr_pp == CRC_INIT);
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assign crc_idr_sel = (haddr_pp == CRC_IDR );
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assign crc_idr_sel = (haddr_pp == CRC_IDR );
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assign crc_poly_sel = (haddr_pp == CRC_POL );
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assign crc_poly_sel = (haddr_pp == CRC_POL );
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assign crc_cr_sel = (haddr_pp == CRC_CR );
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assign crc_cr_sel = (haddr_pp == CRC_CR );
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//Write Esnables Signals for Registers
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//Write Esnables Signals for Registers
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assign buffer_write_en = crc_dr_sel && write_en;
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assign buffer_write_en = crc_dr_sel && write_en;
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assign crc_init_en = crc_init_sel && write_en;
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assign crc_init_en = crc_init_sel && write_en;
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assign crc_idr_en = crc_idr_sel && write_en;
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assign crc_idr_en = crc_idr_sel && write_en;
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assign crc_poly_en = crc_poly_sel && write_en;
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assign crc_poly_en = crc_poly_sel && write_en;
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assign crc_cr_en = crc_cr_sel && write_en;
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assign crc_cr_en = crc_cr_sel && write_en;
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//Indicates reading operation request to crc_dr register
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//Indicates reading operation request to crc_dr register
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assign buffer_read_en = crc_dr_sel && read_en;
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assign buffer_read_en = crc_dr_sel && read_en;
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//Bus Size is the output of HSIZE pipeline register
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//Bus Size is the output of HSIZE pipeline register
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assign bus_size = hsize_pp;
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assign bus_size = hsize_pp;
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//The Write Bus is not pipelined
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//The Write Bus is not pipelined
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assign bus_wr = HWDATA;
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assign bus_wr = HWDATA;
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//HREADY Signal outputed to Master
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//HREADY Signal outputed to Master
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assign HREADYOUT = !((buffer_write_en && buffer_full ) ||
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assign HREADYOUT = !((buffer_write_en && buffer_full ) ||
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(buffer_read_en && read_wait ) ||
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(buffer_read_en && read_wait ) ||
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(crc_init_en && reset_pending ) );
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(crc_init_en && reset_pending ) );
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//Signal to control sampling of bus
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//Signal to control sampling of bus
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assign sample_bus = HREADYOUT && HREADY;
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assign sample_bus = HREADYOUT && HREADY;
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//HRESP Signal outputed to Master
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//HRESP Signal outputed to Master
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//This implementation never signalize bus error to master
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//This implementation never signalize bus error to master
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assign HRESP = OK;
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assign HRESP = OK;
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//CRC_CR Data Read
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//CRC_CR Data Read
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assign crc_cr_rd = {24'h0, crc_cr_ff[4:0], 3'h0};
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assign crc_cr_rd = {24'h0, crc_cr_ff[4:0], 3'h0};
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//Mux to HRDATA
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//Mux to HRDATA
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assign HRDATA = ({32{crc_dr_sel }} & crc_out ) |
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assign HRDATA = ({32{crc_dr_sel }} & crc_out ) |
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({32{crc_init_sel}} & crc_init_out ) |
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({32{crc_init_sel}} & crc_init_out ) |
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({32{crc_idr_sel }} & {24'h0, crc_idr_out}) |
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({32{crc_idr_sel }} & {24'h0, crc_idr_out}) |
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({32{crc_poly_sel}} & crc_poly_out ) |
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({32{crc_poly_sel}} & crc_poly_out ) |
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({32{crc_cr_sel }} & crc_cr_rd ) ;
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({32{crc_cr_sel }} & crc_cr_rd ) ;
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//Control Register
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//Control Register
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always @(posedge HCLK)
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always @(posedge HCLK)
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begin
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begin
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if(!HRESETn)
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if(!HRESETn)
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crc_cr_ff <= RESET_CRC_CR;
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crc_cr_ff <= RESET_CRC_CR;
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else
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else
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if(crc_cr_en)
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if(crc_cr_en)
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crc_cr_ff <= {HWDATA[7], HWDATA[6:5], HWDATA[4:3]};
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crc_cr_ff <= {HWDATA[7], HWDATA[6:5], HWDATA[4:3]};
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end
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end
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//Configuration Signals
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//Configuration Signals
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assign reset_chain = (crc_cr_en && HWDATA[0]);
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assign reset_chain = (crc_cr_en && HWDATA[0]);
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assign crc_poly_size = crc_cr_ff[1:0];
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assign crc_poly_size = crc_cr_ff[1:0];
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assign rev_in_type = crc_cr_ff[3:2];
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assign rev_in_type = crc_cr_ff[3:2];
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assign rev_out_type = crc_cr_ff[4];
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assign rev_out_type = crc_cr_ff[4];
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endmodule
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endmodule
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