--
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--
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-- This file is part of the Crypto-PAn core (www.opencores.org).
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-- This file is part of the Crypto-PAn core (www.opencores.org).
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--
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--
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-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
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-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
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-- Authors: Anthony Blake (tonyb33@opencores.org)
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-- Authors: Anthony Blake (tonyb33@opencores.org)
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--
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--
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- This code has been developed by the University of Waikato WAND
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-- This code has been developed by the University of Waikato WAND
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-- research group. For further information please see http://www.wand.net.nz/
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-- research group. For further information please see http://www.wand.net.nz/
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--
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--
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-- This source file is free software; you can redistribute it and/or modify
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-- This source file is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This source is distributed in the hope that it will be useful,
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-- This source is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with libtrace; if not, write to the Free Software
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-- along with libtrace; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity cryptopan_unit_tb is
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entity cryptopan_unit_tb is
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end cryptopan_unit_tb;
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end cryptopan_unit_tb;
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architecture tb of cryptopan_unit_tb is
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architecture tb of cryptopan_unit_tb is
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component cryptopan_unit
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component cryptopan_unit
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ready : out std_logic;
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ready : out std_logic;
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key : in std_logic_vector(255 downto 0);
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key : in std_logic_vector(255 downto 0);
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key_wren : in std_logic;
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key_wren : in std_logic;
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ip_in : in std_logic_vector(31 downto 0);
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ip_in : in std_logic_vector(31 downto 0);
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ip_wren : in std_logic;
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ip_wren : in std_logic;
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ip_out : out std_logic_vector(31 downto 0);
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ip_out : out std_logic_vector(31 downto 0);
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ip_dv : out std_logic);
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ip_dv : out std_logic);
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end component;
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end component;
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signal clk : std_logic;
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signal clk : std_logic;
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signal reset : std_logic;
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signal reset : std_logic;
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signal key : std_logic_vector(255 downto 0);
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signal key : std_logic_vector(255 downto 0);
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signal key_wren : std_logic;
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signal key_wren : std_logic;
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signal ready : std_logic;
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signal ready : std_logic;
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signal ip_in, ip_out : std_logic_vector(31 downto 0);
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signal ip_in, ip_out : std_logic_vector(31 downto 0);
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signal ip_wren, ip_dv : std_logic;
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signal ip_wren, ip_dv : std_logic;
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type char_file is file of character;
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type char_file is file of character;
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file bin_file_raw : char_file is in "sim/trace_bin_raw";
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file bin_file_raw : char_file is in "sim/trace_bin_raw";
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file bin_file_anon : char_file is in "sim/trace_bin_anon";
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file bin_file_anon : char_file is in "sim/trace_bin_anon";
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signal ip_in_int : std_logic_vector(31 downto 0);
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signal ip_in_int : std_logic_vector(31 downto 0);
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signal ip_out_int : std_logic_vector(31 downto 0);
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signal ip_out_int : std_logic_vector(31 downto 0);
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begin
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begin
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CLKGEN : process
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CLKGEN : process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for 5 ns;
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wait for 5 ns;
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clk <= '0';
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clk <= '0';
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wait for 5 ns;
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wait for 5 ns;
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end process CLKGEN;
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end process CLKGEN;
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DUT : cryptopan_unit
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DUT : cryptopan_unit
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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ready => ready,
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ready => ready,
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key => key,
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key => key,
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key_wren => key_wren,
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key_wren => key_wren,
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ip_in => ip_in,
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ip_in => ip_in,
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ip_wren => ip_wren,
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ip_wren => ip_wren,
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ip_out => ip_out,
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ip_out => ip_out,
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ip_dv => ip_dv);
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ip_dv => ip_dv);
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GEN_IPS : process
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GEN_IPS : process
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variable my_char : character;
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variable my_char : character;
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begin -- process GEN_IPS
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begin -- process GEN_IPS
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-- file_open(bin_file_raw, "sim/trace_bin_raw", read_mode);
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-- file_open(bin_file_raw, "sim/trace_bin_raw", read_mode);
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ip_in_int <= (others => '0');
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ip_in_int <= (others => '0');
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ip_wren <= '0';
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ip_wren <= '0';
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wait until ready = '1';
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wait until ready = '1';
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wait for 50 ns;
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wait for 50 ns;
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while not endfile(bin_file_raw) loop
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while not endfile(bin_file_raw) loop
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read(bin_file_raw, my_char);
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read(bin_file_raw, my_char);
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ip_in_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_in_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_raw, my_char);
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read(bin_file_raw, my_char);
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ip_in_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_in_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_raw, my_char);
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read(bin_file_raw, my_char);
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ip_in_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_in_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_raw, my_char);
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read(bin_file_raw, my_char);
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ip_in_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_in_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
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wait for 10 ns;
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wait for 10 ns;
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ip_wren <= '1';
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ip_wren <= '1';
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wait for 10 ns;
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wait for 10 ns;
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ip_wren <= '0';
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ip_wren <= '0';
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wait until ready = '1';
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wait until ready = '1';
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end loop;
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end loop;
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report "TEST COMPLETED" severity note;
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report "TEST COMPLETED" severity note;
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end process GEN_IPS;
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end process GEN_IPS;
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IP_OUT_INT_LOGIC : process
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IP_OUT_INT_LOGIC : process
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variable my_char : character;
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variable my_char : character;
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begin -- process IP_OUT_INT_LOGIC
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begin -- process IP_OUT_INT_LOGIC
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--ip_out_int <= (others => '0');
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--ip_out_int <= (others => '0');
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wait until ip_dv = '1';
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wait until ip_dv = '1';
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read(bin_file_anon, my_char);
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read(bin_file_anon, my_char);
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ip_out_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_out_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_anon, my_char);
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read(bin_file_anon, my_char);
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ip_out_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_out_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_anon, my_char);
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read(bin_file_anon, my_char);
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ip_out_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_out_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
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read(bin_file_anon, my_char);
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read(bin_file_anon, my_char);
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ip_out_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
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ip_out_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
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end process IP_OUT_INT_LOGIC;
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end process IP_OUT_INT_LOGIC;
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DV_LOGIC : process(clk)
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DV_LOGIC : process(clk)
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variable my_char : character;
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variable my_char : character;
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begin -- process DV_LOGIC
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begin -- process DV_LOGIC
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if ip_dv = '1' then
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if ip_dv = '1' then
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assert ip_out_int = ip_out report "TEST FAILED" severity error;
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assert ip_out_int = ip_out report "TEST FAILED" severity error;
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end if;
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end if;
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end if;
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end if;
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end process DV_LOGIC;
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end process DV_LOGIC;
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ip_in <= ip_in_int;
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ip_in <= ip_in_int;
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TESTBENCH : process
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TESTBENCH : process
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begin
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begin
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reset <= '1';
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reset <= '1';
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-- ip_in <= (others => '0');
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-- ip_in <= (others => '0');
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key <= (others => '0');
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key <= (others => '0');
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-- ip_wren <= '0';
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-- ip_wren <= '0';
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key_wren <= '0';
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key_wren <= '0';
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wait for 50 ns;
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wait for 50 ns;
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reset <= '0';
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reset <= '0';
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wait for 20 ns;
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wait for 20 ns;
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key <= X"d8988f837979652762574c2d2a8422021522178d33a4cf80130a5b1649907d10";
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key <= X"d8988f837979652762574c2d2a8422021522178d33a4cf80130a5b1649907d10";
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key_wren <= '1';
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key_wren <= '1';
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wait for 10 ns;
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wait for 10 ns;
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key_wren <= '0';
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key_wren <= '0';
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-- wait until ready='1';
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-- wait until ready='1';
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-- wait for 40 ns;
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-- wait for 40 ns;
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-- ip_in <= X"18050050";
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-- ip_in <= X"18050050";
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-- ip_wren <= '1';
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-- ip_wren <= '1';
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-- wait for 10 ns;
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-- wait for 10 ns;
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-- ip_wren <= '0';
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-- ip_wren <= '0';
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-- wait until ready='1';
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-- wait until ready='1';
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wait;
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wait;
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end process TESTBENCH;
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end process TESTBENCH;
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end tb;
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end tb;
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