`include "../bench/timescale.v"
|
`include "../bench/timescale.v"
|
|
|
|
|
// this file implement the stream cypher module
|
// this file implement the stream cypher module
|
|
|
module stream_cypher(clk,rst,en,init,ck,sb,cb);
|
module stream_cypher(clk,rst,en,init,ck,sb,cb);
|
input clk;
|
input clk;
|
input rst; // hi enable
|
input rst; // hi enable
|
input en; // hi enable
|
input en; // hi enable
|
input init; // hi enable
|
input init; // hi enable
|
input [8 *8-1:0] ck;
|
input [8 *8-1:0] ck;
|
input [8 *8-1:0] sb;
|
input [8 *8-1:0] sb;
|
output [8 *8-1:0] cb;
|
output [8 *8-1:0] cb;
|
|
|
|
|
|
|
// intermediate variable
|
// intermediate variable
|
reg [10*4-1 : 0]A;
|
reg [10*4-1 : 0]A;
|
reg [10*4-1 : 0]B;
|
reg [10*4-1 : 0]B;
|
reg [4-1 : 0]X;
|
reg [4-1 : 0]X;
|
reg [4-1 : 0]Y;
|
reg [4-1 : 0]Y;
|
reg [4-1 : 0]Z;
|
reg [4-1 : 0]Z;
|
reg [4-1 : 0]D;
|
reg [4-1 : 0]D;
|
reg [4-1 : 0]E;
|
reg [4-1 : 0]E;
|
reg [4-1 : 0]F;
|
reg [4-1 : 0]F;
|
reg p;
|
reg p;
|
reg q;
|
reg q;
|
reg r;
|
reg r;
|
reg [8 *8-1 : 0]cb;
|
|
|
|
wire [10*4-1 : 0]Ao;
|
wire [10*4-1 : 0]Ao;
|
wire [10*4-1 : 0]Ainit;
|
wire [10*4-1 : 0]Ainit;
|
wire [10*4-1 : 0]Bo;
|
wire [10*4-1 : 0]Bo;
|
wire [10*4-1 : 0]Binit;
|
wire [10*4-1 : 0]Binit;
|
wire [4-1 : 0]Xo;
|
wire [4-1 : 0]Xo;
|
wire [4-1 : 0]Yo;
|
wire [4-1 : 0]Yo;
|
wire [4-1 : 0]Zo;
|
wire [4-1 : 0]Zo;
|
wire [4-1 : 0]Do;
|
wire [4-1 : 0]Do;
|
wire [4-1 : 0]Eo;
|
wire [4-1 : 0]Eo;
|
wire [4-1 : 0]Fo;
|
wire [4-1 : 0]Fo;
|
wire po;
|
wire po;
|
wire qo;
|
wire qo;
|
wire ro;
|
wire ro;
|
wire [8 *8-1 : 0]cbo;
|
wire [8 *8-1 : 0]cbo;
|
|
|
assign Ainit = {
|
assign Ainit = {
|
4'b0, 4'b0,
|
4'b0, 4'b0,
|
ck[7*4-1:6*4],ck[8*4-1:7*4],
|
ck[7*4-1:6*4],ck[8*4-1:7*4],
|
ck[5*4-1:4*4],ck[6*4-1:5*4],
|
ck[5*4-1:4*4],ck[6*4-1:5*4],
|
ck[3*4-1:2*4],ck[4*4-1:3*4],
|
ck[3*4-1:2*4],ck[4*4-1:3*4],
|
ck[1*4-1:0*4],ck[2*4-1:1*4]
|
ck[1*4-1:0*4],ck[2*4-1:1*4]
|
};
|
};
|
|
|
assign Binit = {
|
assign Binit = {
|
4'b0, 4'b0,
|
4'b0, 4'b0,
|
ck[15*4-1:14*4],ck[16*4-1:15*4],
|
ck[15*4-1:14*4],ck[16*4-1:15*4],
|
ck[13*4-1:12*4],ck[14*4-1:13*4],
|
ck[13*4-1:12*4],ck[14*4-1:13*4],
|
ck[11*4-1:10*4],ck[12*4-1:11*4],
|
ck[11*4-1:10*4],ck[12*4-1:11*4],
|
ck[ 9*4-1: 8*4],ck[10*4-1: 9*4]
|
ck[ 9*4-1: 8*4],ck[10*4-1: 9*4]
|
};
|
};
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if(rst)
|
if(rst)
|
begin
|
begin
|
A<= 40'h0000000000;
|
A<= 40'h0000000000;
|
B<= 40'h0000000000;
|
B<= 40'h0000000000;
|
X<= 4'h0;
|
X<= 4'h0;
|
Y<= 4'h0;
|
Y<= 4'h0;
|
Z<= 4'h0;
|
Z<= 4'h0;
|
D<= 4'h0;
|
D<= 4'h0;
|
E<= 4'h0;
|
E<= 4'h0;
|
F<= 4'h0;
|
F<= 4'h0;
|
p<= 1'h0;
|
p<= 1'h0;
|
q<= 1'h0;
|
q<= 1'h0;
|
r<= 1'h0;
|
r<= 1'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(en)
|
if(en)
|
begin
|
begin
|
cb <= cbo;
|
|
A<= Ao;
|
A<= Ao;
|
B<= Bo;
|
B<= Bo;
|
X<= Xo;
|
X<= Xo;
|
Y<= Yo;
|
Y<= Yo;
|
Z<= Zo;
|
Z<= Zo;
|
D<= Do;
|
D<= Do;
|
E<= Eo;
|
E<= Eo;
|
F<= Fo;
|
F<= Fo;
|
p<= po;
|
p<= po;
|
q<= qo;
|
q<= qo;
|
r<= ro;
|
r<= ro;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
stream_8bytes stream_8bytes(
|
stream_8bytes stream_8bytes(
|
.init(init)
|
.init(init)
|
,.sb(sb)
|
,.sb(sb)
|
,.Ai((init)?Ainit:A)
|
,.Ai((init)?Ainit:A)
|
,.Bi((init)?Binit:B)
|
,.Bi((init)?Binit:B)
|
,.Di((init)?4'b0 :D)
|
,.Di((init)?4'b0 :D)
|
,.Ei((init)?4'b0 :E)
|
,.Ei((init)?4'b0 :E)
|
,.Fi((init)?4'b0 :F)
|
,.Fi((init)?4'b0 :F)
|
,.Xi((init)?4'b0 :X)
|
,.Xi((init)?4'b0 :X)
|
,.Yi((init)?4'b0 :Y)
|
,.Yi((init)?4'b0 :Y)
|
,.Zi((init)?4'b0 :Z)
|
,.Zi((init)?4'b0 :Z)
|
,.pi((init)?1'b0 :p)
|
,.pi((init)?1'b0 :p)
|
,.qi((init)?1'b0 :q)
|
,.qi((init)?1'b0 :q)
|
,.ri((init)?1'b0 :r)
|
,.ri((init)?1'b0 :r)
|
|
|
,.Ao(Ao)
|
,.Ao(Ao)
|
,.Bo(Bo)
|
,.Bo(Bo)
|
,.Do(Do)
|
,.Do(Do)
|
,.Eo(Eo)
|
,.Eo(Eo)
|
,.Fo(Fo)
|
,.Fo(Fo)
|
,.Xo(Xo)
|
,.Xo(Xo)
|
,.Yo(Yo)
|
,.Yo(Yo)
|
,.Zo(Zo)
|
,.Zo(Zo)
|
,.po(po)
|
,.po(po)
|
,.qo(qo)
|
,.qo(qo)
|
,.ro(ro)
|
,.ro(ro)
|
,.cb(cbo)
|
,.cb(cbo)
|
);
|
);
|
|
|
|
assign cb=cbo;
|
|
|
endmodule
|
endmodule
|
|
|