URL
https://opencores.org/ocsvn/dallas_one-wire/dallas_one-wire/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
| Rev 2 |
Rev 3 |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
entity clk_divider is
|
entity clk_divider is
|
port
|
port
|
(
|
(
|
clk : IN std_logic;
|
clk : IN std_logic;
|
oneus_plus : INOUT std_logic
|
oneus_plus : INOUT std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
|
|
architecture structural of clk_divider is
|
architecture structural of clk_divider is
|
|
|
signal counter : integer range 0 to 16;
|
signal counter : integer range 0 to 16;
|
|
|
begin
|
begin
|
|
|
process ( clk )
|
process ( clk )
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
counter <= counter + 1;
|
counter <= counter + 1;
|
if (counter mod 16) = 0 then
|
if (counter mod 16) = 0 then
|
oneus_plus <= not oneus_plus;
|
oneus_plus <= not oneus_plus;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
PACKAGE TIMER_PKG IS
|
PACKAGE TIMER_PKG IS
|
COMPONENT clk_divider
|
COMPONENT clk_divider
|
END COMPONENT;
|
END COMPONENT;
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.