/*
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/*
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* Copyright (c) 2018, Marcelo Samsoniuk
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* Copyright (c) 2018, Marcelo Samsoniuk
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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*
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* list of conditions and the following disclaimer.
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*
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* and/or other materials provided with the distribution.
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*
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*
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* * Neither the name of the copyright holder nor the names of its
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* * Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* this software without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// implemented opcodes:
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// implemented opcodes:
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`define LUI 7'b01101_11 // lui rd,imm[31:12]
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`define LUI 7'b01101_11 // lui rd,imm[31:12]
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`define AUIPC 7'b00101_11 // auipc rd,imm[31:12]
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`define AUIPC 7'b00101_11 // auipc rd,imm[31:12]
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`define JAL 7'b11011_11 // jal rd,imm[xxxxx]
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`define JAL 7'b11011_11 // jal rd,imm[xxxxx]
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`define JALR 7'b11001_11 // jalr rd,rs1,imm[11:0]
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`define JALR 7'b11001_11 // jalr rd,rs1,imm[11:0]
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`define BCC 7'b11000_11 // bcc rs1,rs2,imm[12:1]
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`define BCC 7'b11000_11 // bcc rs1,rs2,imm[12:1]
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`define LCC 7'b00000_11 // lxx rd,rs1,imm[11:0]
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`define LCC 7'b00000_11 // lxx rd,rs1,imm[11:0]
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`define SCC 7'b01000_11 // sxx rs1,rs2,imm[11:0]
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`define SCC 7'b01000_11 // sxx rs1,rs2,imm[11:0]
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`define MCC 7'b00100_11 // xxxi rd,rs1,imm[11:0]
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`define MCC 7'b00100_11 // xxxi rd,rs1,imm[11:0]
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`define RCC 7'b01100_11 // xxx rd,rs1,rs2
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`define RCC 7'b01100_11 // xxx rd,rs1,rs2
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`define MAC 7'b11111_11 // mac rd,rs1,rs2
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`define MAC 7'b11111_11 // mac rd,rs1,rs2
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// not implemented opcodes:
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// not implemented opcodes:
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`define FCC 7'b00011_11 // fencex
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`define FCC 7'b00011_11 // fencex
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`define CCC 7'b11100_11 // exx, csrxx
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`define CCC 7'b11100_11 // exx, csrxx
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// configuration file
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// configuration file
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`include "../rtl/config.vh"
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`include "../rtl/config.vh"
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module darkriscv
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module darkriscv
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//#(
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//#(
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// parameter [31:0] RESET_PC = 0,
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// parameter [31:0] RESET_PC = 0,
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// parameter [31:0] RESET_SP = 4096
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// parameter [31:0] RESET_SP = 4096
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//)
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//)
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(
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(
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input CLK, // clock
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input CLK, // clock
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input RES, // reset
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input RES, // reset
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input HLT, // halt
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input HLT, // halt
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//`ifdef __THREADING__
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//`ifdef __THREADING__
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// input IREQ, // irq req
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// input IREQ, // irq req
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//`endif
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//`endif
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input [31:0] IDATA, // instruction data bus
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input [31:0] IDATA, // instruction data bus
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output [31:0] IADDR, // instruction addr bus
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output [31:0] IADDR, // instruction addr bus
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input [31:0] DATAI, // data bus (input)
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input [31:0] DATAI, // data bus (input)
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output [31:0] DATAO, // data bus (output)
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output [31:0] DATAO, // data bus (output)
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output [31:0] DADDR, // addr bus
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output [31:0] DADDR, // addr bus
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`ifdef __FLEXBUZZ__
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`ifdef __FLEXBUZZ__
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output [ 2:0] DLEN, // data length
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output [ 2:0] DLEN, // data length
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output RW, // data read/write
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output RW, // data read/write
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`else
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`else
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output [ 3:0] BE, // byte enable
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output [ 3:0] BE, // byte enable
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output WR, // write enable
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output WR, // write enable
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output RD, // read enable
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output RD, // read enable
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`endif
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`endif
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`ifdef SIMULATION
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`ifdef SIMULATION
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input FINISH_REQ,
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input FINISH_REQ,
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`endif
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`endif
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output [3:0] DEBUG // old-school osciloscope based debug! :)
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output [3:0] DEBUG // old-school osciloscope based debug! :)
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);
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);
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// dummy 32-bit words w/ all-0s and all-1s:
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// dummy 32-bit words w/ all-0s and all-1s:
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wire [31:0] ALL0 = 0;
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wire [31:0] ALL0 = 0;
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wire [31:0] ALL1 = -1;
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wire [31:0] ALL1 = -1;
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`ifdef __THREADING__
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`ifdef __THREADING__
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reg XMODE = 0; // thread ptr
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reg [$clog2(`NTHREADS)-1:0] XMODE = 0; // thread ptr
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`endif
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`endif
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// pre-decode: IDATA is break apart as described in the RV32I specification
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// pre-decode: IDATA is break apart as described in the RV32I specification
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reg [31:0] XIDATA;
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reg [31:0] XIDATA;
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reg XLUI, XAUIPC, XJAL, XJALR, XBCC, XLCC, XSCC, XMCC, XRCC, XMAC, XRES=1; //, XFCC, XCCC;
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reg XLUI, XAUIPC, XJAL, XJALR, XBCC, XLCC, XSCC, XMCC, XRCC, XMAC, XRES=1; //, XFCC, XCCC;
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reg [31:0] XSIMM;
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reg [31:0] XSIMM;
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reg [31:0] XUIMM;
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reg [31:0] XUIMM;
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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XIDATA <= XRES ? 0 : HLT ? XIDATA : IDATA;
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XIDATA <= XRES ? 0 : HLT ? XIDATA : IDATA;
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XLUI <= XRES ? 0 : HLT ? XLUI : IDATA[6:0]==`LUI;
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XLUI <= XRES ? 0 : HLT ? XLUI : IDATA[6:0]==`LUI;
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XAUIPC <= XRES ? 0 : HLT ? XAUIPC : IDATA[6:0]==`AUIPC;
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XAUIPC <= XRES ? 0 : HLT ? XAUIPC : IDATA[6:0]==`AUIPC;
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XJAL <= XRES ? 0 : HLT ? XJAL : IDATA[6:0]==`JAL;
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XJAL <= XRES ? 0 : HLT ? XJAL : IDATA[6:0]==`JAL;
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XJALR <= XRES ? 0 : HLT ? XJALR : IDATA[6:0]==`JALR;
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XJALR <= XRES ? 0 : HLT ? XJALR : IDATA[6:0]==`JALR;
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XBCC <= XRES ? 0 : HLT ? XBCC : IDATA[6:0]==`BCC;
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XBCC <= XRES ? 0 : HLT ? XBCC : IDATA[6:0]==`BCC;
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XLCC <= XRES ? 0 : HLT ? XLCC : IDATA[6:0]==`LCC;
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XLCC <= XRES ? 0 : HLT ? XLCC : IDATA[6:0]==`LCC;
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XSCC <= XRES ? 0 : HLT ? XSCC : IDATA[6:0]==`SCC;
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XSCC <= XRES ? 0 : HLT ? XSCC : IDATA[6:0]==`SCC;
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XMCC <= XRES ? 0 : HLT ? XMCC : IDATA[6:0]==`MCC;
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XMCC <= XRES ? 0 : HLT ? XMCC : IDATA[6:0]==`MCC;
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XRCC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`RCC;
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XRCC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`RCC;
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XMAC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`MAC;
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XMAC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`MAC;
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//XFCC <= XRES ? 0 : HLT ? XFCC : IDATA[6:0]==`FCC;
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//XFCC <= XRES ? 0 : HLT ? XFCC : IDATA[6:0]==`FCC;
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//XCCC <= XRES ? 0 : HLT ? XCCC : IDATA[6:0]==`CCC;
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//XCCC <= XRES ? 0 : HLT ? XCCC : IDATA[6:0]==`CCC;
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// signal extended immediate, according to the instruction type:
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// signal extended immediate, according to the instruction type:
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XSIMM <= XRES ? 0 : HLT ? XSIMM :
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XSIMM <= XRES ? 0 : HLT ? XSIMM :
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IDATA[6:0]==`SCC ? { IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
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IDATA[6:0]==`SCC ? { IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
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IDATA[6:0]==`BCC ? { IDATA[31] ? ALL1[31:13]:ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
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IDATA[6:0]==`BCC ? { IDATA[31] ? ALL1[31:13]:ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
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IDATA[6:0]==`JAL ? { IDATA[31] ? ALL1[31:21]:ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
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IDATA[6:0]==`JAL ? { IDATA[31] ? ALL1[31:21]:ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
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IDATA[6:0]==`LUI||
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IDATA[6:0]==`LUI||
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IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
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IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
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{ IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:20] }; // i-type
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{ IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:20] }; // i-type
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// non-signal extended immediate, according to the instruction type:
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// non-signal extended immediate, according to the instruction type:
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XUIMM <= XRES ? 0: HLT ? XUIMM :
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XUIMM <= XRES ? 0: HLT ? XUIMM :
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IDATA[6:0]==`SCC ? { ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
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IDATA[6:0]==`SCC ? { ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
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IDATA[6:0]==`BCC ? { ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
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IDATA[6:0]==`BCC ? { ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
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IDATA[6:0]==`JAL ? { ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
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IDATA[6:0]==`JAL ? { ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
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IDATA[6:0]==`LUI||
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IDATA[6:0]==`LUI||
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IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
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IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
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{ ALL0[31:12], IDATA[31:20] }; // i-type
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{ ALL0[31:12], IDATA[31:20] }; // i-type
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end
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end
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// decode: after XIDATA
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// decode: after XIDATA
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`ifdef __3STAGE__
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`ifdef __3STAGE__
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reg [1:0] FLUSH = -1; // flush instruction pipeline
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reg [1:0] FLUSH = -1; // flush instruction pipeline
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`else
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`else
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reg FLUSH = -1; // flush instruction pipeline
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reg FLUSH = -1; // flush instruction pipeline
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`endif
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`endif
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`ifdef __THREADING__
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`ifdef __THREADING__
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`ifdef __RV32E__
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`ifdef __RV32E__
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reg [4:0] RESMODE = -1;
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reg [$clog2(`NTHREADS)+3:0] RESMODE = -1;
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wire [4:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[10: 7] }; // set SP_RESET when RES==1
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wire [4:0] S1PTR = { XMODE, XIDATA[18:15] };
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wire [4:0] S2PTR = { XMODE, XIDATA[23:20] };
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`else
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reg [5:0] RESMODE = -1;
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wire [5:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[11: 7] }; // set SP_RESET when RES==1
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wire [5:0] S1PTR = { XMODE, XIDATA[19:15] };
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wire [5:0] S2PTR = { XMODE, XIDATA[24:20] };
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`endif
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wire [6:0] OPCODE = FLUSH ? 0 : XIDATA[6:0];
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wire [2:0] FCT3 = XIDATA[14:12];
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wire [6:0] FCT7 = XIDATA[31:25];
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wire [$clog2(`NTHREADS)+3:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[10: 7] }; // set SP_RESET when RES==1
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wire [$clog2(`NTHREADS)+3:0] S1PTR = { XMODE, XIDATA[18:15] };
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wire [$clog2(`NTHREADS)+3:0] S2PTR = { XMODE, XIDATA[23:20] };
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`else
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`else
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reg [$clog2(`NTHREADS)+4:0] RESMODE = -1;
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wire [$clog2(`NTHREADS)+4:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[11: 7] }; // set SP_RESET when RES==1
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wire [$clog2(`NTHREADS)+4:0] S1PTR = { XMODE, XIDATA[19:15] };
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wire [$clog2(`NTHREADS)+4:0] S2PTR = { XMODE, XIDATA[24:20] };
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`endif
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`else
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`ifdef __RV32E__
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`ifdef __RV32E__
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reg [3:0] RESMODE = -1;
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reg [3:0] RESMODE = -1;
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wire [3:0] DPTR = XRES ? RESMODE : XIDATA[10: 7]; // set SP_RESET when RES==1
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wire [3:0] DPTR = XRES ? RESMODE : XIDATA[10: 7]; // set SP_RESET when RES==1
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wire [3:0] S1PTR = XIDATA[18:15];
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wire [3:0] S1PTR = XIDATA[18:15];
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wire [3:0] S2PTR = XIDATA[23:20];
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wire [3:0] S2PTR = XIDATA[23:20];
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`else
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`else
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reg [4:0] RESMODE = -1;
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reg [4:0] RESMODE = -1;
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wire [4:0] DPTR = XRES ? RESMODE : XIDATA[11: 7]; // set SP_RESET when RES==1
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wire [4:0] DPTR = XRES ? RESMODE : XIDATA[11: 7]; // set SP_RESET when RES==1
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wire [4:0] S1PTR = XIDATA[19:15];
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wire [4:0] S1PTR = XIDATA[19:15];
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wire [4:0] S2PTR = XIDATA[24:20];
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wire [4:0] S2PTR = XIDATA[24:20];
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`endif
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`endif
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`endif
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wire [6:0] OPCODE = FLUSH ? 0 : XIDATA[6:0];
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wire [6:0] OPCODE = FLUSH ? 0 : XIDATA[6:0];
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wire [2:0] FCT3 = XIDATA[14:12];
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wire [2:0] FCT3 = XIDATA[14:12];
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wire [6:0] FCT7 = XIDATA[31:25];
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wire [6:0] FCT7 = XIDATA[31:25];
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`endif
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wire [31:0] SIMM = XSIMM;
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wire [31:0] SIMM = XSIMM;
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wire [31:0] UIMM = XUIMM;
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wire [31:0] UIMM = XUIMM;
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// main opcode decoder:
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// main opcode decoder:
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wire LUI = FLUSH ? 0 : XLUI; // OPCODE==7'b0110111;
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wire LUI = FLUSH ? 0 : XLUI; // OPCODE==7'b0110111;
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wire AUIPC = FLUSH ? 0 : XAUIPC; // OPCODE==7'b0010111;
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wire AUIPC = FLUSH ? 0 : XAUIPC; // OPCODE==7'b0010111;
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wire JAL = FLUSH ? 0 : XJAL; // OPCODE==7'b1101111;
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wire JAL = FLUSH ? 0 : XJAL; // OPCODE==7'b1101111;
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wire JALR = FLUSH ? 0 : XJALR; // OPCODE==7'b1100111;
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wire JALR = FLUSH ? 0 : XJALR; // OPCODE==7'b1100111;
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wire BCC = FLUSH ? 0 : XBCC; // OPCODE==7'b1100011; //FCT3
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wire BCC = FLUSH ? 0 : XBCC; // OPCODE==7'b1100011; //FCT3
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wire LCC = FLUSH ? 0 : XLCC; // OPCODE==7'b0000011; //FCT3
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wire LCC = FLUSH ? 0 : XLCC; // OPCODE==7'b0000011; //FCT3
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wire SCC = FLUSH ? 0 : XSCC; // OPCODE==7'b0100011; //FCT3
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wire SCC = FLUSH ? 0 : XSCC; // OPCODE==7'b0100011; //FCT3
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wire MCC = FLUSH ? 0 : XMCC; // OPCODE==7'b0010011; //FCT3
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wire MCC = FLUSH ? 0 : XMCC; // OPCODE==7'b0010011; //FCT3
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wire RCC = FLUSH ? 0 : XRCC; // OPCODE==7'b0110011; //FCT3
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wire RCC = FLUSH ? 0 : XRCC; // OPCODE==7'b0110011; //FCT3
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wire MAC = FLUSH ? 0 : XMAC; // OPCODE==7'b0110011; //FCT3
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wire MAC = FLUSH ? 0 : XMAC; // OPCODE==7'b0110011; //FCT3
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//wire FCC = FLUSH ? 0 : XFCC; // OPCODE==7'b0001111; //FCT3
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//wire FCC = FLUSH ? 0 : XFCC; // OPCODE==7'b0001111; //FCT3
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//wire CCC = FLUSH ? 0 : XCCC; // OPCODE==7'b1110011; //FCT3
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//wire CCC = FLUSH ? 0 : XCCC; // OPCODE==7'b1110011; //FCT3
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`ifdef __THREADING__
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`ifdef __THREADING__
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`ifdef __3STAGE__
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`ifdef __3STAGE__
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reg [31:0] NXPC2 [0:1]; // 32-bit program counter t+2
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reg [31:0] NXPC2 [0:`NTHREADS-1]; // 32-bit program counter t+2
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`endif
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`endif
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reg [31:0] NXPC; // 32-bit program counter t+1
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reg [31:0] PC; // 32-bit program counter t+0
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`ifdef __RV32E__
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`ifdef __RV32E__
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reg [31:0] REG1 [0:31]; // general-purpose 16x32-bit registers (s1)
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reg [31:0] REG1 [0:16*`NTHREADS-1]; // general-purpose 16x32-bit registers (s1)
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reg [31:0] REG2 [0:31]; // general-purpose 16x32-bit registers (s2)
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reg [31:0] REG2 [0:16*`NTHREADS-1]; // general-purpose 16x32-bit registers (s2)
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`else
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`else
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reg [31:0] REG1 [0:63]; // general-purpose 32x32-bit registers (s1)
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reg [31:0] REG1 [0:32*`NTHREADS-1]; // general-purpose 32x32-bit registers (s1)
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reg [31:0] REG2 [0:63]; // general-purpose 32x32-bit registers (s2)
|
reg [31:0] REG2 [0:32*`NTHREADS-1]; // general-purpose 32x32-bit registers (s2)
|
`endif
|
`endif
|
`else
|
`else
|
`ifdef __3STAGE__
|
`ifdef __3STAGE__
|
reg [31:0] NXPC2; // 32-bit program counter t+2
|
reg [31:0] NXPC2; // 32-bit program counter t+2
|
`endif
|
`endif
|
reg [31:0] NXPC; // 32-bit program counter t+1
|
|
reg [31:0] PC; // 32-bit program counter t+0
|
|
|
|
`ifdef __RV32E__
|
`ifdef __RV32E__
|
reg [31:0] REG1 [0:15]; // general-purpose 16x32-bit registers (s1)
|
reg [31:0] REG1 [0:15]; // general-purpose 16x32-bit registers (s1)
|
reg [31:0] REG2 [0:15]; // general-purpose 16x32-bit registers (s2)
|
reg [31:0] REG2 [0:15]; // general-purpose 16x32-bit registers (s2)
|
`else
|
`else
|
reg [31:0] REG1 [0:31]; // general-purpose 32x32-bit registers (s1)
|
reg [31:0] REG1 [0:31]; // general-purpose 32x32-bit registers (s1)
|
reg [31:0] REG2 [0:31]; // general-purpose 32x32-bit registers (s2)
|
reg [31:0] REG2 [0:31]; // general-purpose 32x32-bit registers (s2)
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
reg [31:0] NXPC; // 32-bit program counter t+1
|
|
reg [31:0] PC; // 32-bit program counter t+0
|
|
|
// source-1 and source-1 register selection
|
// source-1 and source-1 register selection
|
|
|
wire signed [31:0] S1REG = REG1[S1PTR];
|
wire signed [31:0] S1REG = REG1[S1PTR];
|
wire signed [31:0] S2REG = REG2[S2PTR];
|
wire signed [31:0] S2REG = REG2[S2PTR];
|
|
|
wire [31:0] U1REG = REG1[S1PTR];
|
wire [31:0] U1REG = REG1[S1PTR];
|
wire [31:0] U2REG = REG2[S2PTR];
|
wire [31:0] U2REG = REG2[S2PTR];
|
|
|
// L-group of instructions (OPCODE==7'b0000011)
|
// L-group of instructions (OPCODE==7'b0000011)
|
|
|
`ifdef __FLEXBUZZ__
|
`ifdef __FLEXBUZZ__
|
|
|
wire [31:0] LDATA = FCT3[1:0]==0 ? { FCT3[2]==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } :
|
wire [31:0] LDATA = FCT3[1:0]==0 ? { FCT3[2]==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } :
|
FCT3[1:0]==1 ? { FCT3[2]==0&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } :
|
FCT3[1:0]==1 ? { FCT3[2]==0&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } :
|
DATAI;
|
DATAI;
|
`else
|
`else
|
wire [31:0] LDATA = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? { FCT3==0&&DATAI[31] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[31:24] } :
|
wire [31:0] LDATA = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? { FCT3==0&&DATAI[31] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[31:24] } :
|
DADDR[1:0]==2 ? { FCT3==0&&DATAI[23] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[23:16] } :
|
DADDR[1:0]==2 ? { FCT3==0&&DATAI[23] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[23:16] } :
|
DADDR[1:0]==1 ? { FCT3==0&&DATAI[15] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[15: 8] } :
|
DADDR[1:0]==1 ? { FCT3==0&&DATAI[15] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[15: 8] } :
|
{ FCT3==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } ):
|
{ FCT3==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } ):
|
FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? { FCT3==1&&DATAI[31] ? ALL1[31:16]:ALL0[31:16] , DATAI[31:16] } :
|
FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? { FCT3==1&&DATAI[31] ? ALL1[31:16]:ALL0[31:16] , DATAI[31:16] } :
|
{ FCT3==1&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } ) :
|
{ FCT3==1&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } ) :
|
DATAI;
|
DATAI;
|
`endif
|
`endif
|
|
|
// S-group of instructions (OPCODE==7'b0100011)
|
// S-group of instructions (OPCODE==7'b0100011)
|
|
|
`ifdef __FLEXBUZZ__
|
`ifdef __FLEXBUZZ__
|
|
|
wire [31:0] SDATA = U2REG; /* FCT3==0 ? { ALL0 [31: 8], U2REG[ 7:0] } :
|
wire [31:0] SDATA = U2REG; /* FCT3==0 ? { ALL0 [31: 8], U2REG[ 7:0] } :
|
FCT3==1 ? { ALL0 [31:16], U2REG[15:0] } :
|
FCT3==1 ? { ALL0 [31:16], U2REG[15:0] } :
|
U2REG;*/
|
U2REG;*/
|
`else
|
`else
|
wire [31:0] SDATA = FCT3==0 ? ( DADDR[1:0]==3 ? { U2REG[ 7: 0], ALL0 [23:0] } :
|
wire [31:0] SDATA = FCT3==0 ? ( DADDR[1:0]==3 ? { U2REG[ 7: 0], ALL0 [23:0] } :
|
DADDR[1:0]==2 ? { ALL0 [31:24], U2REG[ 7:0], ALL0[15:0] } :
|
DADDR[1:0]==2 ? { ALL0 [31:24], U2REG[ 7:0], ALL0[15:0] } :
|
DADDR[1:0]==1 ? { ALL0 [31:16], U2REG[ 7:0], ALL0[7:0] } :
|
DADDR[1:0]==1 ? { ALL0 [31:16], U2REG[ 7:0], ALL0[7:0] } :
|
{ ALL0 [31: 8], U2REG[ 7:0] } ) :
|
{ ALL0 [31: 8], U2REG[ 7:0] } ) :
|
FCT3==1 ? ( DADDR[1]==1 ? { U2REG[15: 0], ALL0 [15:0] } :
|
FCT3==1 ? ( DADDR[1]==1 ? { U2REG[15: 0], ALL0 [15:0] } :
|
{ ALL0 [31:16], U2REG[15:0] } ) :
|
{ ALL0 [31:16], U2REG[15:0] } ) :
|
U2REG;
|
U2REG;
|
`endif
|
`endif
|
|
|
// C-group not implemented yet!
|
// C-group not implemented yet!
|
|
|
wire [31:0] CDATA = 0; // status register istructions not implemented yet
|
wire [31:0] CDATA = 0; // status register istructions not implemented yet
|
|
|
// RM-group of instructions (OPCODEs==7'b0010011/7'b0110011), merged! src=immediate(M)/register(R)
|
// RM-group of instructions (OPCODEs==7'b0010011/7'b0110011), merged! src=immediate(M)/register(R)
|
|
|
wire signed [31:0] S2REGX = XMCC ? SIMM : S2REG;
|
wire signed [31:0] S2REGX = XMCC ? SIMM : S2REG;
|
wire [31:0] U2REGX = XMCC ? UIMM : U2REG;
|
wire [31:0] U2REGX = XMCC ? UIMM : U2REG;
|
|
|
wire [31:0] RMDATA = FCT3==7 ? U1REG&S2REGX :
|
wire [31:0] RMDATA = FCT3==7 ? U1REG&S2REGX :
|
FCT3==6 ? U1REG|S2REGX :
|
FCT3==6 ? U1REG|S2REGX :
|
FCT3==4 ? U1REG^S2REGX :
|
FCT3==4 ? U1REG^S2REGX :
|
FCT3==3 ? U1REG<U2REGX?1:0 : // unsigned
|
FCT3==3 ? U1REG<U2REGX?1:0 : // unsigned
|
FCT3==2 ? S1REG<S2REGX?1:0 : // signed
|
FCT3==2 ? S1REG<S2REGX?1:0 : // signed
|
FCT3==0 ? (XRCC&&FCT7[5] ? U1REG-U2REGX : U1REG+S2REGX) :
|
FCT3==0 ? (XRCC&&FCT7[5] ? U1REG-U2REGX : U1REG+S2REGX) :
|
FCT3==1 ? U1REG<<U2REGX[4:0] :
|
FCT3==1 ? U1REG<<U2REGX[4:0] :
|
//FCT3==5 ?
|
//FCT3==5 ?
|
|
|
// maybe the $signed solves the problem for MODELSIM too! needs to be tested!
|
// maybe the $signed solves the problem for MODELSIM too! needs to be tested!
|
//`ifdef MODEL_TECH
|
//`ifdef MODEL_TECH
|
// FCT7[5] ? -((-U1REG)>>U2REGX[4:0]; // workaround for modelsim
|
// FCT7[5] ? -((-U1REG)>>U2REGX[4:0]; // workaround for modelsim
|
//`else
|
//`else
|
FCT7[5] ? $signed(S1REG>>>U2REGX[4:0]) : // (FCT7[5] ? U1REG>>>U2REG[4:0] :
|
FCT7[5] ? $signed(S1REG>>>U2REGX[4:0]) : // (FCT7[5] ? U1REG>>>U2REG[4:0] :
|
//`endif
|
//`endif
|
U1REG>>U2REGX[4:0];
|
U1REG>>U2REGX[4:0];
|
`ifdef __MAC16X16__
|
`ifdef __MAC16X16__
|
|
|
// MAC instruction rd += s1*s2 (OPCODE==7'b1111111)
|
// MAC instruction rd += s1*s2 (OPCODE==7'b1111111)
|
//
|
//
|
// 0000000 01100 01011 100 01100 0110011 xor a2,a1,a2
|
// 0000000 01100 01011 100 01100 0110011 xor a2,a1,a2
|
// 0000000 01010 01100 000 01010 0110011 add a0,a2,a0
|
// 0000000 01010 01100 000 01010 0110011 add a0,a2,a0
|
// 0000000 01100 01011 000 01010 1111111 mac a0,a1,a2
|
// 0000000 01100 01011 000 01010 1111111 mac a0,a1,a2
|
//
|
//
|
// 0000 0000 1100 0101 1000 0101 0111 1111 = 00c5857F
|
// 0000 0000 1100 0101 1000 0101 0111 1111 = 00c5857F
|
|
|
wire signed [15:0] K1TMP = S1REG[15:0];
|
wire signed [15:0] K1TMP = S1REG[15:0];
|
wire signed [15:0] K2TMP = S2REG[15:0];
|
wire signed [15:0] K2TMP = S2REG[15:0];
|
wire signed [31:0] KDATA = K1TMP*K2TMP;
|
wire signed [31:0] KDATA = K1TMP*K2TMP;
|
|
|
`endif
|
`endif
|
|
|
// J/B-group of instructions (OPCODE==7'b1100011)
|
// J/B-group of instructions (OPCODE==7'b1100011)
|
|
|
wire BMUX = BCC==1 && (
|
wire BMUX = BCC==1 && (
|
FCT3==4 ? S1REG< S2REGX : // blt
|
FCT3==4 ? S1REG< S2REGX : // blt
|
FCT3==5 ? S1REG>=S2REG : // bge
|
FCT3==5 ? S1REG>=S2REG : // bge
|
FCT3==6 ? U1REG< U2REGX : // bltu
|
FCT3==6 ? U1REG< U2REGX : // bltu
|
FCT3==7 ? U1REG>=U2REG : // bgeu
|
FCT3==7 ? U1REG>=U2REG : // bgeu
|
FCT3==0 ? !(U1REG^S2REGX) : //U1REG==U2REG : // beq
|
FCT3==0 ? !(U1REG^S2REGX) : //U1REG==U2REG : // beq
|
/*FCT3==1 ? */ U1REG^S2REGX); //U1REG!=U2REG); // bne
|
/*FCT3==1 ? */ U1REG^S2REGX); //U1REG!=U2REG); // bne
|
//0);
|
//0);
|
|
|
wire JREQ = (JAL||JALR||BMUX);
|
wire JREQ = (JAL||JALR||BMUX);
|
wire [31:0] JVAL = JALR ? DADDR : PC+SIMM; // SIMM + (JALR ? U1REG : PC);
|
wire [31:0] JVAL = JALR ? DADDR : PC+SIMM; // SIMM + (JALR ? U1REG : PC);
|
|
|
`ifdef SIMULATION
|
`ifdef SIMULATION
|
`ifdef __PERFMETER__
|
`ifdef __PERFMETER__
|
integer clocks=0, thread0=0, thread1=0, load=0, store=0, flush=0, halt=0;
|
|
|
integer clocks=0, running=0, load=0, store=0, flush=0, halt=0;
|
|
|
|
`ifdef __THREADING__
|
|
integer thread[0:`NTHREADS-1];
|
|
integer i;
|
|
|
|
initial for(i=0;i!=`NTHREADS;i=i+1) thread[i] = 0;
|
|
`endif
|
|
|
always@(posedge CLK)
|
always@(posedge CLK)
|
begin
|
begin
|
if(!XRES)
|
if(!XRES)
|
begin
|
begin
|
clocks = clocks+1;
|
clocks = clocks+1;
|
|
|
if(HLT)
|
if(HLT)
|
begin
|
begin
|
if(SCC) store = store+1;
|
if(SCC) store = store+1;
|
else if(LCC) load = load +1;
|
else if(LCC) load = load +1;
|
else halt = halt +1;
|
else halt = halt +1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(FLUSH)
|
if(FLUSH)
|
begin
|
begin
|
flush=flush+1;
|
flush=flush+1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
`ifdef __THREADING__
|
`ifdef __THREADING__
|
|
|
if(XMODE==0) thread0 = thread0+1;
|
for(i=0;i!=`NTHREADS;i=i+1)
|
if(XMODE==1) thread1 = thread1+1;
|
thread[i] = thread[i]+(i==XMODE?1:0);
|
`else
|
|
thread0 = thread0 +1;
|
|
`endif
|
`endif
|
|
running = running +1;
|
end
|
end
|
end
|
end
|
|
|
if(FINISH_REQ)
|
if(FINISH_REQ)
|
begin
|
begin
|
$display("****************************************************************************");
|
$display("****************************************************************************");
|
$display("DarkRISCV Pipeline Report:");
|
$display("DarkRISCV Pipeline Report:");
|
$display("core0 clocks: %0d",clocks);
|
$display("core0 clocks: %0d",clocks);
|
|
|
$display("core0 running: %0d%% (%0d%% thread0, %0d%% thread1)",
|
$display("core0: running %0d%%",100.0*running/clocks);
|
100.0*(thread0+thread1)/clocks,
|
|
100.0*thread0/clocks,
|
`ifdef __THREADING__
|
100.0*thread1/clocks);
|
for(i=0;i!=`NTHREADS;i=i+1) $display(" thread%0d: running %0d%%",i,100.0*thread[i]/clocks);
|
|
`endif
|
|
|
$display("core0 halted: %0d%% (%0d%% load, %0d%% store, %0d%% busy)",
|
$display("core0: halted %0d%% (%0d%% load, %0d%% store, %0d%% busy)",
|
100.0*(load+store)/clocks,
|
100.0*(load+store)/clocks,
|
100.0*load/clocks,
|
100.0*load/clocks,
|
100.0*store/clocks,
|
100.0*store/clocks,
|
100.0*halt/clocks);
|
100.0*halt/clocks);
|
|
|
$display("core0 stalled: %0d%%",100.0*flush/clocks);
|
$display("core0: stalled %0d%%",100.0*flush/clocks);
|
|
|
|
|
|
|
$display("****************************************************************************");
|
$display("****************************************************************************");
|
$finish();
|
$finish();
|
end
|
end
|
end
|
end
|
end
|
end
|
`else
|
`else
|
$finish();
|
$finish();
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
always@(posedge CLK)
|
always@(posedge CLK)
|
begin
|
begin
|
RESMODE <= RES ? -1 : RESMODE ? RESMODE-1 : 0;
|
RESMODE <= RES ? -1 : RESMODE ? RESMODE-1 : 0;
|
|
|
XRES <= |RESMODE;
|
XRES <= |RESMODE;
|
|
|
`ifdef __3STAGE__
|
`ifdef __3STAGE__
|
FLUSH <= XRES ? 2 : HLT ? FLUSH : // reset and halt
|
FLUSH <= XRES ? 2 : HLT ? FLUSH : // reset and halt
|
FLUSH ? FLUSH-1 :
|
FLUSH ? FLUSH-1 :
|
(JAL||JALR||BMUX) ? 2 : 0; // flush the pipeline!
|
(JAL||JALR||BMUX) ? 2 : 0; // flush the pipeline!
|
`else
|
`else
|
FLUSH <= XRES ? 1 : HLT ? FLUSH : // reset and halt
|
FLUSH <= XRES ? 1 : HLT ? FLUSH : // reset and halt
|
(JAL||JALR||BMUX); // flush the pipeline!
|
(JAL||JALR||BMUX); // flush the pipeline!
|
`endif
|
`endif
|
|
|
`ifdef __RV32E__
|
`ifdef __RV32E__
|
REG1[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
REG1[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
`else
|
`else
|
REG1[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
REG1[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
`endif
|
`endif
|
HLT ? REG1[DPTR] : // halt
|
HLT ? REG1[DPTR] : // halt
|
!DPTR ? 0 : // x0 = 0, always!
|
!DPTR ? 0 : // x0 = 0, always!
|
AUIPC ? PC+SIMM :
|
AUIPC ? PC+SIMM :
|
JAL||
|
JAL||
|
JALR ? NXPC :
|
JALR ? NXPC :
|
LUI ? SIMM :
|
LUI ? SIMM :
|
LCC ? LDATA :
|
LCC ? LDATA :
|
MCC||RCC ? RMDATA:
|
MCC||RCC ? RMDATA:
|
`ifdef __MAC16X16__
|
`ifdef __MAC16X16__
|
MAC ? REG2[DPTR]+KDATA :
|
MAC ? REG2[DPTR]+KDATA :
|
`endif
|
`endif
|
//CCC ? CDATA :
|
//CCC ? CDATA :
|
REG1[DPTR];
|
REG1[DPTR];
|
`ifdef __RV32E__
|
`ifdef __RV32E__
|
REG2[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
REG2[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
`else
|
`else
|
REG2[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
REG2[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
|
`endif
|
`endif
|
HLT ? REG2[DPTR] : // halt
|
HLT ? REG2[DPTR] : // halt
|
!DPTR ? 0 : // x0 = 0, always!
|
!DPTR ? 0 : // x0 = 0, always!
|
AUIPC ? PC+SIMM :
|
AUIPC ? PC+SIMM :
|
JAL||
|
JAL||
|
JALR ? NXPC :
|
JALR ? NXPC :
|
LUI ? SIMM :
|
LUI ? SIMM :
|
LCC ? LDATA :
|
LCC ? LDATA :
|
MCC||RCC ? RMDATA:
|
MCC||RCC ? RMDATA:
|
`ifdef __MAC16X16__
|
`ifdef __MAC16X16__
|
MAC ? REG2[DPTR]+KDATA :
|
MAC ? REG2[DPTR]+KDATA :
|
`endif
|
`endif
|
//CCC ? CDATA :
|
//CCC ? CDATA :
|
REG2[DPTR];
|
REG2[DPTR];
|
|
|
`ifdef __3STAGE__
|
`ifdef __3STAGE__
|
|
|
`ifdef __THREADING__
|
`ifdef __THREADING__
|
|
|
NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2[XMODE];
|
NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2[XMODE];
|
|
|
NXPC2[RES ? RESMODE[0] : XMODE] <= XRES ? `__RESETPC__ : HLT ? NXPC2[XMODE] : // reset and halt
|
NXPC2[XRES ? RESMODE[$clog2(`NTHREADS)-1:0] : XMODE] <= XRES ? `__RESETPC__ : HLT ? NXPC2[XMODE] : // reset and halt
|
JREQ ? JVAL : // jmp/bra
|
JREQ ? JVAL : // jmp/bra
|
NXPC2[XMODE]+4; // normal flow
|
NXPC2[XMODE]+4; // normal flow
|
|
|
XMODE <= XRES ? 0 : HLT ? XMODE : // reset and halt
|
XMODE <= XRES ? 0 : HLT ? XMODE : // reset and halt
|
XMODE==0/*&& IREQ*/&&(JAL||JALR||BMUX) ? 1 : // wait pipeflush to switch to irq
|
JAL ? XMODE+1 : XMODE;
|
XMODE==1/*&&!IREQ*/&&(JAL||JALR||BMUX) ? 0 : XMODE; // wait pipeflush to return from irq
|
//XMODE==0/*&& IREQ*/&&(JAL||JALR||BMUX) ? 1 : // wait pipeflush to switch to irq
|
|
//XMODE==1/*&&!IREQ*/&&(JAL||JALR||BMUX) ? 0 : XMODE; // wait pipeflush to return from irq
|
|
|
`else
|
`else
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NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2;
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NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2;
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|
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NXPC2 <= XRES ? `__RESETPC__ : HLT ? NXPC2 : // reset and halt
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NXPC2 <= XRES ? `__RESETPC__ : HLT ? NXPC2 : // reset and halt
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JREQ ? JVAL : // jmp/bra
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JREQ ? JVAL : // jmp/bra
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NXPC2+4; // normal flow
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NXPC2+4; // normal flow
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|
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`endif
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`endif
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`else
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`else
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NXPC <= XRES ? `__RESETPC__ : HLT ? NXPC : // reset and halt
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NXPC <= XRES ? `__RESETPC__ : HLT ? NXPC : // reset and halt
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JREQ ? JVAL : // jmp/bra
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JREQ ? JVAL : // jmp/bra
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NXPC+4; // normal flow
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NXPC+4; // normal flow
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`endif
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`endif
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PC <= /*XRES ? `__RESETPC__ :*/ HLT ? PC : NXPC; // current program counter
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PC <= /*XRES ? `__RESETPC__ :*/ HLT ? PC : NXPC; // current program counter
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end
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end
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// IO and memory interface
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// IO and memory interface
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|
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assign DATAO = SDATA; // SCC ? SDATA : 0;
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assign DATAO = SDATA; // SCC ? SDATA : 0;
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assign DADDR = U1REG + SIMM; // (SCC||LCC) ? U1REG + SIMM : 0;
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assign DADDR = U1REG + SIMM; // (SCC||LCC) ? U1REG + SIMM : 0;
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|
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// based in the Scc and Lcc
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// based in the Scc and Lcc
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|
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`ifdef __FLEXBUZZ__
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`ifdef __FLEXBUZZ__
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assign RW = !SCC;
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assign RW = !SCC;
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assign DLEN[0] = (SCC||LCC)&&FCT3[1:0]==0;
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assign DLEN[0] = (SCC||LCC)&&FCT3[1:0]==0;
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assign DLEN[1] = (SCC||LCC)&&FCT3[1:0]==1;
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assign DLEN[1] = (SCC||LCC)&&FCT3[1:0]==1;
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assign DLEN[2] = (SCC||LCC)&&FCT3[1:0]==2;
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assign DLEN[2] = (SCC||LCC)&&FCT3[1:0]==2;
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`else
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`else
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assign RD = LCC;
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assign RD = LCC;
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assign WR = SCC;
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assign WR = SCC;
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assign BE = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? 4'b1000 : // sb/lb
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assign BE = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? 4'b1000 : // sb/lb
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DADDR[1:0]==2 ? 4'b0100 :
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DADDR[1:0]==2 ? 4'b0100 :
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DADDR[1:0]==1 ? 4'b0010 :
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DADDR[1:0]==1 ? 4'b0010 :
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4'b0001 ) :
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4'b0001 ) :
|
FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? 4'b1100 : // sh/lh
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FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? 4'b1100 : // sh/lh
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4'b0011 ) :
|
4'b0011 ) :
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4'b1111; // sw/lw
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4'b1111; // sw/lw
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`endif
|
`endif
|
|
|
`ifdef __3STAGE__
|
`ifdef __3STAGE__
|
`ifdef __THREADING__
|
`ifdef __THREADING__
|
assign IADDR = NXPC2[XMODE];
|
assign IADDR = NXPC2[XMODE];
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`else
|
`else
|
assign IADDR = NXPC2;
|
assign IADDR = NXPC2;
|
`endif
|
`endif
|
`else
|
`else
|
assign IADDR = NXPC;
|
assign IADDR = NXPC;
|
`endif
|
`endif
|
|
|
assign DEBUG = { XRES, |FLUSH, SCC, LCC };
|
assign DEBUG = { XRES, |FLUSH, SCC, LCC };
|
|
|
endmodule
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endmodule
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