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g e jl X6 jl f 7 T& T& SoC / OpenRISC Development Interface Introduction
The Development Interface is used for development purposes (Boundary Scan testing, debugging, program flow tracking, etc.). It is an interface between the OpenRISC, peripheral cores, and any free (GDB) or commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a JTAG port that is fully IEEE 1149.1 compatible. The Development Interface also contains a trace buffer and support for tracing the program flow, execution coverage, and profiling the code.
Features
Figure 1: Soc/OpenRISC Development Interface
The Development Interface provides the following features:
Direct internal signal monitoring (no need for additional software)
IEEE 1149.1 compatible TAP controller that supports all IEEE 1149.1 basic functions and more
Boundary Scan Testing (additional BS equipment that connects to the JTAG pins is needed)
Program Trace incorporated for program flow monitoring
OpenRISC debug interface
WISHBONE interface
General Description
Architecture
Figure 1 above shows the general architecture of the Ethernet IP core. It consists of several building blocks:
JTAG interface with the TAP controller
RISC debug interface
Trace
Trace registers
WISHBONE interface
Several scan chains
Boundary Scan (BS) cells (not in the figure)
JTAG Interface with TAP Controller
The JTAG interface with TAP controller is a fully IEEE 1149.1 std. compliant interface that supports all by standard requested commands plus some additional ones. The controller with the interface is one of the basic components of the development system. A device running the BS, trace, or debugging software connects to the development interface through the five JTAG pins. The controller is connected to several scan chains that are selectable through one of the additional commands.
RISC Debug Interface
The SoC development interface connects to the RISC development interface (which is part of the RISC) through the RISC debug scan chain. The complete control of the RISC is achieved by using this scan chain (setting watchpoints, breakpoints, registers, etc.).
Trace
The trace is used for tracking the program flow. This is especially useful when the RISC uses caches and the program is not necessarily executed serially. The trace has a large number of different modes to meet all needs a user might have:
Option to change sample structure on-the-fly
Normal mode (RISC is stopped when the buffer is full)
Continuous mode (old samples are overwritten)
Post event recording (recording starts after a certain event)
Prior event recording (recording stops after a certain event)
Post-prior event recording (recording occurs between two events)
If required, the RISC stalls automatically. When running resumes, no action needs to be taken as the RISC recommences exactly from where it stopped.
Boundary Scan (BS) Testing
Except for the BS scan chain, the Development Interface contains everything needed for BS testing. To complete this chain, the ASIC needs to be finished and the pin number determined. One of the commercial BS testers might be connected to the Development Interface for the purpose of BS testing.
WISHBONE Interface
The WISHBONE interface connects the Development Interface to external memory. The core is WISHBONE SoC Interconnection specification Rev. B compliant. The implementation realizes a 32-bit bus width and does not support other bus widths. Other cores linked to the WISHBONE can also be connected to the Development Interface by using the same interface.
Utilization
The table in this section lists the intended applications of the different cores.
CoreFPGA SizeSilicon AreaSpeedPower Consumption
OpenCores reserves the right to make changes in specifications at any time and without notice. The information furnished by
OpenCores in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by OpenCores for its use,
nor for any infringements of patents or other rights of third parties resulting from its use. This product is intended for use in normal
commercial applications. Use of this product in applications such as life-support or life-sustaining equipment is at your own risc.
(footnote continued)
OpenCores
PAGE
- PAGE I -
Development Interface IP
I
OpenCores
PAGE
- PAGE I -
Development Interface IP
I
PAGE
PAGE 2
Development Interface
Name of Device
EMBED Visio.Drawing.6
( 5 ( ? b I J _ d j ? Z Y ^ 4 ~{~{ s 0J, h nH tH 0J,
j 0J, U
|
g e jl X6 jl f 7 T& T& SoC / OpenRISC Development Interface Introduction
The Development Interface is used for development purposes (Boundary Scan testing, debugging, program flow tracking, etc.). It is an interface between the OpenRISC, peripheral cores, and any free (GDB) or commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a JTAG port that is fully IEEE 1149.1 compatible. The Development Interface also contains a trace buffer and support for tracing the program flow, execution coverage, and profiling the code.
Features
Figure 1: Soc/OpenRISC Development Interface
The Development Interface provides the following features:
Direct internal signal monitoring (no need for additional software)
IEEE 1149.1 compatible TAP controller that supports all IEEE 1149.1 basic functions and more
Boundary Scan Testing (additional BS equipment that connects to the JTAG pins is needed)
Program Trace incorporated for program flow monitoring
OpenRISC debug interface
WISHBONE interface
General Description
Architecture
Figure 1 above shows the general architecture of the Ethernet IP core. It consists of several building blocks:
JTAG interface with the TAP controller
RISC debug interface
Trace
Trace registers
WISHBONE interface
Several scan chains
Boundary Scan (BS) cells (not in the figure)
JTAG Interface with TAP Controller
The JTAG interface with TAP controller is a fully IEEE 1149.1 std. compliant interface that supports all by standard requested commands plus some additional ones. The controller with the interface is one of the basic components of the development system. A device running the BS, trace, or debugging software connects to the development interface through the five JTAG pins. The controller is connected to several scan chains that are selectable through one of the additional commands.
RISC Debug Interface
The SoC development interface connects to the RISC development interface (which is part of the RISC) through the RISC debug scan chain. The complete control of the RISC is achieved by using this scan chain (setting watchpoints, breakpoints, registers, etc.).
Trace
The trace is used for tracking the program flow. This is especially useful when the RISC uses caches and the program is not necessarily executed serially. The trace has a large number of different modes to meet all needs a user might have:
Option to change sample structure on-the-fly
Normal mode (RISC is stopped when the buffer is full)
Continuous mode (old samples are overwritten)
Post event recording (recording starts after a certain event)
Prior event recording (recording stops after a certain event)
Post-prior event recording (recording occurs between two events)
If required, the RISC stalls automatically. When running resumes, no action needs to be taken as the RISC recommences exactly from where it stopped.
Boundary Scan (BS) Testing
Except for the BS scan chain, the Development Interface contains everything needed for BS testing. To complete this chain, the ASIC needs to be finished and the pin number determined. One of the commercial BS testers might be connected to the Development Interface for the purpose of BS testing.
WISHBONE Interface
The WISHBONE interface connects the Development Interface to external memory. The core is WISHBONE SoC Interconnection specification Rev. B compliant. The implementation realizes a 32-bit bus width and does not support other bus widths. Other cores linked to the WISHBONE can also be connected to the Development Interface by using the same interface.
Utilization
The table in this section lists the intended applications of the different cores.
CoreFPGA SizeSilicon AreaSpeedPower Consumption
OpenCores reserves the right to make changes in specifications at any time and without notice. The information furnished by
OpenCores in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by OpenCores for its use,
nor for any infringements of patents or other rights of third parties resulting from its use. This product is intended for use in normal
commercial applications. Use of this product in applications such as life-support or life-sustaining equipment is at your own risc.
(footnote continued)
OpenCores
PAGE
- PAGE I -
Development Interface IP
I
OpenCores
PAGE
- PAGE I -
Development Interface IP
I
PAGE
PAGE 2
Development Interface
Name of Device
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ral Description # 4 D 4 4 4 # 9 9 9
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4 - - ' @ "Arial w@
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4 - - ' @ "Arial w@
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~LSwUSw 0 - 2
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~LSwUSw 0 - 2
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Architecture9 . 3 . . 3 .
2
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Architecture9 . 3 . . 3 .
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r . - U 2
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r . - U 2
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@
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@
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1 Figure 1 above shows the general architecture of . ) ) % * % * * ) % ) * : ) % ) % ) % % % % ) % % ) % * O 2
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1 Figure 1 above shows the general architecture of . ) ) % * % * * ) % ) * : ) % ) % ) % % % % ) % % ) % * O 2
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- the Ethernet IP core. It consists of several ) % ; 3 ) % ) % ; / ; % * % ; ; % * ) : * : % ) % % # 2
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- the Ethernet IP core. It consists of several ) % ; 3 ) % ) % ; / ; % * % ; ; % * ) : * : % ) % % # 2
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building blocks:* ) * ) ) * * % )
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building blocks:* ) * ) ) * * % )
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2
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&
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p - F 2
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p - F 2
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@ ' JTAG interface with the TAP controller ! 4 ; < ) % % % % : ) ) % 4 ; / % * ) * %
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@ ' JTAG interface with the TAP controller ! 4 ; < ) % % % % : ) ) % 4 ; / % * ) * %
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p - ) 2
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@ RISC debug interface7 . 7 * % * ) ) ) % % % %
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@ RISC debug interface7 . 7 * % * ) ) ) % % % %
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@ Trace registers:4 % % % % ) %
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hains ) % )
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@ % Boundary Scan (BS) cells (not in the 8 * ) ) * % ( ? . % % ) > 8 . > % % > ) * > ) > ) % ' 2
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Z@ figure) ) ) %
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" JTAG Interface with TAP Controller. 3 < A 3 . . . . A 3 3 < 7 < 3 3 3 .
2
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" JTAG Interface with TAP Controller. 3 < A 3 . . . . A 3 3 < 7 < 3 3 3 .
2
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. - M 2
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. - M 2
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y
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, The JTAG interface with TAP controller is a 4 ) % ( ! 4 ; < ( ) % % % % ( : ) ( 4 ; / ' % * ) * % ' ' % S 2
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, The JTAG interface with TAP controller is a 4 ) % ( ! 4 ; < ( ) % % % % ( : ) ( 4 ; / ' % * ) * % ' ' % S 2
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0 fully IEEE 1149.1 std. compliant interface that ) ( 3 3 3 * * * * * * % * ? * % ) ) % % % % ) % M 2
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0 fully IEEE 1149.1 std. compliant interface that ) ( 3 3 3 * * * * * * % * ? * % ) ) % % % % ) % M 2
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9
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9
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, supports all by standard requested commands ) * * * + % + * ( + % ) * % * + % * ) % % * + % * ? ? % ) * = 2
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, supports all by standard requested commands ) * * * + % + * ( + % ) * % * + % * ) % % * + % * ? ? % ) * = 2
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! plus some additional ones. The cor* ) " * ? % " % * * * ) % " * ) % " 4 ) % " % * 2
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! plus some additional ones. The cor* ) " * ? % " % * * * ) % " * ) % " 4 ) % " % * 2
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W ntroller with ) * % ! : ) S 2
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W ntroller with ) * % ! : ) S 2
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0 the interface is one of the basic components of ) % ) % % % % * ) % * ) % * % % % * ? * * ) % ) * O 2
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0 the interface is one of the basic components of ) % ) % % % % * ) % * ) % * % % % * ? * * ) % ) * O 2
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X
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- the development system. A device running the ) % # * % ) % * * ? % ) # ( % ? # ; # * % ) % % # ) ) ) ) ) # ) % U 2
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- the development system. A device running the ) % # * % ) % * * ? % ) # ( % ? # ; # * % ) % % # ) ) ) ) ) # ) % U 2
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1 BS, trace, or debugging software connects to the 8 . % % % * * % * ) ) ) ) ) * : % % % * ) ) % % * ) % M 2
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1 BS, trace, or debugging software connects to the 8 . % % % * * % * ) ) ) ) ) * : % % % * ) ) % % * ) % M 2
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, development interface through the five JTAG * % ) % * * ? % ) + ) % % % % + ) * ) ) ) * ) % * ) % * ! 4 ; < V 2
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, development interface through the five JTAG * % ) % * * ? % ) + ) % % % % + ) * ) ) ) * ) % * ) % * ! 4 ; < V 2
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x
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x
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2 pins. The controller is connected to several scan * ) 4 ) % % * ) * % % * ) ) % % % * * % ) % % % % ) 2
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2 pins. The controller is connected to several scan * ) 4 ) % % * ) * % % * ) ) % % % * * % ) % % % % ) 2
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chains% ) % ) G 2
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chains% ) % ) G 2
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} ( that are selectable through one of the , ) % , % % , % % % % * % , ) * ) ) ) , * ) % , * , ) % + 2
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} ( that are selectable through one of the , ) % , % % , % % % % * % , ) * ) ) ) , * ) % , * , ) % + 2
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7
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7
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additional commands. % * * * ) % % * ? ? % ) *
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additional commands. % * * * ) % % * ? ? % ) *
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7
% @ Times New Roman LSwUSw 0 -
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7
% @ Times New Roman LSwUSw 0 -
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RISC Debug Interface< 7 < < . 3 3 3 3 . . . .
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RISC Debug Interface< 7 < < . 3 3 3 3 . . . .
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. - P 2
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. - P 2
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. The SoC development interface connects to the 4 ) % . * 7 * % ) % * * ? % ) ) % % % % % * ) ) % % * ) % O 2
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- RISC development interface (which is part of 7 . 7 ( * % ) % * * ? % ) ( ) % % % % ' : ) % ) ' ' * % ' * O 2
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- the RISC) through the RISC debug scan chain. ) % 7 . 7 ) * ) ) ) ) % 7 . 7 * % * ) ) % % ) % ) % ) A 2
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$ The complete control of the RISC is 4 ) % $ % * ? * % % # % * ) * # * # ) % # 7 . 7 # # 2
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RISC7 . 7 - - - $ :
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RISC7 . 7 - - - $ :
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- - - Times New Roman LSwUSw 0 - - . - % 2
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Optional Scan Chains< * * ) % . % % ) 7 ) % ) - - Times New Roman LSwUSw 0 - - . - 2
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Optional Scan Chains< * * ) % . % % ) 7 ) % ) - - Times New Roman LSwUSw 0 - - . - 2
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1 JTAG* 4 7 A 2
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1 JTAG* 4 7 A 2
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Interface with . . . * . ; . 2
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Interface with . . . * . ; . 2
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the TAB . . 4 7 7 2
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the TAB . . 4 7 7 2
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Controller< . . . . - - Times New Roman LSwUSw 0 - - . - 2
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I Risc< * * 2
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Debug< . . . . 2
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w Interfacer . . . * . - - - $ ^ L^ L^ - - Arial w@
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w Interfacer . . . * . - - - $ ^ L^ L^ - - Arial w@
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2
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2
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E RISCH C H 2
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Q + :
2
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2
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A DevelopmentH 8 1 8 8 8 T 8 8 2
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A DevelopmentH 8 1 8 8 8 T 8 8 2
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Interfacer 8 8 ! 8 2 8 - - - $ Bu
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Peripheral7 . . . . . 2
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Blocks7 . * + * - - Times New Roman LSwUSw 0 - - . - ! 2
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Blocks7 . * + * - - Times New Roman LSwUSw 0 - - . - ! 2
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s- Block Scan Chains 8 * % ) . % % ) 7 ) % ) - - - $ :
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s- Block Scan Chains 8 * % ) . % % ) 7 ) % ) - - - $ :
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:
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- - - + 4 D M ] f v % . > G W ` p y ( 8 A Q Z j s x h _ O F 6 - ~ n e U L < 3 #
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z j : # V t y m T ( 5 c f 6 A Y ^ # B W X Z \ ^ q w Y ] " # 3 4 B Z \ ^ 3 3 $ 2 4 > Z \ ] z j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c j e a n n e V D : \ M y D o c u m e n t s \ M a r k e t i n g D o c u m e n t s \ P r o d u c t P r e v i e w s \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) . d o c i g o r m O C : \ c v s r o o t \ d b g _ i n t e r f a c e \ d o c \ s r c \ D b g S u p p p r o d u c t b r i e f ( e d i t e d ) f o o p e n c o r e s . d o c i g o r m C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f D b g S u p p p r o d u c t b r i e f ( e d i t e d ) f o o p e n c o r e s . a s d i g o r m C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f D b g S u p p p r o d u c t b r i e f ( e d i t e d ) f o o p e n c o r e s . a s d = |V }6C| ~0H ft L j\( 8f n җ 0d Є ) '{Lݒ zLݒ X B!rLݒ >'
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