//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_defines.v ////
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//// dbg_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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//
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// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
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// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
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// Initial release
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// Initial release
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//
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//
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//
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//
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// Enable TRACE
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// Enable TRACE
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`define TRACE_ENABLED // Uncomment this define to activate the trace
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`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'hdeadbeef
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`define IDCODE_VALUE 32'hdeadbeef
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// Define master clock (RISC clock)
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// Define master clock (RISC clock)
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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// Length of the Instruction register
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// Length of the Instruction register
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`define IR_LENGTH 4
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`define IR_LENGTH 4
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// Length of the Data register (must be equal to the longest scan chain)
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// Length of the Data register (must be equal to the longest scan chain)
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`define DR_LENGTH 73
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`define DR_LENGTH 73
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// Length of the CHAIN ID register
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// Length of the CHAIN ID register
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`define CHAIN_ID_LENGTH 4
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`define CHAIN_ID_LENGTH 4
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// Length of the CRC
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// Length of the CRC
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`define CRC_LENGTH 8
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`define CRC_LENGTH 8
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// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
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// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
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`define TRACECOUNTERWIDTH 5
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`define TRACECOUNTERWIDTH 5
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`define TRACEBUFFERLENGTH 32 // 2^5
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`define TRACEBUFFERLENGTH 32 // 2^5
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`define TRACESAMPLEWIDTH 36
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`define TRACESAMPLEWIDTH 36
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// OpSelect width
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// OpSelect width
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`define OPSELECTWIDTH 3
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`define OPSELECTWIDTH 3
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`define OPSELECTIONCOUNTER 8 //2^3
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`define OPSELECTIONCOUNTER 8 //2^3
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// OpSelect (dbg_op_i) signal meaning
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`define DEBUG_READ_PC 0
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`define DEBUG_READ_LSEA 1
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`define DEBUG_READ_LDATA 2
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`define DEBUG_READ_SDATA 3
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`define DEBUG_READ_SPR 4
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`define DEBUG_WRITE_SPR 5
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`define DEBUG_READ_INSTR 6
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//`define Reserved 7
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// Supported Instructions
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// Supported Instructions
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`define EXTEST 5'b00000
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`define EXTEST 5'b00000
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`define SAMPLE_PRELOAD 5'b00001
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`define SAMPLE_PRELOAD 5'b00001
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`define IDCODE 5'b00010
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`define IDCODE 5'b00010
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`define CHAIN_SELECT 5'b00011
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`define CHAIN_SELECT 5'b00011
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`define INTEST 5'b00100
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`define INTEST 5'b00100
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`define CLAMP 5'b00101
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`define CLAMP 5'b00101
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`define CLAMPZ 5'b00110
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`define CLAMPZ 5'b00110
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`define HIGHZ 5'b00111
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`define HIGHZ 5'b00111
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`define DEBUG 5'b01000
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`define DEBUG 5'b01000
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`define BYPASS 5'b01111
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`define BYPASS 5'b01111
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// Chains
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// Chains
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`define GLOBAL_BS_CHAIN 4'b0000
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`define GLOBAL_BS_CHAIN 4'b0000
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`define RISC_DEBUG_CHAIN 4'b0001
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`define RISC_DEBUG_CHAIN 4'b0001
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`define RISC_TEST_CHAIN 4'b0010
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`define RISC_TEST_CHAIN 4'b0010
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`define TRACE_TEST_CHAIN 4'b0011
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`define TRACE_TEST_CHAIN 4'b0011
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`define REGISTER_SCAN_CHAIN 4'b0100
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`define REGISTER_SCAN_CHAIN 4'b0100
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// Registers addresses
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// Registers addresses
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`define MODER_ADR 5'h00
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`define MODER_ADR 5'h00
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`define TSEL_ADR 5'h01
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`define TSEL_ADR 5'h01
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`define QSEL_ADR 5'h02
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`define QSEL_ADR 5'h02
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`define SSEL_ADR 5'h03
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`define SSEL_ADR 5'h03
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`define RISCOP_ADR 5'h04
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`define RISCOP_ADR 5'h04
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`define RECSEL_ADR 5'h10
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`define RECSEL_ADR 5'h10
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// Registers default values (after reset)
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// Registers default values (after reset)
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`define MODER_DEF 2'h0
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`define MODER_DEF 2'h0
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`define TSEL_DEF 32'h00000000
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`define TSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define RISCOP_DEF 2'h0
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`define RISCOP_DEF 2'h0
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`define RECSEL_DEF 7'h0
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`define RECSEL_DEF 7'h0
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