//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// dbg_tb.v ////
|
//// dbg_tb.v ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// Igor Mohor ////
|
//// Igor Mohor ////
|
//// igorm@opencores.org ////
|
//// igorm@opencores.org ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// All additional information is avaliable in the README.txt ////
|
//// All additional information is avaliable in the README.txt ////
|
//// file. ////
|
//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000,2001 Authors ////
|
//// Copyright (C) 2000,2001 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.11 2002/03/12 14:32:26 mohor
|
|
// Few outputs for boundary scan chain added.
|
|
//
|
// Revision 1.10 2002/03/08 15:27:08 mohor
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// Revision 1.10 2002/03/08 15:27:08 mohor
|
// Structure changed. Hooks for jtag chain added.
|
// Structure changed. Hooks for jtag chain added.
|
//
|
//
|
// Revision 1.9 2001/10/19 11:39:20 mohor
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// Revision 1.9 2001/10/19 11:39:20 mohor
|
// dbg_timescale.v changed to timescale.v This is done for the simulation of
|
// dbg_timescale.v changed to timescale.v This is done for the simulation of
|
// few different cores in a single project.
|
// few different cores in a single project.
|
//
|
//
|
// Revision 1.8 2001/10/17 10:39:17 mohor
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// Revision 1.8 2001/10/17 10:39:17 mohor
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// bs_chain_o added.
|
// bs_chain_o added.
|
//
|
//
|
// Revision 1.7 2001/10/16 10:10:18 mohor
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// Revision 1.7 2001/10/16 10:10:18 mohor
|
// Signal names changed to lowercase.
|
// Signal names changed to lowercase.
|
//
|
//
|
// Revision 1.6 2001/10/15 09:52:50 mohor
|
// Revision 1.6 2001/10/15 09:52:50 mohor
|
// Wishbone interface added, few fixes for better performance,
|
// Wishbone interface added, few fixes for better performance,
|
// hooks for boundary scan testing added.
|
// hooks for boundary scan testing added.
|
//
|
//
|
// Revision 1.5 2001/09/24 14:06:12 mohor
|
// Revision 1.5 2001/09/24 14:06:12 mohor
|
// Changes connected to the OpenRISC access (SPR read, SPR write).
|
// Changes connected to the OpenRISC access (SPR read, SPR write).
|
//
|
//
|
// Revision 1.4 2001/09/20 10:10:29 mohor
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// Revision 1.4 2001/09/20 10:10:29 mohor
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// Working version. Few bugs fixed, comments added.
|
// Working version. Few bugs fixed, comments added.
|
//
|
//
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Minor changes for simulation.
|
// Minor changes for simulation.
|
//
|
//
|
// Revision 1.2 2001/09/18 14:12:43 mohor
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// Revision 1.2 2001/09/18 14:12:43 mohor
|
// Trace fixed. Some registers changed, trace simplified.
|
// Trace fixed. Some registers changed, trace simplified.
|
//
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//
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
|
// Initial official release.
|
//
|
//
|
// Revision 1.3 2001/06/01 22:23:40 mohor
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// Revision 1.3 2001/06/01 22:23:40 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
|
// This is a backup. It is not a fully working version. Not for use, yet.
|
//
|
//
|
// Revision 1.2 2001/05/18 13:10:05 mohor
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// Revision 1.2 2001/05/18 13:10:05 mohor
|
// Headers changed. All additional information is now avaliable in the README.txt file.
|
// Headers changed. All additional information is now avaliable in the README.txt file.
|
//
|
//
|
// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
|
// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
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// Initial release
|
// Initial release
|
//
|
//
|
//
|
//
|
|
|
|
|
`include "timescale.v"
|
`include "timescale.v"
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`include "dbg_defines.v"
|
`include "dbg_defines.v"
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`include "dbg_tb_defines.v"
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`include "dbg_tb_defines.v"
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|
|
// Test bench
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// Test bench
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module dbg_tb;
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module dbg_tb;
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|
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parameter Tp = 1;
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parameter Tp = 1;
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parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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|
|
|
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reg P_TMS, P_TCK;
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reg P_TMS, P_TCK;
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reg P_TRST, P_TDI;
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reg P_TRST, P_TDI;
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reg wb_rst_i;
|
reg wb_rst_i;
|
reg Mclk;
|
reg Mclk;
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|
|
reg [10:0] Wp;
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reg [10:0] Wp;
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reg Bp;
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reg Bp;
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reg [3:0] LsStatus;
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reg [3:0] LsStatus;
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reg [1:0] IStatus;
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reg [1:0] IStatus;
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reg BS_CHAIN_I;
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reg BS_CHAIN_I;
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|
|
wire P_TDO;
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wire P_TDO;
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wire [31:0] ADDR_RISC;
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wire [31:0] ADDR_RISC;
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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|
|
wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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|
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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|
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wire [31:0] wb_adr_i;
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wire [31:0] wb_adr_i;
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wire [31:0] wb_dat_i;
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wire [31:0] wb_dat_i;
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reg [31:0] wb_dat_o;
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reg [31:0] wb_dat_o;
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wire wb_cyc_i;
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wire wb_cyc_i;
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wire wb_stb_i;
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wire wb_stb_i;
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wire [3:0] wb_sel_i;
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wire [3:0] wb_sel_i;
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wire wb_we_i;
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wire wb_we_i;
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reg wb_ack_o;
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reg wb_ack_o;
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wire wb_cab_i;
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wire wb_cab_i;
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reg wb_err_o;
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reg wb_err_o;
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|
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wire ShiftDR;
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wire ShiftDR;
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wire Exit1DR;
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wire Exit1DR;
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wire UpdateDR;
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wire UpdateDR;
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wire UpdateDR_q;
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wire UpdateDR_q;
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wire CaptureDR;
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wire CaptureDR;
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wire IDCODESelected;
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wire IDCODESelected;
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wire CHAIN_SELECTSelected;
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wire CHAIN_SELECTSelected;
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wire DEBUGSelected;
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wire DEBUGSelected;
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wire TDOData_dbg;
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wire TDOData_dbg;
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wire BypassRegister;
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wire BypassRegister;
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wire EXTESTSelected;
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wire EXTESTSelected;
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wire [3:0] mon_cntl_o;
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|
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// Connecting TAP module
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// Connecting TAP module
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tap_top i_tap_top
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tap_top i_tap_top
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.tdo_pad_o(P_TDO), .tdo_padoen_o(tdo_padoen_o),
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.tdo_pad_o(P_TDO), .tdo_padoe_o(tdo_padoe_o),
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|
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// TAP states
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.CaptureDR(CaptureDR),
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.CaptureDR(CaptureDR),
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// Instructions
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
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.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
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// TDO from dbg module
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// TDO from dbg module
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.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
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.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
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// Boundary Scan Chain
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// Boundary Scan Chain
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.bs_chain_i(BS_CHAIN_I)
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.bs_chain_i(BS_CHAIN_I)
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|
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);
|
);
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dbg_top i_dbg_top
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dbg_top i_dbg_top
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(
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(
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.risc_clk_i(Mclk), .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC),
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.risc_clk_i(Mclk), .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC),
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.risc_data_o(DATAIN_RISC), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
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.risc_data_o(DATAIN_RISC), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
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.lsstatus_i(LsStatus), .istatus_i(IStatus), .risc_stall_o(), .reset_o(),
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.lsstatus_i(LsStatus), .istatus_i(IStatus), .risc_stall_o(), .reset_o(),
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.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
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.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
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|
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.wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
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.wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
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.wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
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.wb_err_i(wb_err_o),
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.wb_err_i(wb_err_o),
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|
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// TAP states
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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|
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// Instructions
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected),
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.DEBUGSelected(DEBUGSelected),
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|
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// TAP signals
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// TAP signals
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.BypassRegister(BypassRegister)
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.BypassRegister(BypassRegister),
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|
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.mon_cntl_o(mon_cntl_o)
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|
|
);
|
);
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reg TestEnabled;
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reg TestEnabled;
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initial
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initial
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begin
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begin
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TestEnabled<=#Tp 0;
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TestEnabled<=#Tp 0;
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P_TMS<=#Tp 'hz;
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P_TMS<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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BS_CHAIN_I = 0;
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BS_CHAIN_I = 0;
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Wp<=#Tp 0;
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Wp<=#Tp 0;
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Bp<=#Tp 0;
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Bp<=#Tp 0;
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LsStatus<=#Tp 0;
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LsStatus<=#Tp 0;
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IStatus<=#Tp 0;
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IStatus<=#Tp 0;
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|
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wb_dat_o<=#Tp 32'h0;
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wb_dat_o<=#Tp 32'h0;
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wb_ack_o<=#Tp 1'h0;
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wb_ack_o<=#Tp 1'h0;
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wb_err_o<=#Tp 1'h0;
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wb_err_o<=#Tp 1'h0;
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wb_rst_i<=#Tp 0;
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wb_rst_i<=#Tp 0;
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P_TRST<=#Tp 1;
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P_TRST<=#Tp 1;
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#100 wb_rst_i<=#Tp 1;
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#100 wb_rst_i<=#Tp 1;
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P_TRST<=#Tp 0;
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P_TRST<=#Tp 0;
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#100 wb_rst_i<=#Tp 0;
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#100 wb_rst_i<=#Tp 0;
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P_TRST<=#Tp 1;
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P_TRST<=#Tp 1;
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#Tp TestEnabled<=#Tp 1;
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#Tp TestEnabled<=#Tp 1;
|
end
|
end
|
|
|
|
|
// Generating master clock (RISC clock) 200 MHz
|
// Generating master clock (RISC clock) 200 MHz
|
initial
|
initial
|
begin
|
begin
|
Mclk<=#Tp 0;
|
Mclk<=#Tp 0;
|
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
|
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
|
end
|
end
|
|
|
|
|
// Generating random number for use in DATAOUT_RISC[31:0]
|
// Generating random number for use in DATAOUT_RISC[31:0]
|
reg [31:0] RandNumb;
|
reg [31:0] RandNumb;
|
always @ (posedge Mclk or posedge wb_rst_i)
|
always @ (posedge Mclk or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RandNumb[31:0]<=#Tp 0;
|
RandNumb[31:0]<=#Tp 0;
|
else
|
else
|
RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
|
RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
|
end
|
end
|
|
|
|
|
assign DATAOUT_RISC[31:0] = RandNumb[31:0];
|
assign DATAOUT_RISC[31:0] = RandNumb[31:0];
|
|
|
|
|
always @ (posedge TestEnabled)
|
always @ (posedge TestEnabled)
|
fork
|
fork
|
|
|
begin
|
begin
|
EnableWishboneSlave; // enabling WISHBONE slave
|
EnableWishboneSlave; // enabling WISHBONE slave
|
end
|
end
|
|
|
|
|
begin
|
begin
|
ResetTAP;
|
ResetTAP;
|
GotoRunTestIdle;
|
GotoRunTestIdle;
|
|
|
// Testing read and write to WISHBONE
|
// Testing read and write to WISHBONE
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
|
ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
WriteRISCRegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
|
WriteRISCRegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
//
|
//
|
|
|
// Testing read and write to RISC registers
|
// Testing read and write to RISC registers
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`RISC_DEBUG_CHAIN, 8'h38); // {chain, crc}
|
ChainSelect(`RISC_DEBUG_CHAIN, 8'h38); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
|
|
ReadRISCRegister(32'h12345ead, 8'hbf); // {addr, crc}
|
ReadRISCRegister(32'h12345ead, 8'hbf); // {addr, crc}
|
WriteRISCRegister(32'h11223344, 32'h12345678, 8'haf); // {data, addr, crc}
|
WriteRISCRegister(32'h11223344, 32'h12345678, 8'haf); // {data, addr, crc}
|
//
|
//
|
|
|
|
|
// Testing read and write to internal registers
|
// Testing read and write to internal registers
|
SetInstruction(`IDCODE);
|
SetInstruction(`IDCODE);
|
ReadIDCode; // muten
|
ReadIDCode; // muten
|
|
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
|
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
|
|
|
|
//
|
//
|
// Testing internal registers
|
// Testing internal registers
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
|
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
|
|
WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
|
WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
|
WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
|
WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
|
WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
|
WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
|
WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
|
WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
|
WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
|
WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
|
|
WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
|
|
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
|
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
//
|
//
|
|
|
|
|
// testing trigger and qualifier
|
// testing trigger and qualifier
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
|
|
|
|
|
|
// Anything starts trigger and qualifier
|
// Anything starts trigger and qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
// End: Anything starts trigger and qualifier //
|
// End: Anything starts trigger and qualifier //
|
|
|
|
|
/* Anything starts trigger, breakpoint starts qualifier
|
/* Anything starts trigger, breakpoint starts qualifier
|
// Uncomment this part when you want to test it.
|
// Uncomment this part when you want to test it.
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
#1 Bp = 1; // Set breakpoint
|
#1 Bp = 1; // Set breakpoint
|
repeat(8) @(posedge Mclk);
|
repeat(8) @(posedge Mclk);
|
wait(dbg_tb.i_dbg_top.dbgTrace1.RiscStall)
|
wait(dbg_tb.i_dbg_top.dbgTrace1.RiscStall)
|
#1 Bp = 0; // Clear breakpoint
|
#1 Bp = 0; // Clear breakpoint
|
// End: Anything starts trigger, breakpoint starts qualifier */
|
// End: Anything starts trigger, breakpoint starts qualifier */
|
|
|
|
|
/* Anything starts qualifier, breakpoint starts trigger
|
/* Anything starts qualifier, breakpoint starts trigger
|
// Uncomment this part when you want to test it.
|
// Uncomment this part when you want to test it.
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
@ (posedge Mclk)
|
@ (posedge Mclk)
|
Wp[4] = 1; // Set watchpoint[4]
|
Wp[4] = 1; // Set watchpoint[4]
|
LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
|
LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
|
@ (posedge Mclk)
|
@ (posedge Mclk)
|
Wp[4] = 0; // Clear watchpoint[4]
|
Wp[4] = 0; // Clear watchpoint[4]
|
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
|
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
|
// End: Anything starts trigger and qualifier */
|
// End: Anything starts trigger and qualifier */
|
|
|
|
|
|
|
|
|
|
|
|
|
// Reading data from the trace buffer
|
// Reading data from the trace buffer
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
|
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
|
|
|
|
`endif // TRACE_ENABLED
|
`endif // TRACE_ENABLED
|
|
|
|
|
|
|
|
|
#5000 GenClk(1); // One extra TCLK for debugging purposes
|
#5000 GenClk(1); // One extra TCLK for debugging purposes
|
#1000 $stop;
|
#1000 $stop;
|
|
|
end
|
end
|
join
|
join
|
|
|
|
|
// Generation of the TCLK signal
|
// Generation of the TCLK signal
|
task GenClk;
|
task GenClk;
|
input [7:0] Number;
|
input [7:0] Number;
|
integer i;
|
integer i;
|
begin
|
begin
|
for(i=0; i<Number; i=i+1)
|
for(i=0; i<Number; i=i+1)
|
begin
|
begin
|
#Tclk P_TCK<=1;
|
#Tclk P_TCK<=1;
|
#Tclk P_TCK<=0;
|
#Tclk P_TCK<=0;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// TAP reset
|
// TAP reset
|
task ResetTAP;
|
task ResetTAP;
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(7);
|
GenClk(7);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Goes to RunTestIdle state
|
// Goes to RunTestIdle state
|
task GotoRunTestIdle;
|
task GotoRunTestIdle;
|
begin
|
begin
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// sets the instruction to the IR register and goes to the RunTestIdle state
|
// sets the instruction to the IR register and goes to the RunTestIdle state
|
task SetInstruction;
|
task SetInstruction;
|
input [3:0] Instr;
|
input [3:0] Instr;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(2);
|
GenClk(2);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftIR
|
GenClk(2); // we are in shiftIR
|
|
|
for(i=0; i<`IR_LENGTH-1; i=i+1)
|
for(i=0; i<`IR_LENGTH-1; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Instr[i];
|
P_TDI<=#Tp Instr[i];
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
P_TDI<=#Tp Instr[i]; // last shift
|
P_TDI<=#Tp Instr[i]; // last shift
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // tri-state
|
P_TDI<=#Tp 'hz; // tri-state
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// sets the selected scan chain and goes to the RunTestIdle state
|
// sets the selected scan chain and goes to the RunTestIdle state
|
task ChainSelect;
|
task ChainSelect;
|
input [3:0] Data;
|
input [3:0] Data;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
|
for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Data[i];
|
P_TDI<=#Tp Data[i];
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
for(i=0; i<`CRC_LENGTH; i=i+1) // +1 because crc is 9 bit long
|
for(i=0; i<`CRC_LENGTH; i=i+1) // +1 because crc is 9 bit long
|
begin
|
begin
|
P_TDI<=#Tp Crc[i];
|
P_TDI<=#Tp Crc[i];
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// P_TDI<=#Tp Crc[i]; // last shift
|
// P_TDI<=#Tp Crc[i]; // last shift
|
P_TDI<=#Tp 1'b0; // Crc[i]; // last shift
|
P_TDI<=#Tp 1'b0; // Crc[i]; // last shift
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // tri-state
|
P_TDI<=#Tp 'hz; // tri-state
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Reads the ID code
|
// Reads the ID code
|
task ReadIDCode;
|
task ReadIDCode;
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
P_TDI<=#Tp 0;
|
P_TDI<=#Tp 0;
|
GenClk(31);
|
GenClk(31);
|
|
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
|
|
P_TDI<=#Tp 'hz; // tri-state
|
P_TDI<=#Tp 'hz; // tri-state
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Reads sample from the Trace Buffer
|
// Reads sample from the Trace Buffer
|
task ReadTraceBuffer;
|
task ReadTraceBuffer;
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
P_TDI<=#Tp 0;
|
P_TDI<=#Tp 0;
|
GenClk(47);
|
GenClk(47);
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // tri-state
|
P_TDI<=#Tp 'hz; // tri-state
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Reads the RISC register and latches the data so it is ready for reading
|
// Reads the RISC register and latches the data so it is ready for reading
|
task ReadRISCRegister;
|
task ReadRISCRegister;
|
input [31:0] Address;
|
input [31:0] Address;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Address[i]; // Shifting address
|
P_TDI<=#Tp Address[i]; // Shifting address
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
P_TDI<=#Tp 0; // shifting RW bit = read
|
P_TDI<=#Tp 0; // shifting RW bit = read
|
GenClk(1);
|
GenClk(1);
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
|
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
begin
|
begin
|
P_TDI<=#Tp Crc[i]; // Shifting CRC.
|
P_TDI<=#Tp Crc[i]; // Shifting CRC.
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC.
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC.
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // Tristate TDI.
|
P_TDI<=#Tp 'hz; // Tristate TDI.
|
GenClk(1);
|
GenClk(1);
|
|
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Write the RISC register
|
// Write the RISC register
|
task WriteRISCRegister;
|
task WriteRISCRegister;
|
input [31:0] Data;
|
input [31:0] Data;
|
input [31:0] Address;
|
input [31:0] Address;
|
input [`CRC_LENGTH-1:0] Crc;
|
input [`CRC_LENGTH-1:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Address[i]; // Shifting address
|
P_TDI<=#Tp Address[i]; // Shifting address
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
P_TDI<=#Tp 1; // shifting RW bit = write
|
P_TDI<=#Tp 1; // shifting RW bit = write
|
GenClk(1);
|
GenClk(1);
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Data[i]; // Shifting data
|
P_TDI<=#Tp Data[i]; // Shifting data
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
begin
|
begin
|
P_TDI<=#Tp Crc[i]; // Shifting CRC
|
P_TDI<=#Tp Crc[i]; // Shifting CRC
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// P_TDI<=#Tp Crc[i]; // shifting last bit of CRC
|
// P_TDI<=#Tp Crc[i]; // shifting last bit of CRC
|
P_TDI<=#Tp 1'b0; // Crc[i]; // shifting last bit of CRC
|
P_TDI<=#Tp 1'b0; // Crc[i]; // shifting last bit of CRC
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // tristate TDI
|
P_TDI<=#Tp 'hz; // tristate TDI
|
GenClk(1);
|
GenClk(1);
|
|
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
|
|
GenClk(10); // Generating few clock cycles needed for the write operation to accomplish
|
GenClk(10); // Generating few clock cycles needed for the write operation to accomplish
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Reads the register and latches the data so it is ready for reading
|
// Reads the register and latches the data so it is ready for reading
|
task ReadRegister;
|
task ReadRegister;
|
input [4:0] Address;
|
input [4:0] Address;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
for(i=0; i<5; i=i+1)
|
for(i=0; i<5; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Address[i]; // Shifting address
|
P_TDI<=#Tp Address[i]; // Shifting address
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
P_TDI<=#Tp 0; // shifting RW bit = read
|
P_TDI<=#Tp 0; // shifting RW bit = read
|
GenClk(1);
|
GenClk(1);
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
|
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
begin
|
begin
|
P_TDI<=#Tp Crc[i]; // Shifting CRC. CRC is not important in read cycle.
|
P_TDI<=#Tp Crc[i]; // Shifting CRC. CRC is not important in read cycle.
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC.
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC.
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // Tri state TDI
|
P_TDI<=#Tp 'hz; // Tri state TDI
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
|
|
GenClk(10); // Generating few clock cycles needed for the read operation to accomplish
|
GenClk(10); // Generating few clock cycles needed for the read operation to accomplish
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Write the register
|
// Write the register
|
task WriteRegister;
|
task WriteRegister;
|
input [31:0] Data;
|
input [31:0] Data;
|
input [4:0] Address;
|
input [4:0] Address;
|
input [`CRC_LENGTH-1:0] Crc;
|
input [`CRC_LENGTH-1:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
for(i=0; i<5; i=i+1)
|
for(i=0; i<5; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Address[i]; // Shifting address
|
P_TDI<=#Tp Address[i]; // Shifting address
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
P_TDI<=#Tp 1; // shifting RW bit = write
|
P_TDI<=#Tp 1; // shifting RW bit = write
|
GenClk(1);
|
GenClk(1);
|
|
|
for(i=0; i<32; i=i+1)
|
for(i=0; i<32; i=i+1)
|
begin
|
begin
|
P_TDI<=#Tp Data[i]; // Shifting data
|
P_TDI<=#Tp Data[i]; // Shifting data
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
// for(i=0; i<`CRC_LENGTH-1; i=i+1)
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
for(i=0; i<`CRC_LENGTH; i=i+1) // crc is 9 bit long
|
begin
|
begin
|
P_TDI<=#Tp Crc[i]; // Shifting CRC
|
P_TDI<=#Tp Crc[i]; // Shifting CRC
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
|
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC
|
// P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC
|
P_TDI<=#Tp 1'b0; // Crc[i]; // Shifting last bit of CRC
|
P_TMS<=#Tp 1; // going out of shiftIR
|
P_TMS<=#Tp 1; // going out of shiftIR
|
GenClk(1);
|
GenClk(1);
|
P_TDI<=#Tp 'hz; // Tri state TDI
|
P_TDI<=#Tp 'hz; // Tri state TDI
|
GenClk(1);
|
GenClk(1);
|
|
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
|
|
GenClk(5); // Extra clocks needed for operations to finish
|
GenClk(5); // Extra clocks needed for operations to finish
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task EnableWishboneSlave;
|
task EnableWishboneSlave;
|
begin
|
begin
|
while(1)
|
while(1)
|
begin
|
begin
|
if(wb_stb_i & wb_cyc_i) // WB access
|
if(wb_stb_i & wb_cyc_i) // WB access
|
// wait (wb_stb_i & wb_cyc_i) // WB access
|
// wait (wb_stb_i & wb_cyc_i) // WB access
|
begin
|
begin
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
#1 wb_ack_o = 1;
|
#1 wb_ack_o = 1;
|
if(~wb_we_i) // read
|
if(~wb_we_i) // read
|
wb_dat_o = 32'hbeefdead;
|
wb_dat_o = 32'hbeefdead;
|
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
|
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
|
$display("\nWISHBONE write Data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
|
$display("\nWISHBONE write Data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
|
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
|
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
|
$display("\nWISHBONE read Data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
|
$display("\nWISHBONE read Data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
|
end
|
end
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
#1 wb_ack_o = 0;
|
#1 wb_ack_o = 0;
|
wb_dat_o = 32'h0;
|
wb_dat_o = 32'h0;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Printing the information to the screen *
|
* Printing the information to the screen *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
// Print samples that are recorded to the trace buffer
|
// Print samples that are recorded to the trace buffer
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_dbg_top.dbgTrace1.WriteSample)
|
if(dbg_tb.i_dbg_top.dbgTrace1.WriteSample)
|
$write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.i_dbg_top.dbgTrace1.WritePointer, {dbg_tb.i_dbg_top.dbgTrace1.DataIn, 1'b0, dbg_tb.i_dbg_top.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
|
$write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.i_dbg_top.dbgTrace1.WritePointer, {dbg_tb.i_dbg_top.dbgTrace1.DataIn, 1'b0, dbg_tb.i_dbg_top.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// Print selected instruction
|
// Print selected instruction
|
reg UpdateIR_q;
|
reg UpdateIR_q;
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
UpdateIR_q<=#Tp dbg_tb.i_tap_top.UpdateIR;
|
UpdateIR_q<=#Tp dbg_tb.i_tap_top.UpdateIR;
|
end
|
end
|
|
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(UpdateIR_q)
|
if(UpdateIR_q)
|
case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
|
case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
|
`EXTEST : $write("\n\tInstruction EXTEST");
|
`EXTEST : $write("\n\tInstruction EXTEST");
|
`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
|
`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
|
`IDCODE : $write("\n\tInstruction IDCODE");
|
`IDCODE : $write("\n\tInstruction IDCODE");
|
`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
|
`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
|
`INTEST : $write("\n\tInstruction INTEST");
|
`INTEST : $write("\n\tInstruction INTEST");
|
`CLAMP : $write("\n\tInstruction CLAMP");
|
`CLAMP : $write("\n\tInstruction CLAMP");
|
`CLAMPZ : $write("\n\tInstruction CLAMPZ");
|
`CLAMPZ : $write("\n\tInstruction CLAMPZ");
|
`HIGHZ : $write("\n\tInstruction HIGHZ");
|
`HIGHZ : $write("\n\tInstruction HIGHZ");
|
`DEBUG : $write("\n\tInstruction DEBUG");
|
`DEBUG : $write("\n\tInstruction DEBUG");
|
`BYPASS : $write("\n\tInstruction BYPASS");
|
`BYPASS : $write("\n\tInstruction BYPASS");
|
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
// Print selected chain
|
// Print selected chain
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
|
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
|
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
|
`RISC_DEBUG_CHAIN : $write("\nChain RISC_DEBUG_CHAIN");
|
`RISC_DEBUG_CHAIN : $write("\nChain RISC_DEBUG_CHAIN");
|
`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
|
`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
|
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
|
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
|
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
|
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// print RISC registers read/write
|
// print RISC registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_dbg_top.RISCAccess & ~dbg_tb.i_dbg_top.RISCAccess_q & dbg_tb.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RISCAccess & ~dbg_tb.i_dbg_top.RISCAccess_q & dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
else
|
else
|
if(dbg_tb.i_dbg_top.RISCAccess_q & ~dbg_tb.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RISCAccess_q & ~dbg_tb.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.risc_data_i[31:0]);
|
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.risc_data_i[31:0]);
|
end
|
end
|
|
|
|
|
// print registers read/write
|
// print registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_dbg_top.RegAccess_q & ~dbg_tb.i_dbg_top.RegAccess_q2)
|
if(dbg_tb.i_dbg_top.RegAccess_q & ~dbg_tb.i_dbg_top.RegAccess_q2)
|
begin
|
begin
|
if(dbg_tb.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
else
|
else
|
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.RegDataIn[31:0]);
|
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.RegDataIn[31:0]);
|
end
|
end
|
end
|
end
|
|
|
|
|
// print CRC error
|
// print CRC error
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RiscDebugScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RiscDebugScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.WishboneScanChain));
|
`else // TRACE_ENABLED not enabled
|
`else // TRACE_ENABLED not enabled
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
`endif
|
`endif
|
|
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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else
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else
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if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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else
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else
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if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
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if(CRCErrorReport)
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if(CRCErrorReport)
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begin
|
begin
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$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
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$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
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#1000 $stop;
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#1000 $stop;
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end
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end
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end
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end
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end
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end
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// Print shifted IDCode
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// Print shifted IDCode
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reg [31:0] TempData;
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reg [31:0] TempData;
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always @ (posedge P_TCK)
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always @ (posedge P_TCK)
|
begin
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begin
|
if(dbg_tb.i_tap_top.IDCODESelected)
|
if(dbg_tb.i_tap_top.IDCODESelected)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.ShiftDR)
|
if(dbg_tb.i_tap_top.ShiftDR)
|
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
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TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
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else
|
else
|
if(dbg_tb.i_tap_top.UpdateDR)
|
if(dbg_tb.i_tap_top.UpdateDR)
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
end
|
end
|
end
|
end
|
|
|
|
|
// Print data from the trace buffer
|
// Print data from the trace buffer
|
reg [47:0] TraceData;
|
reg [47:0] TraceData;
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.DEBUGSelected & (dbg_tb.i_dbg_top.Chain==`TRACE_TEST_CHAIN))
|
if(dbg_tb.i_tap_top.DEBUGSelected & (dbg_tb.i_dbg_top.Chain==`TRACE_TEST_CHAIN))
|
begin
|
begin
|
if(dbg_tb.i_tap_top.ShiftDR)
|
if(dbg_tb.i_tap_top.ShiftDR)
|
TraceData[47:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TraceData[47:1]};
|
TraceData[47:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TraceData[47:1]};
|
else
|
else
|
if(dbg_tb.i_tap_top.UpdateDR)
|
if(dbg_tb.i_tap_top.UpdateDR)
|
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule // TB
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endmodule // TB
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