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SoC Debug Interface
Author: Igor Mohor
IgorM@opencores.org
Rev. 2.1
March 14, 2004
Copyright (C) 2001 - 2004 OPENCORES.ORG and Authors.
This document is free; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
Revision History
Rev.DateAuthorDescription0.102/02/01Igor MohorFirst Draft0.205/04/01IMTrace port added0.316/04/01IMWP and BP number changed, trace modified0.401/05/01IMTitle changed, DEBUG instruction added, scan chains changed, IO ports changed 0.505/05/01IMTSEL and QSEL register changed0.606/05/01IMPorts connected to the OpenRISC changed0.714/05/01IMMODER register changed, trace scan chain changed; SSEL register added0.818/05/01IMRESET bit and signal added; STALLR changed to RISCOP0.923/05/01IMRISC changed to OpenRISC; WISHBONE interface added, SPR and memory access added0.1001/06/01IMMeaning of Instruction status and Load/store status changed in all registers; more details added to Appendix A 0.1110/09/01IMRegister and OpenRISC scan chain operation changed1.019/09/01IMSome registers deleted1.115/10/01IMWISHBONE interface added; RISC Stall signal is set by breakpoint and reset by writing 0 to RISCOP register1.203/12/01IMChain length changed so additional CRC checking can be performed 1.321/01/02Jeanne WiegelmannDocument revised. 1.407/05/02IMRegister MONCNTL added. 1.510/10/02IMWISHBONE Scan Chain changed to show state of the access. 1.606/11/02IMTRST_PAD_I changed from active low signal to active low signal.1.723/09/03Simon SrotMultiple CPU support added, WB 16-bit and 8-bit access possible through WBCNTL register use.2.001/02/04IMNew version of debug interface. Document name changed, Document split into two documents, one for TAP and one for debug.2.114/03/04IMMissing things added to the documents.
Contents
TOC \o "1-4" \h \z HYPERLINK \l "_Toc67050066" 1 PAGEREF _Toc67050066 \h 7
HYPERLINK \l "_Toc67050067" Introduction PAGEREF _Toc67050067 \h 7
HYPERLINK \l "_Toc67050068" 2 PAGEREF _Toc67050068 \h 8
HYPERLINK \l "_Toc67050069" IO Ports PAGEREF _Toc67050069 \h 8
HYPERLINK \l "_Toc67050070" 2.1 TAP Ports PAGEREF _Toc67050070 \h 8
HYPERLINK \l "_Toc67050071" 2.2 CPU Ports PAGEREF _Toc67050071 \h 9
HYPERLINK \l "_Toc67050072" 2.3 WISHBONE Ports PAGEREF _Toc67050072 \h 9
HYPERLINK \l "_Toc67050073" 3 PAGEREF _Toc67050073 \h 11
HYPERLINK \l "_Toc67050074" Registers PAGEREF _Toc67050074 \h 11
HYPERLINK \l "_Toc67050075" 3.1 CPU Registers List PAGEREF _Toc67050075 \h 11
HYPERLINK \l "_Toc67050076" 3.2 CPU Operation Register PAGEREF _Toc67050076 \h 12
HYPERLINK \l "_Toc67050077" 3.3 CPU Select Register PAGEREF _Toc67050077 \h 13
HYPERLINK \l "_Toc67050078" 4 PAGEREF _Toc67050078 \h 14
HYPERLINK \l "_Toc67050079" Operation PAGEREF _Toc67050079 \h 14
HYPERLINK \l "_Toc67050080" 4.1 Chain Selection PAGEREF _Toc67050080 \h 14
HYPERLINK \l "_Toc67050081" 4.2 WISHBONE Sub-module PAGEREF _Toc67050081 \h 16
HYPERLINK \l "_Toc67050082" 4.2.1 WISHBONE Read operation PAGEREF _Toc67050082 \h 17
HYPERLINK \l "_Toc67050083" 4.2.2 WISHBONE Write operation PAGEREF _Toc67050083 \h 18
HYPERLINK \l "_Toc67050084" 4.2.3 READx/WRITEx instruction PAGEREF _Toc67050084 \h 19
HYPERLINK \l "_Toc67050085" 4.2.4 GO instruction PAGEREF _Toc67050085 \h 21
HYPERLINK \l "_Toc67050086" 4.2.4.1 GO with READx requested PAGEREF _Toc67050086 \h 21
HYPERLINK \l "_Toc67050087" 4.2.4.2 GO with WRITEx requested PAGEREF _Toc67050087 \h 23
HYPERLINK \l "_Toc67050088" 4.2.5 STATUS instruction PAGEREF _Toc67050088 \h 25
HYPERLINK \l "_Toc67050089" 4.2.6 Data and select signals PAGEREF _Toc67050089 \h 28
HYPERLINK \l "_Toc67050090" 4.2.7 Accessing slow devices PAGEREF _Toc67050090 \h 29
HYPERLINK \l "_Toc67050091" 4.2.7.1 Reading from slow device PAGEREF _Toc67050091 \h 29
HYPERLINK \l "_Toc67050092" 4.2.7.2 Writing to slow device PAGEREF _Toc67050092 \h 30
HYPERLINK \l "_Toc67050093" 4.2.8 Error and retry on the WISHBONE PAGEREF _Toc67050093 \h 31
HYPERLINK \l "_Toc67050094" 4.3 CPU Sub-module PAGEREF _Toc67050094 \h 32
HYPERLINK \l "_Toc67050095" 4.3.1 CPU Register Read operation PAGEREF _Toc67050095 \h 34
HYPERLINK \l "_Toc67050096" 4.3.2 CPU Register Write operation PAGEREF _Toc67050096 \h 35
HYPERLINK \l "_Toc67050097" 4.3.3 CPU Read operation PAGEREF _Toc67050097 \h 36
HYPERLINK \l "_Toc67050098" 4.3.4 CPU Write operation PAGEREF _Toc67050098 \h 37
HYPERLINK \l "_Toc67050099" 4.3.5 CPU_READx/CPU_WRITEx operation PAGEREF _Toc67050099 \h 38
HYPERLINK \l "_Toc67050100" 4.3.6 GO instruction PAGEREF _Toc67050100 \h 40
HYPERLINK \l "_Toc67050101" 4.3.6.1 GO with CPU_READx requested PAGEREF _Toc67050101 \h 40
HYPERLINK \l "_Toc67050102" 4.3.6.2 GO with CPU_WRITEx requested PAGEREF _Toc67050102 \h 42
HYPERLINK \l "_Toc67050103" 4.3.7 Selecting different CPUs PAGEREF _Toc67050103 \h 44
HYPERLINK \l "_Toc67050104" 4.3.8 Stalling CPU(s) PAGEREF _Toc67050104 \h 44
HYPERLINK \l "_Toc67050105" 4.3.9 Resetting CPUs PAGEREF _Toc67050105 \h 45
HYPERLINK \l "_Toc67050106" 5 PAGEREF _Toc67050106 \h 46
HYPERLINK \l "_Toc67050107" Architecture PAGEREF _Toc67050107 \h 46
HYPERLINK \l "_Toc67050108" 5.1 Debug Interface PAGEREF _Toc67050108 \h 48
HYPERLINK \l "_Toc67050109" 5.2 CRC sub-module PAGEREF _Toc67050109 \h 48
HYPERLINK \l "_Toc67050110" 5.3 WISHBONE sub-module PAGEREF _Toc67050110 \h 49
Introduction
The Development Interface is used for debugging purposes and is as such an interface between the processor(s), peripheral cores, and any commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a fully IEEE 1149.1 compatible JTAG TAP port that is not part of this core. TAP is available at the opencores, too (look for project JTAG Test Access Port (TAP)).
IO Ports
2.1 TAP Ports
Debug interface connects to the TAP controller with the following signals:
PortWidth DirectionDescriptiontck_i1inputTest clock inputtdi_i1inputTest data inputtdo_o1outputTest data outputshift_dr_i1inputTAP controller state Shift DRpause_dr_i1inputTAP controller state Pause DRupdate_dr_i1inputTAP controller state Update DRdebug_select_i1inputInstruction DEBUG is activatedTable SEQ Table \* ARABIC 1: TAP Ports
2.2 CPU Ports
Port Width DirectionDescriptioncpu_clk_i1inputCPU clock signal.cpu_addr_o32outputCPU addresscpu_data_i32inputCPU data input (data from CPU)cpu_data_o32outputCPU data output (data to CPU)cpu_bp_i1inputCPU breakpointcpu_stall_o1outputCPU stall (selected CPU is stalled)cpu_stall_all_o1outputCPU stall all (all unselected CPUs are stalled)cpu_stb_o1outputCPU strobecpu_sel_o8outputCPU select signals (one hot), select the CPUcpu_we_o1outputCPU write enable signal indicates a write cycle when asserted high (read cycle when low).cpu_ack_i1inputCPU acknowledge (signals end of cycle)cpu_rst_o1outputCPU reset output (resets CPU)Table SEQ Table \* ARABIC 2: CPU Ports
2.3 WISHBONE Ports
Port Width DirectionDescriptionwb_clk_i1inputWISHBONE clockwb_rst_i1inputWISHBONE resetwb_ack_i1inputWISHBONE acknowledge indicates a normal cycle terminationwb_adr_o32outputWISHBONE address outputwb_cyc_o1outputWISHBONE cycle encapsulates a valid transfer cycle.wb_dat_i32inputWISHBONE data input (data from WISHBONE)wb_dat_o32outputWISHBONE data output (data to WISHBONE)wb_err_i1inputWISHBONE error acknowledge indicates an abnormal cycle terminationwb_sel_o4outputWISHBONE select indicates which bytes are valid on the data bus. wb_stb_o1outputWISHBONE strobe indicates a valid transfer.wb_we_o1outputWISHBONE write enable indicates a write cycle when asserted high (read cycle when low).wb_cab_o1outputWISHBONE consecutive address burst indicates a burst cycle.wb_cti_o3outputWISHBONE cycle type identifier indicates type of cycle (single, burst, end of burst)wb_bte_o2outputWISHBONE burst type extensionTable SEQ Table \* ARABIC 3: WISHBONE Ports
Registers
This section specifies all registers in the Debug Interface. There are currently two sub-modules in the debug interface, WISHBONE and CPU.
WISHBONE sub-module doesnt have internal registers.
CPU sub-module does have internal registers and they are described in the following section.
3.1 CPU Registers List
Name Address Width AccessDescriptionCPU_OP0x08R/WCPU Operation RegisterCPU_SEL0x18R/WCPU Select Register
Table SEQ Table \* ARABIC 4: CPU Register List
3.2 CPU Operation Register
Bit #AccessDescription7:3Reserved2R/WCPUSTALLALL Stall all unselected CPUs
0 = normal operation
1 = Stall all unselected CPUs1R/WRESET Reset CPU
0 = normal
1 = reset0R/WCPUSTALL CPU Stall
0 = normal operation
1 = Stall CPU. CPU can also set this bit by inserting the cpu_bp_i signal.Table SEQ Table \* ARABIC 5: CPU_OP Register
Reset Value:
CPU_OP: 00h
3.3 CPU Select Register
Bit # AccessDescription7:0R/WCPUSEL Select one CPU
00000001b = Selects CPU 0 (cpu_sel_o [0] is active)
00000010b = Selects CPU 1 (cpu_sel_o [1] is active)
00000100b = Selects CPU 2 (cpu_sel_o [2] is active)
00001000b = Selects CPU 3 (cpu_sel_o [3] is active)
00010000b = Selects CPU 4 (cpu_sel_o [4] is active)
00100000b = Selects CPU 5 (cpu_sel_o [5] is active)
01000000b = Selects CPU 6 (cpu_sel_o [6] is active)
10000000b = Selects CPU 7 (cpu_sel_o [7] is active)
00000000b = NO CPU selected (cpu_sel_o [7:0] not active)Table SEQ Table \* ARABIC 6: CPU_SEL Register
Reset Value:
CPU_SEL: 00h
Operation
This section describes the operation of the Debug Interface and its sub-modules.
4.1 Chain Selection
The debug interface is just an interface between the sub-module that is target specific and the TAP controller. Currently two sub-modules are connected to the debug interface, WISHBONE sub-module and CPU sub-module. Up to 8 sub-modules can be connected to the debug interface.
First thing to do is to select the sub-module. This is done with the chain select instruction. Following needs to be done prior to the chain select operation:
instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)
Then the chain select instruction needs to be shifted-in through the TAP data chain:
1-bit with value 1 (This bit is treated as a chain select)
3-bit chain ID (LSB shifted first)
32-bit CRC (MSB shifted first) that is protecting the incoming data (first four bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the chain select instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
1 if command was chain select, else 0
1 if non-existing chain was selected, else 0
always 1
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 36 bits are ignored).
SHAPE \* MERGEFORMAT
Figure SEQ Figure \* ARABIC 1: Chain Selection
See section REF _Ref63228021 \h 5.2 CRC sub-module on page PAGEREF _Ref63228021 \h 48 for more details about the CRC.
4.2 WISHBONE Sub-module
There are three types of instruction in the WISHBONE sub-module (see REF _Ref66710201 \h \* MERGEFORMAT
Table 7: WISHBONE sub-module: Supported Instructions REF _Ref66710201 \p \h below for more details):
READx/WRITEx instructions
GO instruction
STATUS instruction
The following table describes all supported instructions and their codes:
InstructionCodeMeaningSTATUS000Reads the status of the previous command(s)WRITE8001Requests write of the 8-bit dataWRITE16010Requests write of the 16-bit dataWRITE32011Requests write of the 32-bit dataGO100Performs the requested instructionREAD8101Requests read of the 8-bit dataREAD16110Requests read of the 16-bit dataREAD32111Requests read of the 32-bit data
Table SEQ Table \* ARABIC 7: WISHBONE sub-module: Supported Instructions
All WISHBONE operations (except STATUS) consist of two consequent instructions. First instruction is the READx/WRITEx instruction. It sets the address, type of instruction (read or write) and length of data that is read or written. Second instruction is the GO instruction that actually does what the first instruction requests. Following section describes how read, write or status operations are performed.
Note: Before some data can be read from or written to the WISHBONE, the following needs to be done:
instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)
WISHBONE sub-module needs to be selected (refer to section REF _Ref63237097 \h 4.1 Chain Selection on page PAGEREF _Ref63237097 \h 14 for more details)
4.2.1 WISHBONE Read operation
To perform the WISHBONE read operation, the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the WISHBONE sub-module selected (see description on page PAGEREF _Ref63237097 \h 14 for more details).
Read operation is performed in two steps:
Issuing the READx instruction (see section REF _Ref67050293 \h 4.2.3 READx/WRITEx instruction on page PAGEREF _Ref67050304 \h 19 for more details)
Issuing the GO instruction (see section REF _Ref66768261 \h 4.2.4.1 GO with READx requested on page PAGEREF _Ref66768261 \h 21 for more details)
First instruction sets the address, type of operation and data length that needs to be read.
Second instruction performs the read operation on the WISHBONE bus.
Both instructions (READx and GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully. However it is also possible to check the status after the operation by issuing the STATUS instruction. Go to the section REF _Ref66775180 \h 4.2.5 STATUS instruction on page PAGEREF _Ref66775194 \h 25 for more information about the STATUS.
Whenever an error occurs, both steps (READx and GO) need to be repeated.
4.2.2 WISHBONE Write operation
To perform the WISHBONE write operation, the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the WISHBONE sub-module selected (see description on page PAGEREF _Ref63237097 \h 14 for more details).
Write operation is performed in two steps:
Issuing the WRITEx instruction (see section REF _Ref67050369 \h 4.2.3 READx/WRITEx instruction on page PAGEREF _Ref67050381 \h 19 for more details)
Issuing the GO instruction (see section REF _Ref66768668 \h 4.2.4.2 GO with WRITEx requested on page PAGEREF _Ref66768668 \h 23 for more details)
First instruction sets the address, type of operation and data length that needs to be written.
Second instruction performs the write operation on the WISHBONE bus.
Both instructions (WRITEx and GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully. However it is also possible to check the status after the operation by issuing the STATUS instruction. Go to the section REF _Ref66775180 \h 4.2.5 STATUS instruction on page PAGEREF _Ref66775194 \h 25 for more information about the STATUS.
Whenever an error occurs, both steps (WRITEx and GO) need to be repeated.
4.2.3 READx/WRITEx instruction
Read/write instruction sets the address, the type of operation and the length of the data that will be read or written. It is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction (READ8, READ16, READ32, WRITE8, WRITE16 or WRITE32, depending on the cycle type (read or write) and the data width (8-bit, 16-bit or 32-bit))
32-bit address
16-bit length (describes data length in bytes)
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 52 bits).
36 bits with value 0 (this value is ignored in the debug interface)
While the read/write instruction is shifted-in, the following data is shifted out:
84 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s of 0
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 84 bits are ignored).
Figure SEQ Figure \* ARABIC 2: READx/WRITEx instruction
4.2.4 GO instruction
GO instruction actually performs the instruction that was requested with the previous READx/WRITEx instruction. The structure of the GO instruction differs depending on the previous requested instruction. There are two possibilities:
READx instruction was previously requested
WRITEx instruction was previously requested
4.2.4.1 GO with READx requested
GO instruction with READx previously requested performs the read operation on the WISHBONE bus. Address, cycle type and data length are specified with the READx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
(data length x 8) bits with value 0 (this value is ignored in the debug interface). Number x is number of bits that are read out.
While the GO instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
(data length x 8) bits of data
4-bit status
1 if incoming CRC is OK, else 0
1 if WISHBONE cycle didnt finish (still in progress), else 0. This is important only for the first data byte
1 if under run occurred (data couldnt be read fast enough), else 0
1 if WISHBONE error occurred
32-bit CRC (MSB shifted first) that is protecting the outgoing data (data length x 8 + 4 bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 3: GO with READx requested
4.2.4.2 GO with WRITEx requested
GO instruction with WRITEx previously requested performs the write operation on the WISHBONE bus. Address, cycle type and data length are specified with the WRITEx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
(data length x 8) bits of data
32-bit CRC (MSB shifted first) that is protecting the incoming data (first data length x 8 + 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the GO instruction is shifted-in, the following data is shifted out:
(length x 8 + 36) bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
1 if WISHBONE cycle didnt finish (still in progress), else 0. This is important only for the first data byte
1 if overrun occurred (data couldnt be write fast enough), else 0
1 if WISHBONE error occurred
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first length x 8 + 36 bits are ignored).
Figure SEQ Figure \* ARABIC 4: GO with WRITEx requested
4.2.5 STATUS instruction
STATUS instruction is used for reading the value of the status register. Status register consists of four bits. The MSB bit is always shifted out first. The meaning of the bits is described in the following table.
Status bit #Meaning30 = Incoming CRC error
1 = Incoming CRC OK20 = WISHBONE cycle finished
1 = WISHBONE cycle not finished10 = no overrun/underrun
1 = overrun/underrun occurred00 = No WISHBONE error
1= WISHBONE error occurred
Table SEQ Table \* ARABIC 8: Status bit description
Bit 0 is set when at least one WISHBONE error occurred since the last STATUS instruction was performed. Once set, it can be cleared only with the STATUS instruction.
Bit 1 is set when at least one underrun (for read operation) or overrun (for write) happened since the last STATUS instruction was performed. Underrun is when data is not available for reading on time. Overrun is when data is not written to the device on time (new data arrives before the previous data is written). Once set, it can be cleared only with the STATUS instruction.
Bit 2 is set while the WISHBONE cycle is in progress (not finished, yet). Go to section REF _Ref66969966 \h 4.2.7 Accessing slow devices on page PAGEREF _Ref66969966 \h 29 to read how to access data from slow devices. This bit changes when the access is finished (is not latched).
Bit 3 is cleared to zero when the CRC error occurs while shifting the data into the debug interface. This bit is valid only for the last instruction. STATUS instruction does not change the value of this bit.
The STATUS instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction STATUS
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the STATUS instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
4-bit status (see REF _Ref66767365 \h Table 8 REF _Ref66767373 \p \h above for more details)
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 5: STATUS Instruction
4.2.6 Data and select signals
Data in the WISHBONE sub-module is organized in the big endian byte ordering. Following section describes the data and select signals depending on the address and type of operation (32-bit, 16-bit and 8-bit).
32-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1111b
wb_dat_x[31:0] are used
16-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1100b
wb_dat_x[31:16] are used
16-bit access (wb_adr_o[1:0] = 10b):
wb_sel_o[3:0] = 0011b
wb_dat_x[15:0] are used
8-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1000b
wb_dat_x[31:24] are used
8-bit access (wb_adr_o[1:0] = 01b):
wb_sel_o[3:0] = 0100b
wb_dat_x[23:16] are used
8-bit access (wb_adr_o[1:0] = 10b):
wb_sel_o[3:0] = 0010b
wb_dat_x[15:8] are used
8-bit access (wb_adr_o[1:0] = 11b):
wb_sel_o[3:0] = 0001b
wb_dat_x[7:0] are used
4.2.7 Accessing slow devices
Usually the WISHBONE clock (wb_clk_i) is much slower than the JTAG clock (tck_i). In that case read or write accesses are finished on time. However it is possible to do a read or write access to a WISHBONE device that is not fast enough to complete the desired operation on time.
On time means:
Read operation needs to be finished before the data is shifted out through the JTAG
Write operation must be finished before the next write is started.
4.2.7.1 Reading from slow device
Following needs to be done to read the data from a slow device:
Perform the READx instruction normally
Perform only first part of the GO instruction. After the first 36 bits are shifted out, force TAP state machine to go to the PAUSE_DR state. This means that the tms_i signal needs to be driven high after the 35th bit.
Once in the PAUSE_DR state, tdo_o signal reflects the state of the WISHBONE bus. While bus is busy (read cycle not finished), tdo_o is set to 1. Once the read cycle is finished, tdo_o goes to zero. Loop in the PAUSE_DR state until tdo_o goes to zero. Then go to the SHIFT_DR state and continue like nothing happened. When reading more data, go to the PAUSE_DR state after each word/half/byte is shifted out (depending on the type of access (8, 16 or 32 bit)).
CRC is not calculated when not in the SHIFT_DR state.
Note: TAP state machine is described in the documentation that is part of the project JTAG Test Access Port (TAP) that is available on the opencores website.
4.2.7.2 Writing to slow device
Following needs to be done to write the data to a slow device:
Perform the WRITEx instruction normally.
Perform only part of the GO instruction. After the first 4 bits are shifted in, shift in the first data word/half/byte. Then force the TAP state machine to go to the PAUSE_DR state. This means that the tms_i signal needs to be driven high after the 35th bit for 32-bit access, 19th bit for 16-bit access or 11th bit for 8-bit access.
Once in the PAUSE_DR state, tdo_o signal reflects the state of the WISHBONE bus. While bus is busy (write cycle not finished), tdo_o is set to 1. Once the write cycle is finished, tdo_o goes to zero. Loop in the PAUSE_DR state until tdo_o goes to zero. Then go to the SHIFT_DR state and continue like nothing happened. When writing more data, go to the PAUSE_DR state after each data word/half/byte is shifted in.
Check the busy status also after the last data word/half/byte. Then shift out the status and the CRC
CRC is not calculated when not in the SHIFT_DR state.
Note: TAP state machine is described in the documentation that is part of the project JTAG Test Access Port (TAP) that is available on the opencores website.
4.2.8 Error and retry on the WISHBONE
When a WISHBONE cycle is terminated with an error (signal wb_err_i is set to 1), the status bit [0] is set to 1. This bit remains set until the status is read with the STATUS instruction. This is useful to detect errors that occurred during several consecutive cycles (reading/writing data from/to consecutive addresses).
When the addresses WISHBONE device replies to late to the request, status bit [1] (overrun/underrun) is set. This bit remains set until the status is read with the STATUS instruction. This is useful to detect errors that occurred during several consecutive cycles.
WISHBONE retry function is not supported.
4.3 CPU Sub-module
CPU sub-module is an interface to the CPU debug facilities (that are part of the CPU). It consists of the internal registers and the CPU interface.
The CPU sub-module can access both, internal CPU registers and the CPU interface (CPUs on the other side of the debug interface).
Internal registers are used for:
selecting one of the connected CPUs
resetting the CPU(s)
stalling the selected CPU
stalling all unselected CPUs
Before the CPU sub-module can be accessed, several steps need to be taken:
debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must be selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
The following table describes all supported instructions and their codes.
InstructionCodeMeaningCPU_WRITE8001Requests write of the 8-bit data to the CPU.CPU_WRITE32010Requests write of the 32-bit data to the CPU.CPU_WRITE_REG011Requests write of the 8-bit data to the internal CPU register.CPU_GO100Performs the requested instruction.CPU_READ8101Requests read of the 8-bit data from the CPU.CPU_READ32110Requests read of the 32-bit data from the CPU.CPU_READ_REG111Requests read of the 8-bit data from the internal CPU register.
Table SEQ Table \* ARABIC 9: CPU sub-module: Supported Instructions
4.3.1 CPU Register Read operation
To read the data from the CPU register (internal register that is part of the CPU sub-module), the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the CPU sub-module selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
Read operation is performed in two steps:
Issuing the CPU_READ_REG instruction (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details)
Issuing the CPU_GO instruction (see section REF _Ref67049187 \h 4.3.6.1 GO with CPU_READx requested on page PAGEREF _Ref67049187 \h 40 for more details)
First instruction sets the address of the register. Second instruction performs the read operation to the addressed internal CPU register.
Both instructions (CPU_READ_REG and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_READ_REG and CPU_GO) need to be repeated.
4.3.2 CPU Register Write operation
To write the data from the CPU register (internal register that is part of the CPU sub-module), the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the CPU sub-module selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
Write operation is performed in two steps:
Issuing the CPU_WRITE_REG instruction (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details)
Issuing the CPU_GO instruction (see section REF _Ref67048987 \h 4.3.6.2 GO with CPU_WRITEx requested on page PAGEREF _Ref67048987 \h 42 for more details)
First instruction sets the address of the register. Second instruction performs the write operation to the addressed internal CPU register.
Both instructions (CPU_WRITE_REG and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_WRITE_REG and CPU_GO) need to be repeated.
4.3.3 CPU Read operation
To read the data from the CPU, following needs to be done:
the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details)
CPU must be selected. Selection is made through the write operation to the internal CPU register (See section REF _Ref67049087 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67049104 \h 44 for more details).
Read operation is performed in two steps:
Issuing the CPU_READ8 instruction when 8-bit read is needed or CPU_READ32 instruction when 32-bit read is needed (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details).
Issuing the CPU_GO instruction (see section REF _Ref67049187 \h 4.3.6.1 GO with CPU_READx requested on page PAGEREF _Ref67049187 \h 40 for more details)
First instruction sets the address of the CPU where the data will be read from. Second instruction performs the read operation to the addressed CPU space.
Both instructions (CPU_READ8/32 and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_READ8/32 and CPU_GO) need to be repeated.
4.3.4 CPU Write operation
To write the data to the CPU, following needs to be done:
the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details)
CPU must be selected. Selection is made through the write operation to the internal CPU register (See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44).
Write operation is performed in two steps:
Issuing the CPU_WRITE8 instruction when 8-bit write is needed or CPU_WRITE32 instruction when 32-bit read is needed (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details).
Issuing the CPU_GO instruction (see section REF _Ref67048987 \h 4.3.6.2 GO with CPU_WRITEx requested on page PAGEREF _Ref67048987 \h 42 for more details)
First instruction sets the address of the CPU where the data will be written to. Second instruction performs the write operation to the addressed CPU space.
Both instructions (CPU_WRITE8/32 and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_WRITE8/32 and CPU_GO) need to be repeated.
4.3.5 CPU_READx/CPU_WRITEx operation
CPU_READ8, CPU_READ32, CPU_WRITE8 and CPU_WRITE32 instructions set the address of the CPU where the data that will be read from or written to.
CPU_READ_REG and CPU_WRITE_REG instructions set the address of the internal CPU register (that is part of the CPU sub-module) where the data that will be read from or written to.
All mentioned instructions are performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction (CPU_READ8, CPU_READ32, CPU_READ_REG, CPU_WRITE8, CPU_WRITE32 or CPU_WRITE_REG) depending on the cycle type (32-bit or 8-bit access to the CPU or 8-bit access to the CPU register))
32-bit address
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 36 bits).
36 bits with value 0 (this value is ignored in the debug interface)
While the CPU_READx/CPU_WRITEx instruction is shifted-in, the following data is shifted out:
68 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 68 bits are ignored).
Figure SEQ Figure \* ARABIC 6: CPU_READx/CPU_WRITEx instruction
4.3.6 GO instruction
GO instruction actually performs the instruction that was requested with the previous CPU_READx/CPU_WRITEx instruction. The structure of the GO instruction differs depending on the previous requested instruction. There are two possibilities:
CPU_READx instruction was previously requested
CPU_WRITEx instruction was previously requested
4.3.6.1 GO with CPU_READx requested
GO instruction with CPU_READx previously requested performs the read operation to the:
internal CPU register (that is part of the CPU sub-module)
or
CPU that is connected to the CPU sub-module (CPU must be previously selected. See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44)
Address of the internal CPU register or the location in the CPU is specified with the previous CPU_READx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
x bits with value 0 (this value is ignored in the debug interface). Number x is number of bits that are read out.
36 + 32 for CPU_READ32
36 + 8 for CPU_READ8 or CPU_READ_REG
While the GO instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
x bits of data
x is 32 for CPU_READ32
x is 8 for CPU_READ8 or CPU_READ_REG
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (32(8) + 4 bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 7: GO with CPU_READx requested
4.3.6.2 GO with CPU_WRITEx requested
GO instruction with CPU_WRITEx previously requested performs the write operation to the:
internal CPU register (that is part of the CPU sub-module)
or
CPU that is connected to the CPU sub-module (CPU must be previously selected. See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44)
Address of the internal CPU register or the location in the CPU is specified with the previous CPU_WRITEx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
x bits of data
x is 32 for CPU_READ32
x is 8 for CPU_READ8 or CPU_READ_REG
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 32(8) + 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the GO instruction is shifted-in, the following data is shifted out:
36 + 32(8) bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first 36 + 32(8) bits are ignored).
Figure SEQ Figure \* ARABIC 8: GO with CPU_WRITEx requested
4.3.7 Selecting different CPUs
cpu_sel_o and cpu_stall_all_o signals have been added to the Debug Interface to support more than one CPU. It is meant, that this signals are used to enable multiplexing of all the signals going from/to CPU and Debug Interface (cpu_bp_i, cpu_data_i, cpu_data_o, cpu_addr_o, cpu_stall_o, cpu_ack_i). The multiplexing of signals is not part of the Debug Interface and is the responsibility of the system integrator.
cpu_sel_o signals are controlled from CPU_SEL register and cpu_stall_all_o signal is controlled from CPU_OP register.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
Normally, if just one CPU is connected to the Debug Interface these signals are not necessary and can be ignored.
4.3.8 Stalling CPU(s)
The selected CPU can be stalled in two ways:
By deliberately setting bit CPUSTALL in the CPU_OP register to 1 (see section REF _Ref63271995 \h 3.2 CPU Operation Register on page PAGEREF _Ref63271998 \h 12 for more details). Clearing this bit again restarts the CPU.
An input breakpoint signal (cpu_bp_i) automatically stops the CPU and sets bit 0 of the CPU_OP register to 1. Clearing this bit again restarts the CPU.
When CPUSTALLALL bit is set in the CPU_OP register, all unselected CPUs are stalled.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
For more information about the breakpoint generation refer to the CPU manual (i.e. OpenRISC 1000 System Architecture Manual).
4.3.9 Resetting CPUs
The Debug Interface puts the CPU to reset by setting the RESET bit in the CPU_OP register to 1. Clearing this bit to 0 deactivates the reset signal.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
Architecture
The SoC Debug Interface architecture is based on IEEE Std. 1149.1 Standard Test Access Port and Boundary Scan Architecture. Other signals are added to provide additional flexibility.
The interface consists of several parts (blocks):
Logic that selects one of the connected scan chains (from sub-modules). Currently two sub-modules are available, CPU and WISHBONE.
CRC sub-module that checks incoming data.
CRC sub-module that calculates the CRC for the outgoing data.
WISHBONE sub-module
CPU sub-module
As seen on the following figure, debug interface is just one part of the complete debugging system. For more information about the TAP controller, go to the opencores web site and look for the project JTAG Test Access Port (TAP). There is a complete IP core with test bench and documentation available.
If there are more than 1 CPU in the system, then additional external logic is needed (marked as MUX logic in the REF _Ref63219195 \h Figure 9: Complete system on page PAGEREF _Ref63219195 \h 47). The function of this logic is:
Multiplexes data that comes from CPUs to data that goes to the debug interface.
Defines stall signals that are connected to the CPUs from cpu_stall_o, cpu_stall_all_o and cpu_sel_o signals.
Figure SEQ Figure \* ARABIC 9: Complete system
5.1 Debug Interface
Debug Interface is an interface between the TAP controller and the sub-modules that are target specific (CPU, WISHBONE...). It receives data from the TAP whenever the DEBUG instruction is active (see IEEE 1149.1 Test Access Port documentation).
Data can hold two kinds of instructions:
Chain select instruction
Sub-module instruction
First bit of the instruction is used to distinguish between the chain select instruction (first bit is 1) and the sub-module instruction (first bit is 0).
Chain select instruction is used for selecting/enabling the sub-module.
Sub-module instructions are sub-module specific. Each sub-module can use different instructions. Because of this, it is very easy to add additional sub-modules.
All the data (in both directions) is protected with the 32-bit CRC (see section REF _Ref63228021 \h 5.2 CRC sub-module on page PAGEREF _Ref63228021 \h 48 for more information). Both CRC engines (one for incoming data and one for outgoing data) are located in the debug interface. None of the sub-modules have their own CRC engine.
5.2 CRC sub-module
There are two CRC sub-modules in the debug interface. One is checking the incoming data, while the other is calculating the CRC from the outgoing data.
The following polynomial is used for 32-bit CRC calculation:
1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32
1-bit data input is used for CRC calculation. CRC is initialized to the value 0xffffffff before the actual CRC calculation starts. The CRC is received/send with the MSB shifted first.
Incoming CRC is calculated from the incoming data.
Outgoing CRC is calculated from the outgoing data. CRC calculation does not include zero bits that are shifted out while incoming data and incoming CRC are shifting in (See REF _Ref66693848 \h Figure 1 on page PAGEREF _Ref513134321 \h 15 for example).
5.3 WISHBONE sub-module
Is capable of doing the 8-bit, 16-bit and 32-bit WISHBONE accesses. All accesses are single accesses since the data flow through the TAP (JTAG) is slow and there is no need for bursts. Wishbone clock frequency must be higher than the TCK frequency. See section REF _Ref63232554 \h 4.2 WISHBONE Sub-module on page PAGEREF _Ref63232532 \h 16 for more information about the WISHBONE sub-module.
Open Cores SoC Debug Interface DATE \* MERGEFORMAT 3/14/2004
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HYPERLINK "http://www.opencores.org/" http://www.opencores.org/ Rev 2.1 Page PAGE 19 of NUMPAGES 49
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G I Q R W X Z _ ` a x
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- 5 1 0 V Bw n eK Q$ 5 "F < ^F % L _L B
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SoC Debug Interface
Author: Igor Mohor
IgorM@opencores.org
Rev. 2.1
March 14, 2004
Copyright (C) 2001 - 2004 OPENCORES.ORG and Authors.
This document is free; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
Revision History
Rev.DateAuthorDescription0.102/02/01Igor MohorFirst Draft0.205/04/01IMTrace port added0.316/04/01IMWP and BP number changed, trace modified0.401/05/01IMTitle changed, DEBUG instruction added, scan chains changed, IO ports changed 0.505/05/01IMTSEL and QSEL register changed0.606/05/01IMPorts connected to the OpenRISC changed0.714/05/01IMMODER register changed, trace scan chain changed; SSEL register added0.818/05/01IMRESET bit and signal added; STALLR changed to RISCOP0.923/05/01IMRISC changed to OpenRISC; WISHBONE interface added, SPR and memory access added0.1001/06/01IMMeaning of Instruction status and Load/store status changed in all registers; more details added to Appendix A 0.1110/09/01IMRegister and OpenRISC scan chain operation changed1.019/09/01IMSome registers deleted1.115/10/01IMWISHBONE interface added; RISC Stall signal is set by breakpoint and reset by writing 0 to RISCOP register1.203/12/01IMChain length changed so additional CRC checking can be performed 1.321/01/02Jeanne WiegelmannDocument revised. 1.407/05/02IMRegister MONCNTL added. 1.510/10/02IMWISHBONE Scan Chain changed to show state of the access. 1.606/11/02IMTRST_PAD_I changed from active low signal to active low signal.1.723/09/03Simon SrotMultiple CPU support added, WB 16-bit and 8-bit access possible through WBCNTL register use.2.001/02/04IMNew version of debug interface. Document name changed, Document split into two documents, one for TAP and one for debug.2.114/03/04IMMissing things added to the documents.
Contents
TOC \o "1-4" \h \z HYPERLINK \l "_Toc67050066" 1 PAGEREF _Toc67050066 \h 7
HYPERLINK \l "_Toc67050067" Introduction PAGEREF _Toc67050067 \h 7
HYPERLINK \l "_Toc67050068" 2 PAGEREF _Toc67050068 \h 8
HYPERLINK \l "_Toc67050069" IO Ports PAGEREF _Toc67050069 \h 8
HYPERLINK \l "_Toc67050070" 2.1 TAP Ports PAGEREF _Toc67050070 \h 8
HYPERLINK \l "_Toc67050071" 2.2 CPU Ports PAGEREF _Toc67050071 \h 9
HYPERLINK \l "_Toc67050072" 2.3 WISHBONE Ports PAGEREF _Toc67050072 \h 9
HYPERLINK \l "_Toc67050073" 3 PAGEREF _Toc67050073 \h 11
HYPERLINK \l "_Toc67050074" Registers PAGEREF _Toc67050074 \h 11
HYPERLINK \l "_Toc67050075" 3.1 CPU Registers List PAGEREF _Toc67050075 \h 11
HYPERLINK \l "_Toc67050076" 3.2 CPU Operation Register PAGEREF _Toc67050076 \h 12
HYPERLINK \l "_Toc67050077" 3.3 CPU Select Register PAGEREF _Toc67050077 \h 13
HYPERLINK \l "_Toc67050078" 4 PAGEREF _Toc67050078 \h 14
HYPERLINK \l "_Toc67050079" Operation PAGEREF _Toc67050079 \h 14
HYPERLINK \l "_Toc67050080" 4.1 Chain Selection PAGEREF _Toc67050080 \h 14
HYPERLINK \l "_Toc67050081" 4.2 WISHBONE Sub-module PAGEREF _Toc67050081 \h 16
HYPERLINK \l "_Toc67050082" 4.2.1 WISHBONE Read operation PAGEREF _Toc67050082 \h 17
HYPERLINK \l "_Toc67050083" 4.2.2 WISHBONE Write operation PAGEREF _Toc67050083 \h 18
HYPERLINK \l "_Toc67050084" 4.2.3 READx/WRITEx instruction PAGEREF _Toc67050084 \h 19
HYPERLINK \l "_Toc67050085" 4.2.4 GO instruction PAGEREF _Toc67050085 \h 21
HYPERLINK \l "_Toc67050086" 4.2.4.1 GO with READx requested PAGEREF _Toc67050086 \h 21
HYPERLINK \l "_Toc67050087" 4.2.4.2 GO with WRITEx requested PAGEREF _Toc67050087 \h 23
HYPERLINK \l "_Toc67050088" 4.2.5 STATUS instruction PAGEREF _Toc67050088 \h 25
HYPERLINK \l "_Toc67050089" 4.2.6 Data and select signals PAGEREF _Toc67050089 \h 28
HYPERLINK \l "_Toc67050090" 4.2.7 Accessing slow devices PAGEREF _Toc67050090 \h 29
HYPERLINK \l "_Toc67050091" 4.2.7.1 Reading from slow device PAGEREF _Toc67050091 \h 29
HYPERLINK \l "_Toc67050092" 4.2.7.2 Writing to slow device PAGEREF _Toc67050092 \h 30
HYPERLINK \l "_Toc67050093" 4.2.8 Error and retry on the WISHBONE PAGEREF _Toc67050093 \h 31
HYPERLINK \l "_Toc67050094" 4.3 CPU Sub-module PAGEREF _Toc67050094 \h 32
HYPERLINK \l "_Toc67050095" 4.3.1 CPU Register Read operation PAGEREF _Toc67050095 \h 34
HYPERLINK \l "_Toc67050096" 4.3.2 CPU Register Write operation PAGEREF _Toc67050096 \h 35
HYPERLINK \l "_Toc67050097" 4.3.3 CPU Read operation PAGEREF _Toc67050097 \h 36
HYPERLINK \l "_Toc67050098" 4.3.4 CPU Write operation PAGEREF _Toc67050098 \h 37
HYPERLINK \l "_Toc67050099" 4.3.5 CPU_READx/CPU_WRITEx operation PAGEREF _Toc67050099 \h 38
HYPERLINK \l "_Toc67050100" 4.3.6 GO instruction PAGEREF _Toc67050100 \h 40
HYPERLINK \l "_Toc67050101" 4.3.6.1 GO with CPU_READx requested PAGEREF _Toc67050101 \h 40
HYPERLINK \l "_Toc67050102" 4.3.6.2 GO with CPU_WRITEx requested PAGEREF _Toc67050102 \h 42
HYPERLINK \l "_Toc67050103" 4.3.7 Selecting different CPUs PAGEREF _Toc67050103 \h 44
HYPERLINK \l "_Toc67050104" 4.3.8 Stalling CPU(s) PAGEREF _Toc67050104 \h 44
HYPERLINK \l "_Toc67050105" 4.3.9 Resetting CPUs PAGEREF _Toc67050105 \h 45
HYPERLINK \l "_Toc67050106" 5 PAGEREF _Toc67050106 \h 46
HYPERLINK \l "_Toc67050107" Architecture PAGEREF _Toc67050107 \h 46
HYPERLINK \l "_Toc67050108" 5.1 Debug Interface PAGEREF _Toc67050108 \h 48
HYPERLINK \l "_Toc67050109" 5.2 CRC sub-module PAGEREF _Toc67050109 \h 48
HYPERLINK \l "_Toc67050110" 5.3 WISHBONE sub-module PAGEREF _Toc67050110 \h 49
Introduction
The Development Interface is used for debugging purposes and is as such an interface between the processor(s), peripheral cores, and any commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a fully IEEE 1149.1 compatible JTAG TAP port that is not part of this core. TAP is available at the opencores, too (look for project JTAG Test Access Port (TAP)).
IO Ports
2.1 TAP Ports
Debug interface connects to the TAP controller with the following signals:
PortWidth DirectionDescriptiontck_i1inputTest clock inputtdi_i1inputTest data inputtdo_o1outputTest data outputshift_dr_i1inputTAP controller state Shift DRpause_dr_i1inputTAP controller state Pause DRupdate_dr_i1inputTAP controller state Update DRdebug_select_i1inputInstruction DEBUG is activatedTable SEQ Table \* ARABIC 1: TAP Ports
2.2 CPU Ports
Port Width DirectionDescriptioncpu_clk_i1inputCPU clock signal.cpu_addr_o32outputCPU addresscpu_data_i32inputCPU data input (data from CPU)cpu_data_o32outputCPU data output (data to CPU)cpu_bp_i1inputCPU breakpointcpu_stall_o1outputCPU stall (selected CPU is stalled)cpu_stall_all_o1outputCPU stall all (all unselected CPUs are stalled)cpu_stb_o1outputCPU strobecpu_sel_o8outputCPU select signals (one hot), select the CPUcpu_we_o1outputCPU write enable signal indicates a write cycle when asserted high (read cycle when low).cpu_ack_i1inputCPU acknowledge (signals end of cycle)cpu_rst_o1outputCPU reset output (resets CPU)Table SEQ Table \* ARABIC 2: CPU Ports
2.3 WISHBONE Ports
Port Width DirectionDescriptionwb_clk_i1inputWISHBONE clockwb_rst_i1inputWISHBONE resetwb_ack_i1inputWISHBONE acknowledge indicates a normal cycle terminationwb_adr_o32outputWISHBONE address outputwb_cyc_o1outputWISHBONE cycle encapsulates a valid transfer cycle.wb_dat_i32inputWISHBONE data input (data from WISHBONE)wb_dat_o32outputWISHBONE data output (data to WISHBONE)wb_err_i1inputWISHBONE error acknowledge indicates an abnormal cycle terminationwb_sel_o4outputWISHBONE select indicates which bytes are valid on the data bus. wb_stb_o1outputWISHBONE strobe indicates a valid transfer.wb_we_o1outputWISHBONE write enable indicates a write cycle when asserted high (read cycle when low).wb_cab_o1outputWISHBONE consecutive address burst indicates a burst cycle.wb_cti_o3outputWISHBONE cycle type identifier indicates type of cycle (single, burst, end of burst)wb_bte_o2outputWISHBONE burst type extensionTable SEQ Table \* ARABIC 3: WISHBONE Ports
Registers
This section specifies all registers in the Debug Interface. There are currently two sub-modules in the debug interface, WISHBONE and CPU.
WISHBONE sub-module doesnt have internal registers.
CPU sub-module does have internal registers and they are described in the following section.
3.1 CPU Registers List
Name Address Width AccessDescriptionCPU_OP0x08R/WCPU Operation RegisterCPU_SEL0x18R/WCPU Select Register
Table SEQ Table \* ARABIC 4: CPU Register List
3.2 CPU Operation Register
Bit #AccessDescription7:3Reserved2R/WCPUSTALLALL Stall all unselected CPUs
0 = normal operation
1 = Stall all unselected CPUs1R/WRESET Reset CPU
0 = normal
1 = reset0R/WCPUSTALL CPU Stall
0 = normal operation
1 = Stall CPU. CPU can also set this bit by inserting the cpu_bp_i signal.Table SEQ Table \* ARABIC 5: CPU_OP Register
Reset Value:
CPU_OP: 00h
3.3 CPU Select Register
Bit # AccessDescription7:0R/WCPUSEL Select one CPU
00000001b = Selects CPU 0 (cpu_sel_o [0] is active)
00000010b = Selects CPU 1 (cpu_sel_o [1] is active)
00000100b = Selects CPU 2 (cpu_sel_o [2] is active)
00001000b = Selects CPU 3 (cpu_sel_o [3] is active)
00010000b = Selects CPU 4 (cpu_sel_o [4] is active)
00100000b = Selects CPU 5 (cpu_sel_o [5] is active)
01000000b = Selects CPU 6 (cpu_sel_o [6] is active)
10000000b = Selects CPU 7 (cpu_sel_o [7] is active)
00000000b = NO CPU selected (cpu_sel_o [7:0] not active)Table SEQ Table \* ARABIC 6: CPU_SEL Register
Reset Value:
CPU_SEL: 00h
Operation
This section describes the operation of the Debug Interface and its sub-modules.
4.1 Chain Selection
The debug interface is just an interface between the sub-module that is target specific and the TAP controller. Currently two sub-modules are connected to the debug interface, WISHBONE sub-module and CPU sub-module. Up to 8 sub-modules can be connected to the debug interface.
First thing to do is to select the sub-module. This is done with the chain select instruction. Following needs to be done prior to the chain select operation:
instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)
Then the chain select instruction needs to be shifted-in through the TAP data chain:
1-bit with value 1 (This bit is treated as a chain select)
3-bit chain ID (LSB shifted first)
32-bit CRC (MSB shifted first) that is protecting the incoming data (first four bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the chain select instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
1 if command was chain select, else 0
1 if non-existing chain was selected, else 0
always 1
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 36 bits are ignored).
SHAPE \* MERGEFORMAT
Figure SEQ Figure \* ARABIC 1: Chain Selection
See section REF _Ref63228021 \h 5.2 CRC sub-module on page PAGEREF _Ref63228021 \h 48 for more details about the CRC.
4.2 WISHBONE Sub-module
There are three types of instruction in the WISHBONE sub-module (see REF _Ref66710201 \h \* MERGEFORMAT
Table 7: WISHBONE sub-module: Supported Instructions REF _Ref66710201 \p \h below for more details):
READx/WRITEx instructions
GO instruction
STATUS instruction
The following table describes all supported instructions and their codes:
InstructionCodeMeaningSTATUS000Reads the status of the previous command(s)WRITE8001Requests write of the 8-bit dataWRITE16010Requests write of the 16-bit dataWRITE32011Requests write of the 32-bit dataGO100Performs the requested instructionREAD8101Requests read of the 8-bit dataREAD16110Requests read of the 16-bit dataREAD32111Requests read of the 32-bit data
Table SEQ Table \* ARABIC 7: WISHBONE sub-module: Supported Instructions
All WISHBONE operations (except STATUS) consist of two consequent instructions. First instruction is the READx/WRITEx instruction. It sets the address, type of instruction (read or write) and length of data that is read or written. Second instruction is the GO instruction that actually does what the first instruction requests. Following section describes how read, write or status operations are performed.
Note: Before some data can be read from or written to the WISHBONE, the following needs to be done:
instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)
WISHBONE sub-module needs to be selected (refer to section REF _Ref63237097 \h 4.1 Chain Selection on page PAGEREF _Ref63237097 \h 14 for more details)
4.2.1 WISHBONE Read operation
To perform the WISHBONE read operation, the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the WISHBONE sub-module selected (see description on page PAGEREF _Ref63237097 \h 14 for more details).
Read operation is performed in two steps:
Issuing the READx instruction (see section REF _Ref67050293 \h 4.2.3 READx/WRITEx instruction on page PAGEREF _Ref67050304 \h 19 for more details)
Issuing the GO instruction (see section REF _Ref66768261 \h 4.2.4.1 GO with READx requested on page PAGEREF _Ref66768261 \h 21 for more details)
First instruction sets the address, type of operation and data length that needs to be read.
Second instruction performs the read operation on the WISHBONE bus.
Both instructions (READx and GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully. However it is also possible to check the status after the operation by issuing the STATUS instruction. Go to the section REF _Ref66775180 \h 4.2.5 STATUS instruction on page PAGEREF _Ref66775194 \h 25 for more information about the STATUS.
Whenever an error occurs, both steps (READx and GO) need to be repeated.
4.2.2 WISHBONE Write operation
To perform the WISHBONE write operation, the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the WISHBONE sub-module selected (see description on page PAGEREF _Ref63237097 \h 14 for more details).
Write operation is performed in two steps:
Issuing the WRITEx instruction (see section REF _Ref67050369 \h 4.2.3 READx/WRITEx instruction on page PAGEREF _Ref67050381 \h 19 for more details)
Issuing the GO instruction (see section REF _Ref66768668 \h 4.2.4.2 GO with WRITEx requested on page PAGEREF _Ref66768668 \h 23 for more details)
First instruction sets the address, type of operation and data length that needs to be written.
Second instruction performs the write operation on the WISHBONE bus.
Both instructions (WRITEx and GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully. However it is also possible to check the status after the operation by issuing the STATUS instruction. Go to the section REF _Ref66775180 \h 4.2.5 STATUS instruction on page PAGEREF _Ref66775194 \h 25 for more information about the STATUS.
Whenever an error occurs, both steps (WRITEx and GO) need to be repeated.
4.2.3 READx/WRITEx instruction
Read/write instruction sets the address, the type of operation and the length of the data that will be read or written. It is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction (READ8, READ16, READ32, WRITE8, WRITE16 or WRITE32, depending on the cycle type (read or write) and the data width (8-bit, 16-bit or 32-bit))
32-bit address
16-bit length (describes data length in bytes)
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 52 bits).
36 bits with value 0 (this value is ignored in the debug interface)
While the read/write instruction is shifted-in, the following data is shifted out:
84 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s of 0
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 84 bits are ignored).
Figure SEQ Figure \* ARABIC 2: READx/WRITEx instruction
4.2.4 GO instruction
GO instruction actually performs the instruction that was requested with the previous READx/WRITEx instruction. The structure of the GO instruction differs depending on the previous requested instruction. There are two possibilities:
READx instruction was previously requested
WRITEx instruction was previously requested
4.2.4.1 GO with READx requested
GO instruction with READx previously requested performs the read operation on the WISHBONE bus. Address, cycle type and data length are specified with the READx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
(data length x 8) bits with value 0 (this value is ignored in the debug interface). Number x is number of bits that are read out.
While the GO instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
(data length x 8) bits of data
4-bit status
1 if incoming CRC is OK, else 0
1 if WISHBONE cycle didnt finish (still in progress), else 0. This is important only for the first data byte
1 if under run occurred (data couldnt be read fast enough), else 0
1 if WISHBONE error occurred
32-bit CRC (MSB shifted first) that is protecting the outgoing data (data length x 8 + 4 bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 3: GO with READx requested
4.2.4.2 GO with WRITEx requested
GO instruction with WRITEx previously requested performs the write operation on the WISHBONE bus. Address, cycle type and data length are specified with the WRITEx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
(data length x 8) bits of data
32-bit CRC (MSB shifted first) that is protecting the incoming data (first data length x 8 + 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the GO instruction is shifted-in, the following data is shifted out:
(length x 8 + 36) bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
1 if WISHBONE cycle didnt finish (still in progress), else 0. This is important only for the first data byte
1 if overrun occurred (data couldnt be write fast enough), else 0
1 if WISHBONE error occurred
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first length x 8 + 36 bits are ignored).
Figure SEQ Figure \* ARABIC 4: GO with WRITEx requested
4.2.5 STATUS instruction
STATUS instruction is used for reading the value of the status register. Status register consists of four bits. The MSB bit is always shifted out first. The meaning of the bits is described in the following table.
Status bit #Meaning30 = Incoming CRC error
1 = Incoming CRC OK20 = WISHBONE cycle finished
1 = WISHBONE cycle not finished10 = no overrun/underrun
1 = overrun/underrun occurred00 = No WISHBONE error
1= WISHBONE error occurred
Table SEQ Table \* ARABIC 8: Status bit description
Bit 0 is set when at least one WISHBONE error occurred since the last STATUS instruction was performed. Once set, it can be cleared only with the STATUS instruction.
Bit 1 is set when at least one underrun (for read operation) or overrun (for write) happened since the last STATUS instruction was performed. Underrun is when data is not available for reading on time. Overrun is when data is not written to the device on time (new data arrives before the previous data is written). Once set, it can be cleared only with the STATUS instruction.
Bit 2 is set while the WISHBONE cycle is in progress (not finished, yet). Go to section REF _Ref66969966 \h 4.2.7 Accessing slow devices on page PAGEREF _Ref66969966 \h 29 to read how to access data from slow devices. This bit changes when the access is finished (is not latched).
Bit 3 is cleared to zero when the CRC error occurs while shifting the data into the debug interface. This bit is valid only for the last instruction. STATUS instruction does not change the value of this bit.
The STATUS instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction STATUS
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the STATUS instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
4-bit status (see REF _Ref66767365 \h Table 8 REF _Ref66767373 \p \h above for more details)
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 5: STATUS Instruction
4.2.6 Data and select signals
Data in the WISHBONE sub-module is organized in the big endian byte ordering. Following section describes the data and select signals depending on the address and type of operation (32-bit, 16-bit and 8-bit).
32-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1111b
wb_dat_x[31:0] are used
16-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1100b
wb_dat_x[31:16] are used
16-bit access (wb_adr_o[1:0] = 10b):
wb_sel_o[3:0] = 0011b
wb_dat_x[15:0] are used
8-bit access (wb_adr_o[1:0] = 00b):
wb_sel_o[3:0] = 1000b
wb_dat_x[31:24] are used
8-bit access (wb_adr_o[1:0] = 01b):
wb_sel_o[3:0] = 0100b
wb_dat_x[23:16] are used
8-bit access (wb_adr_o[1:0] = 10b):
wb_sel_o[3:0] = 0010b
wb_dat_x[15:8] are used
8-bit access (wb_adr_o[1:0] = 11b):
wb_sel_o[3:0] = 0001b
wb_dat_x[7:0] are used
4.2.7 Accessing slow devices
Usually the WISHBONE clock (wb_clk_i) is much slower than the JTAG clock (tck_i). In that case read or write accesses are finished on time. However it is possible to do a read or write access to a WISHBONE device that is not fast enough to complete the desired operation on time.
On time means:
Read operation needs to be finished before the data is shifted out through the JTAG
Write operation must be finished before the next write is started.
4.2.7.1 Reading from slow device
Following needs to be done to read the data from a slow device:
Perform the READx instruction normally
Perform only first part of the GO instruction. After the first 36 bits are shifted out, force TAP state machine to go to the PAUSE_DR state. This means that the tms_i signal needs to be driven high after the 35th bit.
Once in the PAUSE_DR state, tdo_o signal reflects the state of the WISHBONE bus. While bus is busy (read cycle not finished), tdo_o is set to 1. Once the read cycle is finished, tdo_o goes to zero. Loop in the PAUSE_DR state until tdo_o goes to zero. Then go to the SHIFT_DR state and continue like nothing happened. When reading more data, go to the PAUSE_DR state after each word/half/byte is shifted out (depending on the type of access (8, 16 or 32 bit)).
CRC is not calculated when not in the SHIFT_DR state.
Note: TAP state machine is described in the documentation that is part of the project JTAG Test Access Port (TAP) that is available on the opencores website.
4.2.7.2 Writing to slow device
Following needs to be done to write the data to a slow device:
Perform the WRITEx instruction normally.
Perform only part of the GO instruction. After the first 4 bits are shifted in, shift in the first data word/half/byte. Then force the TAP state machine to go to the PAUSE_DR state. This means that the tms_i signal needs to be driven high after the 35th bit for 32-bit access, 19th bit for 16-bit access or 11th bit for 8-bit access.
Once in the PAUSE_DR state, tdo_o signal reflects the state of the WISHBONE bus. While bus is busy (write cycle not finished), tdo_o is set to 1. Once the write cycle is finished, tdo_o goes to zero. Loop in the PAUSE_DR state until tdo_o goes to zero. Then go to the SHIFT_DR state and continue like nothing happened. When writing more data, go to the PAUSE_DR state after each data word/half/byte is shifted in.
Check the busy status also after the last data word/half/byte. Then shift out the status and the CRC
CRC is not calculated when not in the SHIFT_DR state.
Note: TAP state machine is described in the documentation that is part of the project JTAG Test Access Port (TAP) that is available on the opencores website.
4.2.8 Error and retry on the WISHBONE
When a WISHBONE cycle is terminated with an error (signal wb_err_i is set to 1), the status bit [0] is set to 1. This bit remains set until the status is read with the STATUS instruction. This is useful to detect errors that occurred during several consecutive cycles (reading/writing data from/to consecutive addresses).
When the addresses WISHBONE device replies to late to the request, status bit [1] (overrun/underrun) is set. This bit remains set until the status is read with the STATUS instruction. This is useful to detect errors that occurred during several consecutive cycles.
WISHBONE retry function is not supported.
4.3 CPU Sub-module
CPU sub-module is an interface to the CPU debug facilities (that are part of the CPU). It consists of the internal registers and the CPU interface.
The CPU sub-module can access both, internal CPU registers and the CPU interface (CPUs on the other side of the debug interface).
Internal registers are used for:
selecting one of the connected CPUs
resetting the CPU(s)
stalling the selected CPU
stalling all unselected CPUs
Before the CPU sub-module can be accessed, several steps need to be taken:
debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must be selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
The following table describes all supported instructions and their codes.
InstructionCodeMeaningCPU_WRITE8001Requests write of the 8-bit data to the CPU.CPU_WRITE32010Requests write of the 32-bit data to the CPU.CPU_WRITE_REG011Requests write of the 8-bit data to the internal CPU register.CPU_GO100Performs the requested instruction.CPU_READ8101Requests read of the 8-bit data from the CPU.CPU_READ32110Requests read of the 32-bit data from the CPU.CPU_READ_REG111Requests read of the 8-bit data from the internal CPU register.
Table SEQ Table \* ARABIC 9: CPU sub-module: Supported Instructions
4.3.1 CPU Register Read operation
To read the data from the CPU register (internal register that is part of the CPU sub-module), the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the CPU sub-module selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
Read operation is performed in two steps:
Issuing the CPU_READ_REG instruction (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details)
Issuing the CPU_GO instruction (see section REF _Ref67049187 \h 4.3.6.1 GO with CPU_READx requested on page PAGEREF _Ref67049187 \h 40 for more details)
First instruction sets the address of the register. Second instruction performs the read operation to the addressed internal CPU register.
Both instructions (CPU_READ_REG and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_READ_REG and CPU_GO) need to be repeated.
4.3.2 CPU Register Write operation
To write the data from the CPU register (internal register that is part of the CPU sub-module), the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information)) and the CPU sub-module selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details).
Write operation is performed in two steps:
Issuing the CPU_WRITE_REG instruction (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details)
Issuing the CPU_GO instruction (see section REF _Ref67048987 \h 4.3.6.2 GO with CPU_WRITEx requested on page PAGEREF _Ref67048987 \h 42 for more details)
First instruction sets the address of the register. Second instruction performs the write operation to the addressed internal CPU register.
Both instructions (CPU_WRITE_REG and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_WRITE_REG and CPU_GO) need to be repeated.
4.3.3 CPU Read operation
To read the data from the CPU, following needs to be done:
the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details)
CPU must be selected. Selection is made through the write operation to the internal CPU register (See section REF _Ref67049087 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67049104 \h 44 for more details).
Read operation is performed in two steps:
Issuing the CPU_READ8 instruction when 8-bit read is needed or CPU_READ32 instruction when 32-bit read is needed (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details).
Issuing the CPU_GO instruction (see section REF _Ref67049187 \h 4.3.6.1 GO with CPU_READx requested on page PAGEREF _Ref67049187 \h 40 for more details)
First instruction sets the address of the CPU where the data will be read from. Second instruction performs the read operation to the addressed CPU space.
Both instructions (CPU_READ8/32 and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_READ8/32 and CPU_GO) need to be repeated.
4.3.4 CPU Write operation
To write the data to the CPU, following needs to be done:
the debug must be enabled (instruction DEBUG needs to be activated in the TAP (refer to the IEEE 1149.1 Test Access Port documentation for more information))
CPU sub-module must selected (see description of the REF _Ref63237097 \h 4.1 Chain Selection section on page PAGEREF _Ref63237097 \h 14 for more details)
CPU must be selected. Selection is made through the write operation to the internal CPU register (See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44).
Write operation is performed in two steps:
Issuing the CPU_WRITE8 instruction when 8-bit write is needed or CPU_WRITE32 instruction when 32-bit read is needed (see section REF _Ref67048924 \h 4.3.5 CPU_READx/CPU_WRITEx operation on page PAGEREF _Ref67048924 \h 38 for more details).
Issuing the CPU_GO instruction (see section REF _Ref67048987 \h 4.3.6.2 GO with CPU_WRITEx requested on page PAGEREF _Ref67048987 \h 42 for more details)
First instruction sets the address of the CPU where the data will be written to. Second instruction performs the write operation to the addressed CPU space.
Both instructions (CPU_WRITE8/32 and CPU_GO) return status. This status should be checked on-the-fly to verify that the instruction was completed successfully.
Whenever an error occurs, both steps (CPU_WRITE8/32 and CPU_GO) need to be repeated.
4.3.5 CPU_READx/CPU_WRITEx operation
CPU_READ8, CPU_READ32, CPU_WRITE8 and CPU_WRITE32 instructions set the address of the CPU where the data that will be read from or written to.
CPU_READ_REG and CPU_WRITE_REG instructions set the address of the internal CPU register (that is part of the CPU sub-module) where the data that will be read from or written to.
All mentioned instructions are performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction (CPU_READ8, CPU_READ32, CPU_READ_REG, CPU_WRITE8, CPU_WRITE32 or CPU_WRITE_REG) depending on the cycle type (32-bit or 8-bit access to the CPU or 8-bit access to the CPU register))
32-bit address
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 36 bits).
36 bits with value 0 (this value is ignored in the debug interface)
While the CPU_READx/CPU_WRITEx instruction is shifted-in, the following data is shifted out:
68 bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (four bits). Only status bits are protected with this CRC (first 68 bits are ignored).
Figure SEQ Figure \* ARABIC 6: CPU_READx/CPU_WRITEx instruction
4.3.6 GO instruction
GO instruction actually performs the instruction that was requested with the previous CPU_READx/CPU_WRITEx instruction. The structure of the GO instruction differs depending on the previous requested instruction. There are two possibilities:
CPU_READx instruction was previously requested
CPU_WRITEx instruction was previously requested
4.3.6.1 GO with CPU_READx requested
GO instruction with CPU_READx previously requested performs the read operation to the:
internal CPU register (that is part of the CPU sub-module)
or
CPU that is connected to the CPU sub-module (CPU must be previously selected. See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44)
Address of the internal CPU register or the location in the CPU is specified with the previous CPU_READx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 4 bits).
x bits with value 0 (this value is ignored in the debug interface). Number x is number of bits that are read out.
36 + 32 for CPU_READ32
36 + 8 for CPU_READ8 or CPU_READ_REG
While the GO instruction is shifted-in, the following data is shifted out:
36 bits with value 0 (this value should be ignored)
x bits of data
x is 32 for CPU_READ32
x is 8 for CPU_READ8 or CPU_READ_REG
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (32(8) + 4 bits). Only outgoing data bits are protected with this CRC (first 36 bits are ignored).
Figure SEQ Figure \* ARABIC 7: GO with CPU_READx requested
4.3.6.2 GO with CPU_WRITEx requested
GO instruction with CPU_WRITEx previously requested performs the write operation to the:
internal CPU register (that is part of the CPU sub-module)
or
CPU that is connected to the CPU sub-module (CPU must be previously selected. See section REF _Ref67048750 \h 4.3.7 Selecting different CPUs on page PAGEREF _Ref67048756 \h 44)
Address of the internal CPU register or the location in the CPU is specified with the previous CPU_WRITEx instruction. The GO instruction is performed by shifting the following data through the data scan chain:
1-bit with value 0
3-bit instruction GO
x bits of data
x is 32 for CPU_READ32
x is 8 for CPU_READ8 or CPU_READ_REG
32-bit CRC (MSB shifted first) that is protecting the incoming data (first 32(8) + 4 bits).
36 bits with value 0 (these bits are ignored in the debug interface)
While the GO instruction is shifted-in, the following data is shifted out:
36 + 32(8) bits with value 0 (this value should be ignored)
4-bit status
1 if incoming CRC is OK, else 0
3 bit-s 010b
32-bit CRC (MSB shifted first) that is protecting the outgoing data (4 status bits). Only outgoing data bits are protected with this CRC (first 36 + 32(8) bits are ignored).
Figure SEQ Figure \* ARABIC 8: GO with CPU_WRITEx requested
4.3.7 Selecting different CPUs
cpu_sel_o and cpu_stall_all_o signals have been added to the Debug Interface to support more than one CPU. It is meant, that this signals are used to enable multiplexing of all the signals going from/to CPU and Debug Interface (cpu_bp_i, cpu_data_i, cpu_data_o, cpu_addr_o, cpu_stall_o, cpu_ack_i). The multiplexing of signals is not part of the Debug Interface and is the responsibility of the system integrator.
cpu_sel_o signals are controlled from CPU_SEL register and cpu_stall_all_o signal is controlled from CPU_OP register.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
Normally, if just one CPU is connected to the Debug Interface these signals are not necessary and can be ignored.
4.3.8 Stalling CPU(s)
The selected CPU can be stalled in two ways:
By deliberately setting bit CPUSTALL in the CPU_OP register to 1 (see section REF _Ref63271995 \h 3.2 CPU Operation Register on page PAGEREF _Ref63271998 \h 12 for more details). Clearing this bit again restarts the CPU.
An input breakpoint signal (cpu_bp_i) automatically stops the CPU and sets bit 0 of the CPU_OP register to 1. Clearing this bit again restarts the CPU.
When CPUSTALLALL bit is set in the CPU_OP register, all unselected CPUs are stalled.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
For more information about the breakpoint generation refer to the CPU manual (i.e. OpenRISC 1000 System Architecture Manual).
4.3.9 Resetting CPUs
The Debug Interface puts the CPU to reset by setting the RESET bit in the CPU_OP register to 1. Clearing this bit to 0 deactivates the reset signal.
For more information about changing the value of the internal CPU register go to the section REF _Ref67047744 \h 4.3.2 CPU Register Write operation on page PAGEREF _Ref67047744 \h 35.
Reading the value of the internal CPU register is described in section REF _Ref67047818 \h 4.3.1 CPU Register Read operation on page PAGEREF _Ref67047818 \h 34.
Architecture
The SoC Debug Interface architecture is based on IEEE Std. 1149.1 Standard Test Access Port and Boundary Scan Architecture. Other signals are added to provide additional flexibility.
The interface consists of several parts (blocks):
Logic that selects one of the connected scan chains (from sub-modules). Currently two sub-modules are available, CPU and WISHBONE.
CRC sub-module that checks incoming data.
CRC sub-module that calculates the CRC for the outgoing data.
WISHBONE sub-module
CPU sub-module
As seen on the following figure, debug interface is just one part of the complete debugging system. For more information about the TAP controller, go to the opencores web site and look for the project JTAG Test Access Port (TAP). There is a complete IP core with test bench and documentation available.
If there are more than 1 CPU in the system, then additional external logic is needed (marked as MUX logic in the REF _Ref63219195 \h Figure 9: Complete system on page PAGEREF _Ref63219195 \h 47). The function of this logic is:
Multiplexes data that comes from CPUs to data that goes to the debug interface.
Defines stall signals that are connected to the CPUs from cpu_stall_o, cpu_stall_all_o and cpu_sel_o signals.
Figure SEQ Figure \* ARABIC 9: Complete system
5.1 Debug Interface
Debug Interface is an interface between the TAP controller and the sub-modules that are target specific (CPU, WISHBONE...). It receives data from the TAP whenever the DEBUG instruction is active (see IEEE 1149.1 Test Access Port documentation).
Data can hold two kinds of instructions:
Chain select instruction
Sub-module instruction
First bit of the instruction is used to distinguish between the chain select instruction (first bit is 1) and the sub-module instruction (first bit is 0).
Chain select instruction is used for selecting/enabling the sub-module.
Sub-module instructions are sub-module specific. Each sub-module can use different instructions. Because of this, it is very easy to add additional sub-modules.
All the data (in both directions) is protected with the 32-bit CRC (see section REF _Ref63228021 \h 5.2 CRC sub-module on page PAGEREF _Ref63228021 \h 48 for more information). Both CRC engines (one for incoming data and one for outgoing data) are located in the debug interface. None of the sub-modules have their own CRC engine.
5.2 CRC sub-module
There are two CRC sub-modules in the debug interface. One is checking the incoming data, while the other is calculating the CRC from the outgoing data.
The following polynomial is used for 32-bit CRC calculation:
1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32
1-bit data input is used for CRC calculation. CRC is initialized to the value 0xffffffff before the actual CRC calculation starts. The CRC is received/send with the MSB shifted first.
Incoming CRC is calculated from the incoming data.
Outgoing CRC is calculated from the outgoing data. CRC calculation does not include zero bits that are shifted out while incoming data and incoming CRC are shifting in (See REF _Ref66693848 \h Figure 1 on page PAGEREF _Ref513134321 \h 15 for example).
5.3 WISHBONE sub-module
Is capable of doing the 8-bit, 16-bit and 32-bit WISHBONE accesses. All accesses are single accesses since the data flow through the TAP (JTAG) is slow and there is no need for bursts. Wishbone clock frequency must be higher than the TCK frequency. See section REF _Ref63232554 \h 4.2 WISHBONE Sub-module on page PAGEREF _Ref63232532 \h 16 for more information about the WISHBONE sub-module.
Open Cores SoC Debug Interface DATE \* MERGEFORMAT 3/14/2004
PAGE
HYPERLINK "http://www.opencores.org/" http://www.opencores.org/ Rev 2.1 Page PAGE 19 of NUMPAGES 49
TDI
32(8) data bits
0
32-bit
CRC
Outgoing data
Outgoing CRC
Incoming data
Incoming CRC
Data shifted out from the debug interface
36 zero bits
4-bit Status
32-bit CRC
Data shifted into the debug interface
32(8) + 36 zero bits
3-bit
GO Instr.
Boundary Scan Chain
TRSTn
TMS
TCK
TDO
TDI
TDI
TDO
3-bit
GO Instr.
TDO
TDI
0
TDI
32-bit CRC
Outgoing data
Outgoing CRC
Debug Interface
Incoming data
Incoming CRC
MBIST Scan Chain
0
Data shifted out from the debug interface
68 zero bits
4-bit Status
32-bit CRC
Data shifted into the debug interface
36 zero bits
32-bit address
36 zero bits
3-bit
Instr.
TDI
TDO
Debug Scan Chain
TDO
TDO
TDI
36 zero bits
CPU
+
CPU Development Interface
CPU
+
CPU Development Interface
0
32-bit CRC
Outgoing data
CPU n
Outgoing CRC
Incoming data
Incoming CRC
Data shifted out from the debug interface
CPU 1
4-bit Status
CPU sub-module
32-bit CRC
MUX
ID
FSM
TAP Controller
MUX
Data shifted into the debug interface
36 zero bits
3-bit
STATUS
Instruct.
TDI
TDO
TDO
data_len x 8 data bits
Data shifted out from the debug interface
TDI
data_len x 8 + 36 zero bits
Outgoing data
Data shifted into the debug interface
32-bit
CRC
36 zero bits
TDI
MUX logic
TDO
32-bit CRC
4-bit Status
Outgoing CRC
TDO
TDI
3-bit
GO Instr.
0
Incoming data
0
Incoming CRC
32-bit
CRC
Outgoing data
Outgoing CRC
Incoming data
Incoming CRC
Data shifted out from the debug interface
36 zero bits
4-bit Status
32-bit CRC
Data shifted into the debug interface
data_len x 8 + 36 zero bits
data_len x 8 data bits
3-bit
GO Instr.
TDI
TDO
TDO
16-bit
length
32-bit
CRC
Outgoing data
Outgoing CRC
TDO
Incoming data
Incoming CRC
Data shifted out from the debug interface
84 zero bits
4-bit Status
32-bit CRC
TDI
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36 zero bits
TDO
1
3-bit Chain ID
32-bit CRC
TDI
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Instr.
TDI
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Incoming data
Outgoing CRC
Incoming CRC
TDO
TDO
Data shifted out from the debug interface
Data shifted into the debug interface
TDO
TDI
36 zero bits
36 zero bits
4-bit Status
32-bit CRC
EMBED Word.Picture.8
TDI
WISHB. sub-module
Optional sub-modules
FSM
MUX
Reg.
CRC
Logic
MUX
FSM
Logic
Data shifted into the debug interface
32-bit CRC
4-bit Status
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Incoming CRC
Incoming data
Outgoing CRC
Outgoing data
32-bit
CRC
0
32(8) + 36 zero bits
32(8) data bits
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a p - - - - - - - P ʭ G d s G ` s G s G s G s _ $If gd~ kdS{ $$If l F f! < 8 ^
|
t 0 4
|
t 0 4
|
l `
|
l `
|
a p - - - - - - ?. P ʭ G d s G ` s G s G s G s _ $If gd~ kdg| $$If l F f! < 8 ^
|
a p - - - - - - ?. P ʭ G d s G ` s G s G s G s _ $If gd~ kdg| $$If l F f! < 8 ^
|
t 0 4
|
t 0 4
|
l `
|
l `
|
a p ?. @. q. ~. . . . . P I! K ! v: I ! D ! I ! ? D ! gdN gdN $a$ kdm} $$If l F f! < 8 ^
|
a p ?. @. q. ~. . . . . P I! K ! v: I ! D ! I ! ? D ! gdN gdN $a$ kdm} $$If l F f! < 8 ^
|
t 0 4
|
t 0 4
|
l `
|
l `
|
a p . . . . . . . . . . . . . . . . . . / / / / / :/ Q/ R/ d/ n/ / / / / / / / /
|
a p . . . . . . . . . . . . . . . . . . / / / / / :/ Q/ R/ d/ n/ / / / / / / / /
|
0 !0 "0 >0 U0 V0 r0 0 0 0 0 0 0 0 0 0 0 0 0 ǻ h{d h;* 5CJ \ h~ 5CJ \mH nH u j h{d hN 5CJ U\h{d hN 5CJ \ h{d hN \ h{d hlq h{d h[ h{d h;* h{d hN 5\ h{d hN h{d hc h) 6. . . . . . . d s s <
|
0 !0 "0 >0 U0 V0 r0 0 0 0 0 0 0 0 0 0 0 0 0 ǻ h{d h;* 5CJ \ h~ 5CJ \mH nH u j h{d hN 5CJ U\h{d hN 5CJ \ h{d hN \ h{d hlq h{d h[ h{d h;* h{d hN 5\ h{d hN h{d hc h) 6. . . . . . . d s s <
|
d s ` s kd~ $$If l 44 nF f!< 8 ^
|
d s ` s kd~ $$If l 44 nF f!< 8 ^
|
t & & & 0 4
|
t & & & 0 4
|
l `
|
l `
|
a f4p & & & _ $If gd~ . . / I/ }/ / / 0 M0 0 0 s s s s s s s s s s _ $If gd~
|
a f4p & & & _ $If gd~ . . / I/ }/ / / 0 M0 0 0 s s s s s s s s s s _ $If gd~
|
0 0 0 0 1 1 K NC C ! v: > ! > ! < ! gdN $a$gdN kd $$If l F f! < 8 ^
|
0 0 0 0 1 1 K NC C ! v: > ! > ! < ! gdN $a$gdN kd $$If l F f! < 8 ^
|
t 0 4
|
t 0 4
|
l `
|
l `
|
a p 0 0 0 0 0 0 0 1 1 B1 E1 O1 c1 e1 f1 g1 i1 j1 k1 z1 {1 2 2 q3 3 3 4 4 G4 V4 j4 k4 u4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 ||||x h P he h6 h
|
a p 0 0 0 0 0 0 0 1 1 B1 E1 O1 c1 e1 f1 g1 i1 j1 k1 z1 {1 2 2 q3 3 3 4 4 G4 V4 j4 k4 u4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 ||||x h P he h6 h
|
1 1 f1 g1 {1 2 2 03 3 3 4 H4 k4 4 5 5 ! D ! ! ! ! ! ! ! ! } ! ! ! H ! H ! } ! H !
|
1 1 f1 g1 {1 2 2 03 3 3 4 H4 k4 4 5 5 ! D ! ! ! ! ! ! ! ! } ! ! ! H ! H ! } ! H !
|
& FO gd6
|
& FO gd6
|
& FO gd? gd]B
|
& FO gd? gd]B
|
& FP gd? gd? gd? ^ C Eƀ p aF 5 5 5 5 ^5 `5 5 5 *6 >6 F6 Q6 b6 n6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 07 17 27 D7 E7 N7 O7 h7 ܾyr h{d h~ j hK Uj h Uh h hDo h~ 5CJ mH nH u j h hy 5CJ U h hy 5CJ hiZ j h
|
& FP gd? gd? gd? ^ C Eƀ p aF 5 5 5 5 ^5 `5 5 5 *6 >6 F6 Q6 b6 n6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 07 17 27 D7 E7 N7 O7 h7 ܾyr h{d h~ j hK Uj h Uh h hDo h~ 5CJ mH nH u j h hy 5CJ U h hy 5CJ hiZ j h
|
& FM gd? gd? gd $a$gd
|
& FM gd? gd? gd $a$gd
|
& FQ gd]B
|
& FQ gd]B
|
& FQ gd]B
|
& FQ gd]B
|
& FQ gdX gd]B h7 i7 j7 l7 m7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 I8 J8 K8 L8 d8 e8 f8 k8 l8 ~8 8 ~n~f[fWf h~ j h#, Uj h#, U h~ h~ \aJ mH nH u h~ h~ \aJ h~ h~ aJ h
|
& FQ gdX gd]B h7 i7 j7 l7 m7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 I8 J8 K8 L8 d8 e8 f8 k8 l8 ~8 8 ~n~f[fWf h~ j h#, Uj h#, U h~ h~ \aJ mH nH u h~ h~ \aJ h~ h~ aJ h
|
& FM gdJ? !9 "9 )9 -9 Y9 E
|
& FM gdJ? !9 "9 )9 -9 Y9 E
|
< s < s < ] s _ $If gd~ kdv $$If l 44 nF u1f!t 5
|
< s < s < ] s _ $If gd~ kdv $$If l 44 nF u1f!t 5
|
t & & & 0 e 4
|
t & & & 0 e 4
|
l `
|
l `
|
amf4p & & & Y9 Z9 a9 e9 9 K l B s B s B ] s _ $If gd~ kd̄ $$If l F u1f! t 5
|
amf4p & & & Y9 Z9 a9 e9 9 K l B s B s B ] s _ $If gd~ kd̄ $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp 9 9 9 9 9 K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
amp 9 9 9 9 9 K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp 9 9 9 9 9 K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
amp 9 9 9 9 9 K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp 9 9 9 9 : K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
amp 9 9 9 9 : K 9 B s B s B ] s _ $If gd~ kd $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp : : : : :: K 9 B s B s B ] s _ $If gd~ kd0 $$If l F u1f! t 5
|
amp : : : : :: K 9 B s B s B ] s _ $If gd~ kd0 $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp :: ;: B: F: g: K 9 B s B s B ] s _ $If gd~ kdI $$If l F u1f! t 5
|
amp :: ;: B: F: g: K 9 B s B s B ] s _ $If gd~ kdI $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp g: h: o: s: : K 9 B s B s B ] s _ $If gd~ kdb $$If l F u1f! t 5
|
amp g: h: o: s: : K 9 B s B s B ] s _ $If gd~ kdb $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp : : : : : < K 9 F ! > ! v: 5 ! 0 ! gd0
|
amp : : : : : < K 9 F ! > ! v: 5 ! 0 ! gd0
|
a
gdh $a$gd gd kd{ $$If l F u1f! t 5
|
a
gdh $a$gd gd kd{ $$If l F u1f! t 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp : : : : : : : : : : : ; ; N; Z; ; ; < < < < < < < < < < < < %= A= = = = = = = = = = = = = = = = = ijijįįijĨĠĕĠv h~ mH nH uj hK Uh~ h{d h~ j hK Uj h7 A U h? h7 A h h? h0
|
amp : : : : : : : : : : : ; ; N; Z; ; ; < < < < < < < < < < < < %= A= = = = = = = = = = = = = = = = = ijijįįijĨĠĕĠv h~ mH nH uj hK Uh~ h{d h~ j hK Uj h7 A U h? h7 A h h? h0
|
a 5he h0
|
a 5he h0
|
a h7 A hh h 5CJ \ h~ 5CJ \mH nH uh{d h 5CJ \ j h{d h 5CJ U\ .< < < f= > >
|
a h7 A hh h 5CJ \ h~ 5CJ \mH nH uh{d h 5CJ \ j h{d h 5CJ U\ .< < < f= > >
|
> (> _? `? ? '@ @ @ A eA B >C ^C D D D `E E ! ! ! } ! } ! ! ! ! ! ! ! } ! } ! ! ! ! ! ! ! ! ! } ! }
|
> (> _? `? ? '@ @ @ A eA B >C ^C D D D `E E ! ! ! } ! } ! ! ! ! ! ! ! } ! } ! ! ! ! ! ! ! ! ! } ! }
|
& FN gd3G gd3G
|
& FN gd3G gd3G
|
& FN gdUHW
|
& FN gdUHW
|
& FN gd gd gd gd7 A
|
& FN gd gd gd gd7 A
|
& FM gd7 A gd? = = >
|
& FM gd7 A gd? = = >
|
> > > > > '> (> i> > > > ,? -? F? G? H? J? K? d? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ @ @ @ @ O@ P@ e@ f@ g@ k@ l@ @ ѽ뱭뱭~~ h P h~ j h Uj h~ U h{d h~ j h~ Uh~ j h~ UhUHW h~ mH nH uj h Uj h U h? h^#e h^#e h{d h h h h7 A j h7 A U 1@ @ @ @ @ @ @ @ @ @ @ @ @ eA A rB sB B B B B B B B B B B B B B B B B B =C >C @C CC DC EC ]C ^C C C C &D cD dD }D ~D D D D нȹЧۣИІ j h3G U h? h^#e h^#e h{d h h
|
> > > > > '> (> i> > > > ,? -? F? G? H? J? K? d? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ @ @ @ @ O@ P@ e@ f@ g@ k@ l@ @ ѽ뱭뱭~~ h P h~ j h Uj h~ U h{d h~ j h~ Uh~ j h~ UhUHW h~ mH nH uj h Uj h U h? h^#e h^#e h{d h h h h7 A j h7 A U 1@ @ @ @ @ @ @ @ @ @ @ @ @ eA A rB sB B B B B B B B B B B B B B B B B B =C >C @C CC DC EC ]C ^C C C C &D cD dD }D ~D D D D нȹЧۣИІ j h3G U h? h^#e h^#e h{d h h
|
E E E $E %E &E .E /E HE IE JE LE ME E E E E E E E E E E E E E E E E E E E E E F G G G G G G G G G G G G G H ° jN h3G U h
|
E E E $E %E &E .E /E HE IE JE LE ME E E E E E E E E E E E E E E E E E E E E E F G G G G G G G G G G G G G H ° jN h3G U h
|
Z ! H ! H ! H ! H ! ! ! H ! H ! !
|
Z ! H ! H ! H ! H ! ! ! H ! H ! !
|
& FQ gdG
|
& FQ gdG
|
& FQ gdG
|
& FQ gdG
|
& FQ gde gdK~
|
& FQ gde gdK~
|
& FN gde
|
& FN gde
|
& FN gdK~
|
& FN gdK~
|
& FN gdG gdG gdJ? gd gd3G H H H H
|
& FN gdG gdG gdJ? gd gd3G H H H H
|
H ~H H H H H H H H H H H H H H H H H H H H I I I I I I I J J VJ J J J J J J J EK yK K OL PL QL RL aL hL iL L L ļļļߣ j h hJ? 5CJ U h hJ? 5CJ j h h6oR 5U h h P he hK~ h0
|
H ~H H H H H H H H H H H H H H H H H H H H I I I I I I I J J VJ J J J J J J J EK yK K OL PL QL RL aL hL iL L L ļļļߣ j h hJ? 5CJ U h hJ? 5CJ j h h6oR 5U h h P he hK~ h0
|
a hG he h h{d hJ? hJ? h h3G h~ mH nH uj h3G Ujɔ h3G U 5K OL PL SL TL UL VL WL XL YL ZL [L \L ]L ^L _L `L aL L L L L L L L L L ! } ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! gd $a$gd gdG
|
a hG he h h{d hJ? hJ? h h3G h~ mH nH uj h3G Ujɔ h3G U 5K OL PL SL TL UL VL WL XL YL ZL [L \L ]L ^L _L `L aL L L L L L L L L L ! } ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! gd $a$gd gdG
|
& FQ gdK~ L L L L L L L L L L L L L L L L L L L L L L L M M M M $M M M M N N N N O O O O O P 'P 3P 5P tP vP P Q R R (R 6R @R `R vR »·¤¤¤ hP hv1 h P h6oR h P h6oR h~ he h h{d hK~ hK~ h h h
hv1 5CJ h hK~ 5CJ h hJ? 5CJ j h hJ? 5CJ U*h~ 5CJ mH nH u* 6L L L L M M M M N N *O =O RO O (P )P tP P P P P bQ Q ! ! ! ! ! H ! H ! ! ! ! ! H ! H ! H ! } ! ! ! H ! H ! H ! ! !
|
& FQ gdK~ L L L L L L L L L L L L L L L L L L L L L L L M M M M $M M M M N N N N O O O O O P 'P 3P 5P tP vP P Q R R (R 6R @R `R vR »·¤¤¤ hP hv1 h P h6oR h P h6oR h~ he h h{d hK~ hK~ h h h
hv1 5CJ h hK~ 5CJ h hJ? 5CJ j h hJ? 5CJ U*h~ 5CJ mH nH u* 6L L L L M M M M N N *O =O RO O (P )P tP P P P P bQ Q ! ! ! ! ! H ! H ! ! ! ! ! H ! H ! H ! } ! ! ! H ! H ! H ! ! !
|
& FQ gdv1
|
& FQ gdv1
|
& FQ gdv1
|
& FQ gdv1
|
& FQ gd P
|
& FQ gd P
|
& FN gd P gd P gd P
|
& FN gd P gd P gd P
|
& F[ gd gdK~ gdK~ gd Q Q uR vR xR yR zR {R |R }R ~R R R R R R R R R R R R R R R R ! !
|
& F[ gd gdK~ gdK~ gd Q Q uR vR xR yR zR {R |R }R ~R R R R R R R R R R R R R R R R ! !
|
Z ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! $a$gdv1 gdK~
|
Z ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! $a$gdv1 gdK~
|
& FQ gd P
|
& FQ gd P
|
& FQ gdv1 vR wR R R R R R R R R R R R R R R R R R R R R /W 0W ?W FW GW ]W ^W _W `W bW zW {W }W ~W Ƿvvf_[ hN
hhU 5CJ j h hhU 5CJ U* j h hhU 5CJ U h hhU 5CJ j h#I UmH nH u h h P hhU hhU hJ?
hv1 5CJ j h hv1 5CJ U*h~ 5CJ mH nH u* j h hv1 5CJ U h hv1 5CJ h P j h0% UmH nH u#R R R R S T T ?T T T T 6U yU U U V WV tV (W )W *W +W ,W -W .W /W ! ! ! ! H ! H ! H ! } ! H ! ! ! H ! H ! ! ! ! !
|
& FQ gdv1 vR wR R R R R R R R R R R R R R R R R R R R R /W 0W ?W FW GW ]W ^W _W `W bW zW {W }W ~W Ƿvvf_[ hN
hhU 5CJ j h hhU 5CJ U* j h hhU 5CJ U h hhU 5CJ j h#I UmH nH u h h P hhU hhU hJ?
hv1 5CJ j h hv1 5CJ U*h~ 5CJ mH nH u* j h hv1 5CJ U h hv1 5CJ h P j h0% UmH nH u#R R R R S T T ?T T T T 6U yU U U V WV tV (W )W *W +W ,W -W .W /W ! ! ! ! H ! H ! H ! } ! H ! ! ! H ! H ! ! ! ! !
|
Z ! ! ! ! ! ! !
|
Z ! ! ! ! ! ! !
|
& FQ gdhU
|
& FQ gdhU
|
& FQ gdhU
|
& FQ gdhU
|
& FN gdhU gdhU gdhU gd /W 1W 2W 3W 4W 5W 6W 7W 8W 9W :W ;W W ?W {W |W }W W nX pX }X X ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! s ] s _ $If gdqt gd#I gd#I $a$gdhU gdhU ~W W W W W W W W W X 6X =X IX MX mX oX pX |X }X X X X X X X X X X X X X +Y ,Y -Y .Y :Y CY _Y `Y aY gY hY }Y ~Y Y Y Y Y Y Y Y Y Z 鈄h: h<*> hI
5CJ \ h~ 5CJ \mH nH u* j h{d hI
5CJ U\h{d hI
5CJ \ hI
hI
h{d hI
\h{d hI
5\ h{d hI
hNQc h=A hI
hqt h h{d h#I h#I 4X X X X X c Z s Z ] s Z ] s _ $If gdN kdD $$If l 44 n0 5
|
& FN gdhU gdhU gdhU gd /W 1W 2W 3W 4W 5W 6W 7W 8W 9W :W ;W W ?W {W |W }W W nX pX }X X ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! s ] s _ $If gdqt gd#I gd#I $a$gdhU gdhU ~W W W W W W W W W X 6X =X IX MX mX oX pX |X }X X X X X X X X X X X X X +Y ,Y -Y .Y :Y CY _Y `Y aY gY hY }Y ~Y Y Y Y Y Y Y Y Y Z 鈄h: h<*> hI
5CJ \ h~ 5CJ \mH nH u* j h{d hI
5CJ U\h{d hI
5CJ \ hI
hI
h{d hI
\h{d hI
5\ h{d hI
hNQc h=A hI
hqt h h{d h#I h#I 4X X X X X c Z s Z ] s Z ] s _ $If gdN kdD $$If l 44 n0 5
|
t & & 0 4
|
t & & 0 4
|
l `
|
l `
|
aef4p & & X X X X X i ` s ` ] s ` ] s _ $If gdN kd` $$If l 0 5
|
aef4p & & X X X X X i ` s ` ] s ` ] s _ $If gdN kd` $$If l 0 5
|
t 0 4
|
t 0 4
|
l `
|
l `
|
aep X X X
Y +Y i ` s ` ] s ` ] s _ $If gdN kdM $$If l 0 5
|
aep X X X
Y +Y i ` s ` ] s ` ] s _ $If gdN kdM $$If l 0 5
|
t 0 4
|
t 0 4
|
l `
|
l `
|
aep +Y ,Y .Y DY _Y i ` s ` ] s ` ] s _ $If gdN kd: $$If l 0 5
|
aep +Y ,Y .Y DY _Y i ` s ` ] s ` ] s _ $If gdN kd: $$If l 0 5
|
t 0 4
|
t 0 4
|
l `
|
l `
|
aep _Y `Y aY Y Y @Z AZ [ [ \ i d ! \ W ! W ! W ! R ! W ! R gd<*> gd $a$gdI
gdI
kd' $$If l 0 5
|
aep _Y `Y aY Y Y @Z AZ [ [ \ i d ! \ W ! W ! W ! R ! W ! R gd<*> gd $a$gdI
gdI
kd' $$If l 0 5
|
t 0 4
|
t 0 4
|
l `
|
l `
|
aep Z ?Z @Z AZ MZ SZ {[ [ [ [ \ \ *\ +\ ,\ -\ 0\ 1\ 2\ H\ I\ R\ S\ l\ m\ n\ p\ q\ \ \ \ \ \ ] Q] ] ] ] ] m_ n_ _ _ _ ļļIJԜ|q| j
|
aep Z ?Z @Z AZ MZ SZ {[ [ [ [ \ \ *\ +\ ,\ -\ 0\ 1\ 2\ H\ I\ R\ S\ l\ m\ n\ p\ q\ \ \ \ \ \ ] Q] ] ] ] ] m_ n_ _ _ _ ļļIJԜ|q| j
|
h=A Uj h=A Uh=A h
|
h=A Uj h=A Uh=A h
|
h: 5 h
|
h: 5 h
|
h: hS h~ mH nH u* j h<*> Uj h<*> U* h{d h~ * h~ *j h<*> Uj h<*> U h<*> 5 h
|
h: hS h~ mH nH u* j h<*> Uj h<*> U* h{d h~ * h~ *j h<*> Uj h<*> U h<*> 5 h
|
h<*> h: h<*> h
|
h<*> h: h<*> h
|
5 h
|
5 h
|
h
|
h
|
hd +\ \ ] ] ] ^ %^ >^ ^ ^ ^ '_ [_ _ i` j` l` n` o` p` q` r` s` t` u` v` w` ! ! ! ! ! ! H ! H ! H ! H ! ! ! H ! } ! ! ! ! ! ! ! ! ! ! !
|
hd +\ \ ] ] ] ^ %^ >^ ^ ^ ^ '_ [_ _ i` j` l` n` o` p` q` r` s` t` u` v` w` ! ! ! ! ! ! H ! H ! H ! H ! ! ! H ! } ! ! ! ! ! ! ! ! ! ! !
|
& FQ gd=A
|
& FQ gd=A
|
& FN gd=A gd=A gd gd<*> _ _ _ _ _ _ _ _ _ _ _ j` k` l` m` |` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` a ̼ԸԪԠslhd`YdY`Y` h{d hK hK h#2 h ,A
h=A 5CJ j h h=A 5CJ U*h~ 5CJ mH nH u* j h h=A 5CJ U h h=A 5CJ j ha Aa Za wa a a a a a a a a a a a a a a "b #b 9b :b Bb Cb Sb Tb Ub yb zb b b b b b b b b b b b c c c %c &c
|
& FN gd=A gd=A gd gd<*> _ _ _ _ _ _ _ _ _ _ _ j` k` l` m` |` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` a ̼ԸԪԠslhd`YdY`Y` h{d hK hK h#2 h ,A
h=A 5CJ j h h=A 5CJ U*h~ 5CJ mH nH u* j h h=A 5CJ U h h=A 5CJ j ha Aa Za wa a a a a a a a a a a a a a a "b #b 9b :b Bb Cb Sb Tb Ub yb zb b b b b b b b b b b b c c c %c &c
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d d h{d hNy hNy hr< h{d h~ h{d h hFX h{d hr< h~ h{d hK h hK h| Jb b b c c &c =c Wc Xc |c c c c c c d d d d !d "d ;e Je e e e x x x x x x x x x x x x x ! ! ! ! ! ! } ! H !
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d d h{d hNy hNy hr< h{d h~ h{d h hFX h{d hr< h~ h{d hK h hK h| Jb b b c c &c =c Wc Xc |c c c c c c d d d d !d "d ;e Je e e e x x x x x x x x x x x x x ! ! ! ! ! ! } ! H !
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& FN gdNy gdNy gdNy , gdr< gdr< , d d d !d "d *d Hd [d d d d d d d e e e e e e e e f f f f f f Df Ef tf f f >g @g Eg Fg h h h i i i Hi Ii Pi i i i i i i i i i i j
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& FN gdNy gdNy gdNy , gdr< gdr< , d d d !d "d *d Hd [d d d d d d d e e e e e e e e f f f f f f Df Ef tf f f >g @g Eg Fg h h h i i i Hi Ii Pi i i i i i i i i i i j
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j nk pk k ƿޠ h[3 hL H* h) h h) h) h) h) 5 h{d h F h F h[3 h[3 H*h[3 h< hu e hL h P hL h7 hH h{d hNy hNy h)
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j nk pk k ƿޠ h[3 hL H* h) h h) h) h) h) 5 h{d h F h F h[3 h[3 H*h[3 h< hu e hL h P hL h7 hH h{d hNy hNy h)
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j j Jj sj k _m m m m m n n ! ! ! ! H !
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j j Jj sj k _m m m m m n n ! ! ! ! H !
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Z ! _ ! ! ! ! ! ! ! H ! ! _ ! } ! ! ! ! ! gd)
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Z ! _ ! ! ! ! ! ! ! H ! ! _ ! } ! ! ! ! ! gd)
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& Fa gdL gdL ^ ` gd F gdr< gd F
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& Fa gdL gdL ^ ` gd F gdr< gd F
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& Fa gd< gdNy gdL k k k k m m _m m m m m n Sn nn n n n n n n n n n n n o o o p p p p q q Eq Fq Pq Qq q q q q q r r 7r hr jr r r r r r r r r r s s s &s /s s h.2 hr h_Q h+^q h\ h{d hh hh h#2 h{d h
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& Fa gd< gdNy gdL k k k k m m _m m m m m n Sn nn n n n n n n n n n n n o o o p p p p q q Eq Fq Pq Qq q q q q q r r 7r hr jr r r r r r r r r r s s s &s /s s h.2 hr h_Q h+^q h\ h{d hh hh h#2 h{d h
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h
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h
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h{d h^ZJ h^ZJ h) h) h) h) 5h F h7 hL hL hL H* @n n n p p q q =q Qq Rq q jr kr r r r r r r Hs s t ! ! ! ! ! ! ! ! ! ! ! ! H ! H ! H ! H ! ! ! }
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h{d h^ZJ h^ZJ h) h) h) h) 5h F h7 hL hL hL H* @n n n p p q q =q Qq Rq q jr kr r r r r r r Hs s t ! ! ! ! ! ! ! ! ! ! ! ! H ! H ! H ! H ! ! ! }
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& Fb gd\
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& Fb gd\
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& FX gd_Q
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& FX gd_Q
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& FX gdh
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& FX gdh
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& FX gd+^q gd+^q gd_Q gd\ gdh gd
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& FX gd+^q gd+^q gd_Q gd\ gdh gd
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gd^ZJ gd^ZJ s s t t 0t 1t 2t 4t 5t 6t Et Ft Wt Xt qt rt st ut vt t t t t t t t t t t t t t u -u .u 9u :u =u >u lu mu zu {u ~u u u u u u u u u u u u u u h{d h x \h{d h x 5\ h{d h x h+^q h x hr h~ mH nH u* j{ h\ Uj h\ U* h~ *h{d h~ *j hO Uj h\ Uh\ h? h\ 8t t t t t t t ! ! s s ] s _ $If gd x gd+^q h^hgdr t t t u -u E < s < s < ] s _ $If gd x kd $$If l 44 nF ~ 1f!} 5
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gd^ZJ gd^ZJ s s t t 0t 1t 2t 4t 5t 6t Et Ft Wt Xt qt rt st ut vt t t t t t t t t t t t t t u -u .u 9u :u =u >u lu mu zu {u ~u u u u u u u u u u u u u u h{d h x \h{d h x 5\ h{d h x h+^q h x hr h~ mH nH u* j{ h\ Uj h\ U* h~ *h{d h~ *j hO Uj h\ Uh\ h? h\ 8t t t t t t t ! ! s s ] s _ $If gd x gd+^q h^hgdr t t t u -u E < s < s < ] s _ $If gd x kd $$If l 44 nF ~ 1f!} 5
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t & & & 0 e 4
|
t & & & 0 e 4
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l `
|
l `
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amf4p & & & -u .u :u >u lu K B s B s B ] s _ $If gd x kdL $$If l F ~ 1f! } 5
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amf4p & & & -u .u :u >u lu K B s B s B ] s _ $If gd x kdL $$If l F ~ 1f! } 5
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t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp lu mu {u u u K B s B s B ] s _ $If gd x kde $$If l F ~ 1f! } 5
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amp lu mu {u u u K B s B s B ] s _ $If gd x kde $$If l F ~ 1f! } 5
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t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp u u u u u K B s B s B ] s _ $If gd x kd~ $$If l F ~ 1f! } 5
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amp u u u u u K B s B s B ] s _ $If gd x kd~ $$If l F ~ 1f! } 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp u u u u +v K B s B s B ] s _ $If gd x kd $$If l F ~ 1f! } 5
|
amp u u u u +v K B s B s B ] s _ $If gd x kd $$If l F ~ 1f! } 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp u +v ,v 6v 7v :v ;v jv kv wv xv {v |v v v v v v v v v v v w w w w
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amp u +v ,v 6v 7v :v ;v jv kv wv xv {v |v v v v v v v v v v v w w w w
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w w w
w w w *w +w Sw \w w x 0x 3x Hx `x ax vx wx xx ᢞuj h$0 Uj h$0 U h? h9t( h$0 h{d h9t( h9t( hwm h+^q h x 5CJ \ "j h{d h x 5CJ U\* h~ 5CJ \mH nH u* j h{d h x 5CJ U\h{d h x 5CJ \ h{d h x h{d h x \h x .+v ,v 7v ;v jv K B s B s B ] s _ $If gd x kd $$If l F ~ 1f! } 5
|
w w w
w w w *w +w Sw \w w x 0x 3x Hx `x ax vx wx xx ᢞuj h$0 Uj h$0 U h? h9t( h$0 h{d h9t( h9t( hwm h+^q h x 5CJ \ "j h{d h x 5CJ U\* h~ 5CJ \mH nH u* j h{d h x 5CJ U\h{d h x 5CJ \ h{d h x h{d h x \h x .+v ,v 7v ;v jv K B s B s B ] s _ $If gd x kd $$If l F ~ 1f! } 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp jv kv xv |v v K B s B s B ] s _ $If gd x kdɣ $$If l F ~ 1f! } 5
|
amp jv kv xv |v v K B s B s B ] s _ $If gd x kdɣ $$If l F ~ 1f! } 5
|
t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp v v v w w w K F ! > F ! 9 ! gd{ $a$gd x gd+^q kd $$If l F ~ 1f! } 5
|
amp v v v w w w K F ! > F ! 9 ! gd{ $a$gd x gd+^q kd $$If l F ~ 1f! } 5
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t 0 e 4
|
t 0 e 4
|
l `
|
l `
|
amp w +w x x x y Hz Iz z u{ { { } } } k~ > + ! ! ! ! ! ! ! ! ! ! ! ! ! ! }
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amp w +w x x x y Hz Iz z u{ { { } } } k~ > + ! ! ! ! ! ! ! ! ! ! ! ! ! ! }
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& Fc gd*C gd*C gd*C gd$0
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& Fc gd*C gd*C gd*C gd$0
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& FN gd9t( gd9t( gd9t( xx zx {x |x x x x x x x x x x x y y ,y -y .y Cy Dy Ey Hy Iy Jy Ky iy jy ky sy ty y y y y y y y y y y y y y ¾v j hLv Uh%/ h~ mH nH ujl hLv U hLv h9t( h{d h~ h~ j hLv Uj hLv UhLv h9t( h~ mH nH u* jv h$0 Uj h$0 Uh$0 j h$0 U* h~ *h{d h~ * +y y y y y y y z
z z z z 0z 1z 2z 4z 5z Fz Iz [z kz {z |z }z z z z z z z z z { { { { { { { { { { { { { | | $} %} :} ;} <} >} ?} @} O} P} a} b} ʿʿʿʿʿʻʿʻʴʴʴ h{d h~ jݨ h$0 Uj h$0 U h? h$0 h{d h9t( h%/ h$0 h
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& FN gd9t( gd9t( gd9t( xx zx {x |x x x x x x x x x x x y y ,y -y .y Cy Dy Ey Hy Iy Jy Ky iy jy ky sy ty y y y y y y y y y y y y y ¾v j hLv Uh%/ h~ mH nH ujl hLv U hLv h9t( h{d h~ h~ j hLv Uj hLv UhLv h9t( h~ mH nH u* jv h$0 Uj h$0 Uh$0 j h$0 U* h~ *h{d h~ * +y y y y y y y z
z z z z 0z 1z 2z 4z 5z Fz Iz [z kz {z |z }z z z z z z z z z { { { { { { { { { { { { { | | $} %} :} ;} <} >} ?} @} O} P} a} b} ʿʿʿʿʿʻʿʻʴʴʴ h{d h~ jݨ h$0 Uj h$0 U h? h$0 h{d h9t( h%/ h$0 h
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~ ~ ~ ~ ~ ~ /~ 0~ 1~ 9~ :~ S~ T~ U~ W~ X~ Y~ i~ w~ }~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ѾɺܬѡѬܝђɋѬ h P h~ jɪ hU Uh%/ jN hU U hU h9t( h{d h~ h~ jө hU Uj hU UhU h$0 h$0 h9t( h~ mH nH uj h$0 UjX h$0 Uh$0 4~ ~ ~ ~ ~ " 2 B C D t d q r v | E a ҁ Ӂ ԁ ց ׁ ؾ j: h*C Uh~ h{d h~ j h*C Uj h*C U h? h*C h{d h*C h*C hh h%/ h$0 h$0 h$0 h
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~ ~ ~ ~ ~ ~ /~ 0~ 1~ 9~ :~ S~ T~ U~ W~ X~ Y~ i~ w~ }~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ѾɺܬѡѬܝђɋѬ h P h~ jɪ hU Uh%/ jN hU U hU h9t( h{d h~ h~ jө hU Uj hU UhU h$0 h$0 h9t( h~ mH nH uj h$0 UjX h$0 Uh$0 4~ ~ ~ ~ ~ " 2 B C D t d q r v | E a ҁ Ӂ ԁ ց ׁ ؾ j: h*C Uh~ h{d h~ j h*C Uj h*C U h? h*C h{d h*C h*C hh h%/ h$0 h$0 h$0 h
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& FN gd*C gd*C
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& FN gd*C gd*C
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& Fc gd*C v w x Є ӄ F L g h i j k l 2 ʇ ˇ Z _ i j ʿʿʸʸʸʸʱʩʞʩʌΩ hU hU j h*C U h{d h~ j h*C Uj h*C U h? h*C h{d h*C h%/ h ? H Q \ ] ^ f g \ b 0 1 3 4 5 6 9 : ; J K T U l v { L V X c g t һݷ h%/ hMX hMX h%/ h%/ h,< h{ hl h{d hh hJv
hh h%/ h
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& Fc gd*C v w x Є ӄ F L g h i j k l 2 ʇ ˇ Z _ i j ʿʿʸʸʸʸʱʩʞʩʌΩ hU hU j h*C U h{d h~ j h*C Uj h*C U h? h*C h{d h*C h%/ h ? H Q \ ] ^ f g \ b 0 1 3 4 5 6 9 : ; J K T U l v { L V X c g t һݷ h%/ hMX hMX h%/ h%/ h,< h{ hl h{d hh hJv
hh h%/ h
|
Z ! H ! H ! H ! ! ! H ! H ! ! ! } ! ! ! ! ! gdh
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Z ! H ! H ! H ! ! ! H ! H ! ! ! } ! ! ! ! ! gdh
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& FQ gdt
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& FQ gdt
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& FQ gdMX
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& FQ gdMX
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& FQ gdMX
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& FQ gdMX
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& FN gdMX gdMX gd%/ t D P ؐ
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& FN gdMX gdMX gd%/ t D P ؐ
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! " # % ) * . / 9 F J K L M N O P _ ` ƒ ֒ Ɠ Ǔ ȓ ݓ ɻؤؤؤ𠙕{ j hU U hU hU hU h P hX h#M h{d hX hX
h5K 5CJ j h h5K 5CJ U*h~ 5CJ mH nH u* j h h5K 5CJ U h h5K 5CJ j hX UmH nH u h5K hh ht hMX - F G H I ` R ֒ ג . ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! H ! H ! ! ! ! gdX
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! " # % ) * . / 9 F J K L M N O P _ ` ƒ ֒ Ɠ Ǔ ȓ ݓ ɻؤؤؤ𠙕{ j hU U hU hU hU h P hX h#M h{d hX hX
h5K 5CJ j h h5K 5CJ U*h~ 5CJ mH nH u* j h h5K 5CJ U h h5K 5CJ j hX UmH nH u h5K hh ht hMX - F G H I ` R ֒ ג . ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! H ! H ! ! ! ! gdX
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& F[ gdX gdX gdX $a$gd5K gdh . j m ( ) # w & ' r ̖ + ӗ ԗ ! H ! ! ! ! H ! H ! H ! } ! ! ! ! ! H ! H ! ! ! H ! ! !
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& F[ gdX gdX gdX $a$gd5K gdh . j m ( ) # w & ' r ̖ + ӗ ԗ ! H ! ! ! ! H ! H ! H ! } ! ! ! ! ! H ! H ! ! ! H ! ! !
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Z !
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Z !
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& FQ gd0%
|
& FQ gd0%
|
& FQ gdX
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& FQ gdX
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& FN gd0%
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& FN gd0%
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& FN gd0%
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& FN gd0%
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& FN gdX gdX h^hgdX
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& FN gdX gdX h^hgdX
|
& Fe gdX ݓ ޓ ߓ ! " # % & w y % + p v ԗ " # ' ųũ|unu
h0% 5CJ
hX 5CJ j h hX 5CJ U*h~ 5CJ mH nH u* j h hX 5CJ U h hX 5CJ j hX UmH nH u h0% hX h~ mH nH uj hU UhU h{d h~ h~ j hU Ujo hU U *ԗ ֗ ח ؗ ٗ ڗ ۗ ܗ ݗ ޗ ߗ # $ % & ' L M ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! H
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& Fe gdX ݓ ޓ ߓ ! " # % & w y % + p v ԗ " # ' ųũ|unu
h0% 5CJ
hX 5CJ j h hX 5CJ U*h~ 5CJ mH nH u* j h hX 5CJ U h hX 5CJ j hX UmH nH u h0% hX h~ mH nH uj hU UhU h{d h~ h~ j hU Ujo hU U *ԗ ֗ ח ؗ ٗ ڗ ۗ ܗ ݗ ޗ ߗ # $ % & ' L M ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! H
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& Fe gdLs gdLs ^ ` gdLs $a$gdX gdX ' ) * + , - . 7 ; @ L M 3 4 7 8 > ? @ U V W Z [ \ ] u v t 2 7 ֛ ޛ J ݜ ĽĽө h hX 5CJ j hX UmH nH u h.2 h~ mH nH uj hU U h{d h~ h~ je hU Uj hU U hU hU hU hLs hU hLs hX h#M h P hX 2 t C ԛ = J ! ! ! ! H ! H ! H ! ! ! } ! H ! ! ! H ! H ! ! !
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& Fe gdLs gdLs ^ ` gdLs $a$gdX gdX ' ) * + , - . 7 ; @ L M 3 4 7 8 > ? @ U V W Z [ \ ] u v t 2 7 ֛ ޛ J ݜ ĽĽө h hX 5CJ j hX UmH nH u h.2 h~ mH nH uj hU U h{d h~ h~ je hU Uj hU U hU hU hU hLs hU hLs hX h#M h P hX 2 t C ԛ = J ! ! ! ! H ! H ! H ! ! ! } ! H ! ! ! H ! H ! ! !
|
Z !
|
Z !
|
& FQ gdLs
|
& FQ gdLs
|
& FQ gdLs
|
& FQ gdLs
|
& FQ gdX gdX
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& FQ gdX gdX
|
& FN gdLs
|
& FN gdLs
|
& FN gdLs
|
& FN gdLs
|
& FN gdX gdLs
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& FN gdX gdLs
|
& Fe gdLs h^hgdLs
|
& Fe gdLs h^hgdLs
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K L M N n
G e ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! gd#M gd#M gdh $a$gdX gdX ) * + , . 6 : J K M N R S T U r | R V \ ` h k t w
3 ; H X r x »緳 h{d h~ h~ j[ h#M Uj h#M Uh.2 h{d h#M h#M hh hX
hLs 5CJ
hX 5CJ j h hX 5CJ U*h~ 5CJ mH nH u*h hX 5CJ j h hX 5CJ U4 % & ? @ A C D Ǡ Ƞ Ѡ Ҡ d f i j k l { | ơ ݡ 娡塝j h'Z! U h{d h? h'Z! h{d h>5 h>5 h{d h#M j̶ h@H UjQ h@H Uj h@H Uh~ mH nH ujֵ h#M Uh#M h@H j h#M U h{d h~ h~ 8e f | * + D n o ݦ ! ! ! ! } ! ! ! ! ! ! ! ! ! ! ! gd? gdS; gdU C
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K L M N n
G e ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! gd#M gd#M gdh $a$gdX gdX ) * + , . 6 : J K M N R S T U r | R V \ ` h k t w
3 ; H X r x »緳 h{d h~ h~ j[ h#M Uj h#M Uh.2 h{d h#M h#M hh hX
hLs 5CJ
hX 5CJ j h hX 5CJ U*h~ 5CJ mH nH u*h hX 5CJ j h hX 5CJ U4 % & ? @ A C D Ǡ Ƞ Ѡ Ҡ d f i j k l { | ơ ݡ 娡塝j h'Z! U h{d h? h'Z! h{d h>5 h>5 h{d h#M j̶ h@H UjQ h@H Uj h@H Uh~ mH nH ujֵ h#M Uh#M h@H j h#M U h{d h~ h~ 8e f | * + D n o ݦ ! ! ! ! } ! ! ! ! ! ! ! ! ! ! ! gd? gdS; gdU C
|
& F gdS; C
|
& F gdS; C
|
& F gd'Z! C gd'Z! gd? gd>5 gd#M * + 4 5 N O P R S d p Ϣ Ӣ ( * ޣ ߣ " # < = > @ A ÿ⨷η j3 hU Uj hU Uh~ j= hU Uj hU UhU hS; h{d h? h~ mH nH uj· h\ U h{d h~ j h'Z! UjG h\ Uh'Z! 9 Ĥ Ť Τ Ϥ C k r s t u Υ ҥ w x զ ֦ צ ٦ ڦ $ % : ; < = > ? @ A B ] ^ ÿѸѸѸѸ j hU Uj hU Uj) hU U h{d h? h#M h{d hS; hS; hS; hS; h~ mH nH uj hU UhU j hU U h{d h~ h~ ;^ g h . / > n © # A \ w x ê 4 5 J K L S T e f o p ҽҶү˨}vv h{d h~ j h{d h&{ Uj h{d hlN9 U h^#e h^#e h^#e h{d hlN9 h{d hQ h{d h4g h{d hJR h{d hrE h{d hwe h{d h$' h{d h h{d hPm h~ mH nH uj hU Uj hU UhU . O / n ê n o q s ! D ! ! ! ! } ! H ! H ! H ! H ! ! ! H ! } ! ! . # gd7
|
& F gd'Z! C gd'Z! gd? gd>5 gd#M * + 4 5 N O P R S d p Ϣ Ӣ ( * ޣ ߣ " # < = > @ A ÿ⨷η j3 hU Uj hU Uh~ j= hU Uj hU UhU hS; h{d h? h~ mH nH uj· h\ U h{d h~ j h'Z! UjG h\ Uh'Z! 9 Ĥ Ť Τ Ϥ C k r s t u Υ ҥ w x զ ֦ צ ٦ ڦ $ % : ; < = > ? @ A B ] ^ ÿѸѸѸѸ j hU Uj hU Uj) hU U h{d h? h#M h{d hS; hS; hS; hS; h~ mH nH uj hU UhU j hU U h{d h~ h~ ;^ g h . / > n © # A \ w x ê 4 5 J K L S T e f o p ҽҶү˨}vv h{d h~ j h{d h&{ Uj h{d hlN9 U h^#e h^#e h^#e h{d hlN9 h{d hQ h{d h4g h{d hJR h{d hrE h{d hwe h{d h$' h{d h h{d hPm h~ mH nH uj hU Uj hU UhU . O / n ê n o q s ! D ! ! ! ! } ! H ! H ! H ! H ! ! ! H ! } ! ! . # gd7
|
& FK gdlN9 gdQ C
|
& FK gdlN9 gdQ C
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F Microsoft Word Document
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MSWordDoc Word.Document.8 9q
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MSWordDoc Word.Document.8 9q
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Debug Support for Bender Title 8 @ _PID_HLINKS A | 7
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Debug Support for Bender Title 8 @ _PID_HLINKS A | 7
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