//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tap_top.v ////
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//// tap_top.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000, 2001, 2002 Authors ////
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//// Copyright (C) 2000, 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
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//// ////
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//// ////
|
//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/04/22 12:55:56 mohor
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// Revision 1.6 2002/04/22 12:55:56 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
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// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
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//
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//
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// Revision 1.5 2002/03/26 14:23:38 mohor
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// Revision 1.5 2002/03/26 14:23:38 mohor
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// Signal tdo_padoe_o changed back to tdo_padoen_o.
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// Signal tdo_padoe_o changed back to tdo_padoen_o.
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//
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//
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// Revision 1.4 2002/03/25 13:16:15 mohor
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// Revision 1.4 2002/03/25 13:16:15 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
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// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
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// not named correctly.
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// not named correctly.
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//
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//
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// Revision 1.3 2002/03/12 14:30:05 mohor
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// Revision 1.3 2002/03/12 14:30:05 mohor
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// Few outputs for boundary scan chain added.
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// Few outputs for boundary scan chain added.
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//
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//
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// Revision 1.2 2002/03/12 10:31:53 mohor
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// Revision 1.2 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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// logic necessery for debugging.
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//
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//
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// Revision 1.1 2002/03/08 15:28:16 mohor
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// Revision 1.1 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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// Structure changed. Hooks for jtag chain added.
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//
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//
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//
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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|
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// Top module
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// Top module
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module tap_top(
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module tap_top(
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// JTAG pins
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// JTAG pins
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
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|
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// TAP states
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// TAP states
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
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|
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// Instructions
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// Instructions
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
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|
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// TDO from dbg module
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// TDO from dbg module
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TDOData_dbg, BypassRegister,
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TDOData_dbg, BypassRegister,
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|
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// From Boundary Scan Chain
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// From Boundary Scan Chain
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bs_chain_i
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bs_chain_i
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|
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);
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);
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|
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parameter Tp = 1;
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parameter Tp = 1;
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|
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// JTAG pins
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// JTAG pins
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input tms_pad_i; // JTAG test mode select pad
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input tms_pad_i; // JTAG test mode select pad
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input tck_pad_i; // JTAG test clock pad
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input tck_pad_i; // JTAG test clock pad
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input trst_pad_i; // JTAG test reset pad
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input trst_pad_i; // JTAG test reset pad
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input tdi_pad_i; // JTAG test data input pad
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input tdi_pad_i; // JTAG test data input pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_padoe_o; // Output enable for JTAG test data output pad
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output tdo_padoe_o; // Output enable for JTAG test data output pad
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// TAP states
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// TAP states
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output ShiftDR;
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output ShiftDR;
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output Exit1DR;
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output Exit1DR;
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output UpdateDR;
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output UpdateDR;
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output UpdateDR_q;
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output UpdateDR_q;
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output CaptureDR;
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output CaptureDR;
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// Instructions
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// Instructions
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output IDCODESelected;
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output IDCODESelected;
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output CHAIN_SELECTSelected;
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output CHAIN_SELECTSelected;
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output DEBUGSelected;
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output DEBUGSelected;
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output EXTESTSelected;
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output EXTESTSelected;
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input TDOData_dbg;
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input TDOData_dbg;
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output BypassRegister;
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output BypassRegister;
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// From Boundary Scan Chain
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// From Boundary Scan Chain
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input bs_chain_i;
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input bs_chain_i;
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|
|
|
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reg tdo_pad_o;
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reg tdo_pad_o;
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// TAP states
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// TAP states
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reg TestLogicReset;
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reg TestLogicReset;
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reg RunTestIdle;
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reg RunTestIdle;
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reg SelectDRScan;
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reg SelectDRScan;
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reg CaptureDR;
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reg CaptureDR;
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reg ShiftDR;
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reg ShiftDR;
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reg Exit1DR;
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reg Exit1DR;
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reg PauseDR;
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reg PauseDR;
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reg Exit2DR;
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reg Exit2DR;
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reg UpdateDR;
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reg UpdateDR;
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|
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reg SelectIRScan;
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reg SelectIRScan;
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reg CaptureIR;
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reg CaptureIR;
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reg ShiftIR;
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reg ShiftIR;
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reg Exit1IR;
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reg Exit1IR;
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reg PauseIR;
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reg PauseIR;
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reg Exit2IR;
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reg Exit2IR;
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reg UpdateIR;
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reg UpdateIR;
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// Defining which instruction is selected
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// Defining which instruction is selected
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reg EXTESTSelected;
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reg EXTESTSelected;
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reg SAMPLE_PRELOADSelected;
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reg SAMPLE_PRELOADSelected;
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reg IDCODESelected;
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reg IDCODESelected;
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reg CHAIN_SELECTSelected;
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reg CHAIN_SELECTSelected;
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reg INTESTSelected;
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reg INTESTSelected;
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reg CLAMPSelected;
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reg CLAMPSelected;
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reg CLAMPZSelected;
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reg CLAMPZSelected;
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reg HIGHZSelected;
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reg HIGHZSelected;
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reg DEBUGSelected;
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reg DEBUGSelected;
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reg BYPASSSelected;
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reg BYPASSSelected;
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|
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reg BypassRegister; // Bypass register
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reg BypassRegister; // Bypass register
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|
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wire trst;
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wire trst;
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wire tck;
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wire tck;
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wire TMS;
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wire TMS;
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wire tdi;
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wire tdi;
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|
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wire RiscDebugScanChain;
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wire RiscDebugScanChain;
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wire WishboneScanChain;
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wire WishboneScanChain;
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wire RegisterScanChain;
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wire RegisterScanChain;
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|
|
|
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assign trst = trst_pad_i; // trst_pad_i is active high !!! Inverted on higher layer
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assign trst = trst_pad_i; // trst_pad_i is active high !!! Inverted on higher layer
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assign tck = tck_pad_i;
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assign tck = tck_pad_i;
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assign TMS = tms_pad_i;
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assign TMS = tms_pad_i;
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assign tdi = tdi_pad_i;
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assign tdi = tdi_pad_i;
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|
|
|
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/**********************************************************************************
|
/**********************************************************************************
|
* *
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* *
|
* TAP State Machine: Fully JTAG compliant *
|
* TAP State Machine: Fully JTAG compliant *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
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|
|
// TestLogicReset state
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// TestLogicReset state
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always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
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begin
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if(trst)
|
if(trst)
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TestLogicReset<=#Tp 1;
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TestLogicReset<=#Tp 1;
|
else
|
else
|
begin
|
begin
|
if(TMS & (TestLogicReset | SelectIRScan))
|
if(TMS & (TestLogicReset | SelectIRScan))
|
TestLogicReset<=#Tp 1;
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TestLogicReset<=#Tp 1;
|
else
|
else
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TestLogicReset<=#Tp 0;
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TestLogicReset<=#Tp 0;
|
end
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end
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end
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end
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|
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// RunTestIdle state
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// RunTestIdle state
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always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
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begin
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if(trst)
|
if(trst)
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RunTestIdle<=#Tp 0;
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RunTestIdle<=#Tp 0;
|
else
|
else
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if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
|
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
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RunTestIdle<=#Tp 1;
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RunTestIdle<=#Tp 1;
|
else
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else
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RunTestIdle<=#Tp 0;
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RunTestIdle<=#Tp 0;
|
end
|
end
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|
|
// SelectDRScan state
|
// SelectDRScan state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
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SelectDRScan<=#Tp 0;
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SelectDRScan<=#Tp 0;
|
else
|
else
|
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
|
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
|
SelectDRScan<=#Tp 1;
|
SelectDRScan<=#Tp 1;
|
else
|
else
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SelectDRScan<=#Tp 0;
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SelectDRScan<=#Tp 0;
|
end
|
end
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|
|
// CaptureDR state
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// CaptureDR state
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always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
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begin
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begin
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if(trst)
|
if(trst)
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CaptureDR<=#Tp 0;
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CaptureDR<=#Tp 0;
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else
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else
|
if(~TMS & SelectDRScan)
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if(~TMS & SelectDRScan)
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CaptureDR<=#Tp 1;
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CaptureDR<=#Tp 1;
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else
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else
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CaptureDR<=#Tp 0;
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CaptureDR<=#Tp 0;
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end
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end
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// ShiftDR state
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// ShiftDR state
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always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
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begin
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begin
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if(trst)
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if(trst)
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ShiftDR<=#Tp 0;
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ShiftDR<=#Tp 0;
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else
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else
|
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
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if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
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ShiftDR<=#Tp 1;
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ShiftDR<=#Tp 1;
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else
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else
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ShiftDR<=#Tp 0;
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ShiftDR<=#Tp 0;
|
end
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end
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|
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// Exit1DR state
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// Exit1DR state
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always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
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begin
|
if(trst)
|
if(trst)
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Exit1DR<=#Tp 0;
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Exit1DR<=#Tp 0;
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else
|
else
|
if(TMS & (CaptureDR | ShiftDR))
|
if(TMS & (CaptureDR | ShiftDR))
|
Exit1DR<=#Tp 1;
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Exit1DR<=#Tp 1;
|
else
|
else
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Exit1DR<=#Tp 0;
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Exit1DR<=#Tp 0;
|
end
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end
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|
|
// PauseDR state
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// PauseDR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
PauseDR<=#Tp 0;
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PauseDR<=#Tp 0;
|
else
|
else
|
if(~TMS & (Exit1DR | PauseDR))
|
if(~TMS & (Exit1DR | PauseDR))
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PauseDR<=#Tp 1;
|
PauseDR<=#Tp 1;
|
else
|
else
|
PauseDR<=#Tp 0;
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PauseDR<=#Tp 0;
|
end
|
end
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|
|
// Exit2DR state
|
// Exit2DR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
Exit2DR<=#Tp 0;
|
Exit2DR<=#Tp 0;
|
else
|
else
|
if(TMS & PauseDR)
|
if(TMS & PauseDR)
|
Exit2DR<=#Tp 1;
|
Exit2DR<=#Tp 1;
|
else
|
else
|
Exit2DR<=#Tp 0;
|
Exit2DR<=#Tp 0;
|
end
|
end
|
|
|
// UpdateDR state
|
// UpdateDR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
UpdateDR<=#Tp 0;
|
UpdateDR<=#Tp 0;
|
else
|
else
|
if(TMS & (Exit1DR | Exit2DR))
|
if(TMS & (Exit1DR | Exit2DR))
|
UpdateDR<=#Tp 1;
|
UpdateDR<=#Tp 1;
|
else
|
else
|
UpdateDR<=#Tp 0;
|
UpdateDR<=#Tp 0;
|
end
|
end
|
|
|
// Delayed UpdateDR state
|
// Delayed UpdateDR state
|
reg UpdateDR_q;
|
reg UpdateDR_q;
|
always @ (posedge tck)
|
always @ (posedge tck)
|
begin
|
begin
|
UpdateDR_q<=#Tp UpdateDR;
|
UpdateDR_q<=#Tp UpdateDR;
|
end
|
end
|
|
|
// SelectIRScan state
|
// SelectIRScan state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
SelectIRScan<=#Tp 0;
|
SelectIRScan<=#Tp 0;
|
else
|
else
|
if(TMS & SelectDRScan)
|
if(TMS & SelectDRScan)
|
SelectIRScan<=#Tp 1;
|
SelectIRScan<=#Tp 1;
|
else
|
else
|
SelectIRScan<=#Tp 0;
|
SelectIRScan<=#Tp 0;
|
end
|
end
|
|
|
// CaptureIR state
|
// CaptureIR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
CaptureIR<=#Tp 0;
|
CaptureIR<=#Tp 0;
|
else
|
else
|
if(~TMS & SelectIRScan)
|
if(~TMS & SelectIRScan)
|
CaptureIR<=#Tp 1;
|
CaptureIR<=#Tp 1;
|
else
|
else
|
CaptureIR<=#Tp 0;
|
CaptureIR<=#Tp 0;
|
end
|
end
|
|
|
// ShiftIR state
|
// ShiftIR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
ShiftIR<=#Tp 0;
|
ShiftIR<=#Tp 0;
|
else
|
else
|
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
|
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
|
ShiftIR<=#Tp 1;
|
ShiftIR<=#Tp 1;
|
else
|
else
|
ShiftIR<=#Tp 0;
|
ShiftIR<=#Tp 0;
|
end
|
end
|
|
|
// Exit1IR state
|
// Exit1IR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
Exit1IR<=#Tp 0;
|
Exit1IR<=#Tp 0;
|
else
|
else
|
if(TMS & (CaptureIR | ShiftIR))
|
if(TMS & (CaptureIR | ShiftIR))
|
Exit1IR<=#Tp 1;
|
Exit1IR<=#Tp 1;
|
else
|
else
|
Exit1IR<=#Tp 0;
|
Exit1IR<=#Tp 0;
|
end
|
end
|
|
|
// PauseIR state
|
// PauseIR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
PauseIR<=#Tp 0;
|
PauseIR<=#Tp 0;
|
else
|
else
|
if(~TMS & (Exit1IR | PauseIR))
|
if(~TMS & (Exit1IR | PauseIR))
|
PauseIR<=#Tp 1;
|
PauseIR<=#Tp 1;
|
else
|
else
|
PauseIR<=#Tp 0;
|
PauseIR<=#Tp 0;
|
end
|
end
|
|
|
// Exit2IR state
|
// Exit2IR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
Exit2IR<=#Tp 0;
|
Exit2IR<=#Tp 0;
|
else
|
else
|
if(TMS & PauseIR)
|
if(TMS & PauseIR)
|
Exit2IR<=#Tp 1;
|
Exit2IR<=#Tp 1;
|
else
|
else
|
Exit2IR<=#Tp 0;
|
Exit2IR<=#Tp 0;
|
end
|
end
|
|
|
// UpdateIR state
|
// UpdateIR state
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
UpdateIR<=#Tp 0;
|
UpdateIR<=#Tp 0;
|
else
|
else
|
if(TMS & (Exit1IR | Exit2IR))
|
if(TMS & (Exit1IR | Exit2IR))
|
UpdateIR<=#Tp 1;
|
UpdateIR<=#Tp 1;
|
else
|
else
|
UpdateIR<=#Tp 0;
|
UpdateIR<=#Tp 0;
|
end
|
end
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: TAP State Machine *
|
* End: TAP State Machine *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* JTAG_IR: JTAG Instruction Register *
|
* JTAG_IR: JTAG Instruction Register *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
|
wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
|
|
|
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
|
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
|
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
|
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
|
|
|
reg TDOInstruction;
|
reg TDOInstruction;
|
|
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
|
else
|
else
|
if(CaptureIR)
|
if(CaptureIR)
|
begin
|
begin
|
JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
|
JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
|
JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
|
JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
|
end
|
end
|
else
|
else
|
if(ShiftIR)
|
if(ShiftIR)
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
|
end
|
end
|
|
|
|
|
//TDO is changing on the falling edge of tck
|
//TDO is changing on the falling edge of tck
|
always @ (negedge tck)
|
always @ (negedge tck)
|
begin
|
begin
|
if(ShiftIR)
|
if(ShiftIR)
|
TDOInstruction <= #Tp JTAG_IR[0];
|
TDOInstruction <= #Tp JTAG_IR[0];
|
end
|
end
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: JTAG_IR *
|
* End: JTAG_IR *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* JTAG_DR: JTAG Data Register *
|
* JTAG_DR: JTAG Data Register *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
|
|
|
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
else
|
else
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
else
|
else
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
end
|
end
|
else
|
else
|
if(CHAIN_SELECTSelected & ShiftDR)
|
if(CHAIN_SELECTSelected & ShiftDR)
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
else
|
else
|
if(DEBUGSelected & ShiftDR)
|
if(DEBUGSelected & ShiftDR)
|
begin
|
begin
|
if(RiscDebugScanChain | WishboneScanChain)
|
if(RiscDebugScanChain | WishboneScanChain)
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: JTAG_DR *
|
* End: JTAG_DR *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Bypass logic *
|
* Bypass logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg TDOBypassed;
|
reg TDOBypassed;
|
|
|
always @ (posedge tck)
|
always @ (posedge tck)
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
BypassRegister<=#Tp tdi;
|
BypassRegister<=#Tp tdi;
|
end
|
end
|
|
|
always @ (negedge tck)
|
always @ (negedge tck)
|
begin
|
begin
|
TDOBypassed<=#Tp BypassRegister;
|
TDOBypassed<=#Tp BypassRegister;
|
end
|
end
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Bypass logic *
|
* End: Bypass logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Activating Instructions *
|
* Activating Instructions *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
// Updating JTAG_IR (Instruction Register)
|
// Updating JTAG_IR (Instruction Register)
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
|
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
|
else
|
else
|
if(UpdateIR)
|
if(UpdateIR)
|
LatchedJTAG_IR <=#Tp JTAG_IR;
|
LatchedJTAG_IR <=#Tp JTAG_IR;
|
end
|
end
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Activating Instructions *
|
* End: Activating Instructions *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
// Updating JTAG_IR (Instruction Register)
|
// Updating JTAG_IR (Instruction Register)
|
always @ (LatchedJTAG_IR)
|
always @ (LatchedJTAG_IR)
|
begin
|
begin
|
EXTESTSelected = 0;
|
EXTESTSelected = 0;
|
SAMPLE_PRELOADSelected = 0;
|
SAMPLE_PRELOADSelected = 0;
|
IDCODESelected = 0;
|
IDCODESelected = 0;
|
CHAIN_SELECTSelected = 0;
|
CHAIN_SELECTSelected = 0;
|
INTESTSelected = 0;
|
INTESTSelected = 0;
|
CLAMPSelected = 0;
|
CLAMPSelected = 0;
|
CLAMPZSelected = 0;
|
CLAMPZSelected = 0;
|
HIGHZSelected = 0;
|
HIGHZSelected = 0;
|
DEBUGSelected = 0;
|
DEBUGSelected = 0;
|
BYPASSSelected = 0;
|
BYPASSSelected = 0;
|
|
|
case(LatchedJTAG_IR)
|
case(LatchedJTAG_IR)
|
`EXTEST: EXTESTSelected = 1; // External test
|
`EXTEST: EXTESTSelected = 1; // External test
|
`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
|
`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
|
`IDCODE: IDCODESelected = 1; // ID Code
|
`IDCODE: IDCODESelected = 1; // ID Code
|
`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
|
`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
|
`INTEST: INTESTSelected = 1; // Internal test
|
`INTEST: INTESTSelected = 1; // Internal test
|
`CLAMP: CLAMPSelected = 1; // Clamp
|
`CLAMP: CLAMPSelected = 1; // Clamp
|
`CLAMPZ: CLAMPZSelected = 1; // ClampZ
|
`CLAMPZ: CLAMPZSelected = 1; // ClampZ
|
`HIGHZ: HIGHZSelected = 1; // High Z
|
`HIGHZ: HIGHZSelected = 1; // High Z
|
`DEBUG: DEBUGSelected = 1; // Debug
|
`DEBUG: DEBUGSelected = 1; // Debug
|
`BYPASS: BYPASSSelected = 1; // BYPASS
|
`BYPASS: BYPASSSelected = 1; // BYPASS
|
default: BYPASSSelected = 1; // BYPASS
|
default: BYPASSSelected = 1; // BYPASS
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Multiplexing TDO data *
|
* Multiplexing TDO data *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
// This multiplexer can be expanded with number of user registers
|
// This multiplexer can be expanded with number of user registers
|
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
|
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
|
begin
|
begin
|
if(ShiftIR | Exit1IR)
|
if(ShiftIR | Exit1IR)
|
tdo_pad_o <=#Tp TDOInstruction;
|
tdo_pad_o <=#Tp TDOInstruction;
|
else
|
else
|
begin
|
begin
|
case(LatchedJTAG_IR)
|
case(LatchedJTAG_IR)
|
`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
|
`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
|
`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
|
`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
|
`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
|
`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
|
`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
|
`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
|
`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
|
`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
|
default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
|
default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
// Tristate control for tdo_pad_o pin
|
// Tristate control for tdo_pad_o pin
|
assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
|
assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Multiplexing TDO data *
|
* End: Multiplexing TDO data *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
endmodule
|
endmodule
|
|
|