//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_register.v ////
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//// dbg_register.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/04/22 12:54:11 mohor
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// Revision 1.4 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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// Signal names changed to lower case.
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//
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//
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// Revision 1.3 2001/11/26 10:47:09 mohor
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// Revision 1.3 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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//
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module dbg_register(data_in, data_out, write, clk, reset, defaulty);
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module dbg_register(data_in, data_out, write, clk, reset, defaulty);
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parameter WIDTH = 8; // default parameter of the register width
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parameter WIDTH = 8; // default parameter of the register width
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input [WIDTH-1:0] data_in;
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input [WIDTH-1:0] data_in;
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input write;
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input write;
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input clk;
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input clk;
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input reset;
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input reset;
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input [WIDTH-1:0] defaulty;
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input [WIDTH-1:0] defaulty;
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output [WIDTH-1:0] data_out;
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output [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] data_out;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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//always @ (posedge clk)
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//always @ (posedge clk)
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begin
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begin
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if(reset)
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if(reset)
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data_out[WIDTH-1:0]<=#1 defaulty;
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data_out[WIDTH-1:0]<=#1 defaulty;
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else
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else
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begin
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begin
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if(write) // write
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if(write) // write
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data_out[WIDTH-1:0]<=#1 data_in[WIDTH-1:0];
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data_out[WIDTH-1:0]<=#1 data_in[WIDTH-1:0];
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end
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end
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end
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end
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endmodule // Register
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endmodule // Register
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