//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_registers.v ////
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//// dbg_registers.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/04/22 12:54:11 mohor
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// Revision 1.6 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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// Signal names changed to lower case.
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//
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//
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// Revision 1.5 2001/11/26 10:47:09 mohor
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// Revision 1.5 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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//
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// Revision 1.4 2001/10/19 11:40:02 mohor
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// Revision 1.4 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.3 2001/10/15 09:55:47 mohor
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// Revision 1.3 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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// hooks for boundary scan testing added.
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//
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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//
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// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
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// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
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// Initial release
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// Initial release
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
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module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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ContinMode,
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ContinMode,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
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RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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LSSStopValid, IStopValid,
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LSSStopValid, IStopValid,
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`endif
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`endif
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risc_stall, risc_reset, mon_cntl_o
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risc_stall, risc_reset, mon_cntl_o
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] data_in;
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input [31:0] data_in;
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input [4:0] address;
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input [4:0] address;
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input rw;
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input rw;
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input access;
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input access;
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input clk;
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input clk;
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input bp;
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input bp;
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input reset;
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input reset;
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output [31:0] data_out;
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output [31:0] data_out;
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reg [31:0] data_out;
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reg [31:0] data_out;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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output ContinMode;
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output ContinMode;
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output TraceEnable;
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output TraceEnable;
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output [10:0] WpTrigger;
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output [10:0] WpTrigger;
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output BpTrigger;
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output BpTrigger;
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output [3:0] LSSTrigger;
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output [3:0] LSSTrigger;
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output [1:0] ITrigger;
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output [1:0] ITrigger;
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output [1:0] TriggerOper;
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output [1:0] TriggerOper;
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output WpTriggerValid;
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output WpTriggerValid;
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output BpTriggerValid;
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output BpTriggerValid;
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output LSSTriggerValid;
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output LSSTriggerValid;
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output ITriggerValid;
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output ITriggerValid;
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output [10:0] WpQualif;
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output [10:0] WpQualif;
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output BpQualif;
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output BpQualif;
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output [3:0] LSSQualif;
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output [3:0] LSSQualif;
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output [1:0] IQualif;
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output [1:0] IQualif;
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output [1:0] QualifOper;
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output [1:0] QualifOper;
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output WpQualifValid;
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output WpQualifValid;
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output BpQualifValid;
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output BpQualifValid;
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output LSSQualifValid;
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output LSSQualifValid;
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output IQualifValid;
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output IQualifValid;
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output [10:0] WpStop;
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output [10:0] WpStop;
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output BpStop;
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output BpStop;
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output [3:0] LSSStop;
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output [3:0] LSSStop;
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output [1:0] IStop;
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output [1:0] IStop;
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output [1:0] StopOper;
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output [1:0] StopOper;
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output WpStopValid;
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output WpStopValid;
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output BpStopValid;
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output BpStopValid;
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output LSSStopValid;
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output LSSStopValid;
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output IStopValid;
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output IStopValid;
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output RecordPC;
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output RecordPC;
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output RecordLSEA;
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output RecordLSEA;
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output RecordLDATA;
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output RecordLDATA;
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output RecordSDATA;
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output RecordSDATA;
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output RecordReadSPR;
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output RecordReadSPR;
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output RecordWriteSPR;
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output RecordWriteSPR;
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output RecordINSTR;
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output RecordINSTR;
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`endif
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`endif
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output risc_stall;
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output risc_stall;
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output risc_reset;
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output risc_reset;
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output [3:0] mon_cntl_o;
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output [3:0] mon_cntl_o;
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|
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wire MODER_Acc = (address == `MODER_ADR) & access;
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wire MODER_Acc = (address == `MODER_ADR) & access;
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wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
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wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
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wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
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wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Acc = (address == `TSEL_ADR) & access;
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wire TSEL_Acc = (address == `TSEL_ADR) & access;
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wire QSEL_Acc = (address == `QSEL_ADR) & access;
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wire QSEL_Acc = (address == `QSEL_ADR) & access;
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wire SSEL_Acc = (address == `SSEL_ADR) & access;
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wire SSEL_Acc = (address == `SSEL_ADR) & access;
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wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
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wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
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`endif
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`endif
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wire MODER_Wr = MODER_Acc & rw;
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wire MODER_Wr = MODER_Acc & rw;
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wire RISCOP_Wr = RISCOP_Acc & rw;
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wire RISCOP_Wr = RISCOP_Acc & rw;
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wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
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wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Wr = TSEL_Acc & rw;
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wire TSEL_Wr = TSEL_Acc & rw;
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wire QSEL_Wr = QSEL_Acc & rw;
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wire QSEL_Wr = QSEL_Acc & rw;
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wire SSEL_Wr = SSEL_Acc & rw;
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wire SSEL_Wr = SSEL_Acc & rw;
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wire RECSEL_Wr = RECSEL_Acc & rw;
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wire RECSEL_Wr = RECSEL_Acc & rw;
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`endif
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`endif
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wire MODER_Rd = MODER_Acc & ~rw;
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wire MODER_Rd = MODER_Acc & ~rw;
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wire RISCOP_Rd = RISCOP_Acc & ~rw;
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wire RISCOP_Rd = RISCOP_Acc & ~rw;
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wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
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wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Rd = TSEL_Acc & ~rw;
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wire TSEL_Rd = TSEL_Acc & ~rw;
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wire QSEL_Rd = QSEL_Acc & ~rw;
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wire QSEL_Rd = QSEL_Acc & ~rw;
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wire SSEL_Rd = SSEL_Acc & ~rw;
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wire SSEL_Rd = SSEL_Acc & ~rw;
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wire RECSEL_Rd = RECSEL_Acc & ~rw;
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wire RECSEL_Rd = RECSEL_Acc & ~rw;
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`endif
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`endif
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [1:1] RISCOPOut;
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wire [1:1] RISCOPOut;
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wire [3:0] MONCNTLOut;
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wire [3:0] MONCNTLOut;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire [31:0] TSELOut;
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wire [31:0] TSELOut;
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wire [31:0] QSELOut;
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wire [31:0] QSELOut;
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wire [31:0] SSELOut;
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wire [31:0] SSELOut;
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wire [6:0] RECSELOut;
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wire [6:0] RECSELOut;
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`endif
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`endif
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign MODEROut[15:0] = 16'h0001;
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assign MODEROut[15:0] = 16'h0001;
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assign MODEROut[31:18] = 14'h0;
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assign MODEROut[31:18] = 14'h0;
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`else
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`else
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assign MODEROut[31:0] = 32'h0000;
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assign MODEROut[31:0] = 32'h0000;
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`endif
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`endif
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reg RiscStallBp;
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reg RiscStallBp;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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begin
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begin
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if(reset)
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if(reset)
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RiscStallBp <= 1'b0;
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RiscStallBp <= 1'b0;
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else
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else
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if(bp) // Breakpoint sets bit
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if(bp) // Breakpoint sets bit
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RiscStallBp <= 1'b1;
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RiscStallBp <= 1'b1;
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else
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else
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if(RISCOP_Wr) // Register access can set or clear bit
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if(RISCOP_Wr) // Register access can set or clear bit
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RiscStallBp <= data_in[0];
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RiscStallBp <= data_in[0];
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end
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end
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dbg_register #(1) RISCOP (.data_in(data_in[1]), .data_out(RISCOPOut[1]), .write(RISCOP_Wr), .clk(clk), .reset(reset), .defaulty(1'b0));
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dbg_register #(1) RISCOP (.data_in(data_in[1]), .data_out(RISCOPOut[1]), .write(RISCOP_Wr), .clk(clk), .reset(reset), .defaulty(1'b0));
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dbg_register #(4) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset), .defaulty(`MON_CNTL_DEF));
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dbg_register #(4) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset), .defaulty(`MON_CNTL_DEF));
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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dbg_register #(2) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset), .defaulty(`MODER_DEF));
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dbg_register #(2) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset), .defaulty(`MODER_DEF));
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dbg_register #(32) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset), .defaulty(`TSEL_DEF));
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dbg_register #(32) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset), .defaulty(`TSEL_DEF));
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dbg_register #(32) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset), .defaulty(`QSEL_DEF));
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dbg_register #(32) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset), .defaulty(`QSEL_DEF));
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dbg_register #(32) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset), .defaulty(`SSEL_DEF));
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dbg_register #(32) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset), .defaulty(`SSEL_DEF));
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dbg_register #(7) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset), .defaulty(`RECSEL_DEF));
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dbg_register #(7) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset), .defaulty(`RECSEL_DEF));
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`endif
|
`endif
|
|
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if(MODER_Rd) data_out<= #Tp MODEROut;
|
if(MODER_Rd) data_out<= #Tp MODEROut;
|
else
|
else
|
if(RISCOP_Rd) data_out<= #Tp {30'h0, RISCOPOut[1], risc_stall};
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if(RISCOP_Rd) data_out<= #Tp {30'h0, RISCOPOut[1], risc_stall};
|
else
|
else
|
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
|
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
else
|
else
|
if(TSEL_Rd) data_out<= #Tp TSELOut;
|
if(TSEL_Rd) data_out<= #Tp TSELOut;
|
else
|
else
|
if(QSEL_Rd) data_out<= #Tp QSELOut;
|
if(QSEL_Rd) data_out<= #Tp QSELOut;
|
else
|
else
|
if(SSEL_Rd) data_out<= #Tp SSELOut;
|
if(SSEL_Rd) data_out<= #Tp SSELOut;
|
else
|
else
|
if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
|
if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
|
`endif
|
`endif
|
else data_out<= #Tp 'h0;
|
else data_out<= #Tp 'h0;
|
end
|
end
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign TraceEnable = MODEROut[16];
|
assign TraceEnable = MODEROut[16];
|
assign ContinMode = MODEROut[17];
|
assign ContinMode = MODEROut[17];
|
|
|
assign WpTrigger[10:0] = TSELOut[10:0];
|
assign WpTrigger[10:0] = TSELOut[10:0];
|
assign WpTriggerValid = TSELOut[11];
|
assign WpTriggerValid = TSELOut[11];
|
assign BpTrigger = TSELOut[12];
|
assign BpTrigger = TSELOut[12];
|
assign BpTriggerValid = TSELOut[13];
|
assign BpTriggerValid = TSELOut[13];
|
assign LSSTrigger[3:0] = TSELOut[19:16];
|
assign LSSTrigger[3:0] = TSELOut[19:16];
|
assign LSSTriggerValid = TSELOut[20];
|
assign LSSTriggerValid = TSELOut[20];
|
assign ITrigger[1:0] = TSELOut[22:21];
|
assign ITrigger[1:0] = TSELOut[22:21];
|
assign ITriggerValid = TSELOut[23];
|
assign ITriggerValid = TSELOut[23];
|
assign TriggerOper[1:0] = TSELOut[31:30];
|
assign TriggerOper[1:0] = TSELOut[31:30];
|
|
|
assign WpQualif[10:0] = QSELOut[10:0];
|
assign WpQualif[10:0] = QSELOut[10:0];
|
assign WpQualifValid = QSELOut[11];
|
assign WpQualifValid = QSELOut[11];
|
assign BpQualif = QSELOut[12];
|
assign BpQualif = QSELOut[12];
|
assign BpQualifValid = QSELOut[13];
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assign BpQualifValid = QSELOut[13];
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assign LSSQualif[3:0] = QSELOut[19:16];
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assign LSSQualif[3:0] = QSELOut[19:16];
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assign LSSQualifValid = QSELOut[20];
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assign LSSQualifValid = QSELOut[20];
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assign IQualif[1:0] = QSELOut[22:21];
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assign IQualif[1:0] = QSELOut[22:21];
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assign IQualifValid = QSELOut[23];
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assign IQualifValid = QSELOut[23];
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assign QualifOper[1:0] = QSELOut[31:30];
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assign QualifOper[1:0] = QSELOut[31:30];
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assign WpStop[10:0] = SSELOut[10:0];
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assign WpStop[10:0] = SSELOut[10:0];
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assign WpStopValid = SSELOut[11];
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assign WpStopValid = SSELOut[11];
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assign BpStop = SSELOut[12];
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assign BpStop = SSELOut[12];
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assign BpStopValid = SSELOut[13];
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assign BpStopValid = SSELOut[13];
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assign LSSStop[3:0] = SSELOut[19:16];
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assign LSSStop[3:0] = SSELOut[19:16];
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assign LSSStopValid = SSELOut[20];
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assign LSSStopValid = SSELOut[20];
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assign IStop[1:0] = SSELOut[22:21];
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assign IStop[1:0] = SSELOut[22:21];
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assign IStopValid = SSELOut[23];
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assign IStopValid = SSELOut[23];
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assign StopOper[1:0] = SSELOut[31:30];
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assign StopOper[1:0] = SSELOut[31:30];
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assign RecordPC = RECSELOut[0];
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assign RecordPC = RECSELOut[0];
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assign RecordLSEA = RECSELOut[1];
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assign RecordLSEA = RECSELOut[1];
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assign RecordLDATA = RECSELOut[2];
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assign RecordLDATA = RECSELOut[2];
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assign RecordSDATA = RECSELOut[3];
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assign RecordSDATA = RECSELOut[3];
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assign RecordReadSPR = RECSELOut[4];
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assign RecordReadSPR = RECSELOut[4];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordINSTR = RECSELOut[6];
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assign RecordINSTR = RECSELOut[6];
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`endif
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`endif
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assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
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assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
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assign risc_reset = RISCOPOut[1];
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assign risc_reset = RISCOPOut[1];
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assign mon_cntl_o = MONCNTLOut;
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assign mon_cntl_o = MONCNTLOut;
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endmodule
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endmodule
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