//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// dbg_sync_clk1_clk2.v ////
|
//// dbg_sync_clk1_clk2.v ////
|
//// ////
|
//// ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// http://www.opencores.org/cores/DebugInterface/ ////
|
//// http://www.opencores.org/cores/DebugInterface/ ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// ////
|
//// ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// file. ////
|
//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Authors ////
|
//// Copyright (C) 2001 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.2 2001/10/19 11:40:01 mohor
|
// Revision 1.2 2001/10/19 11:40:01 mohor
|
// dbg_timescale.v changed to timescale.v This is done for the simulation of
|
// dbg_timescale.v changed to timescale.v This is done for the simulation of
|
// few different cores in a single project.
|
// few different cores in a single project.
|
//
|
//
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
|
// Initial official release.
|
// Initial official release.
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// FF in clock domain 1 is being set by a signal from the clock domain 2
|
// FF in clock domain 1 is being set by a signal from the clock domain 2
|
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
|
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
input clk1;
|
input clk1;
|
input clk2;
|
input clk2;
|
input reset1;
|
input reset1;
|
input reset2;
|
input reset2;
|
input set2;
|
input set2;
|
|
|
output sync_out;
|
output sync_out;
|
|
|
reg set2_q;
|
reg set2_q;
|
reg set2_q2;
|
reg set2_q2;
|
reg set1_q;
|
reg set1_q;
|
reg set1_q2;
|
reg set1_q2;
|
reg clear2_q;
|
reg clear2_q;
|
reg clear2_q2;
|
reg clear2_q2;
|
reg sync_out;
|
reg sync_out;
|
|
|
wire z;
|
wire z;
|
|
|
assign z = set2 | set2_q & ~clear2_q2;
|
assign z = set2 | set2_q & ~clear2_q2;
|
|
|
|
|
// Latching and synchronizing "set" to clk2
|
// Latching and synchronizing "set" to clk2
|
always @ (posedge clk2 or posedge reset2)
|
always @ (posedge clk2 or posedge reset2)
|
begin
|
begin
|
if(reset2)
|
if(reset2)
|
set2_q <=#Tp 1'b0;
|
set2_q <=#Tp 1'b0;
|
else
|
else
|
set2_q <=#Tp z;
|
set2_q <=#Tp z;
|
end
|
end
|
|
|
|
|
always @ (posedge clk2 or posedge reset2)
|
always @ (posedge clk2 or posedge reset2)
|
begin
|
begin
|
if(reset2)
|
if(reset2)
|
set2_q2 <=#Tp 1'b0;
|
set2_q2 <=#Tp 1'b0;
|
else
|
else
|
set2_q2 <=#Tp set2_q;
|
set2_q2 <=#Tp set2_q;
|
end
|
end
|
|
|
|
|
// Synchronizing "set" to clk1
|
// Synchronizing "set" to clk1
|
always @ (posedge clk1 or posedge reset1)
|
always @ (posedge clk1 or posedge reset1)
|
begin
|
begin
|
if(reset1)
|
if(reset1)
|
set1_q <=#Tp 1'b0;
|
set1_q <=#Tp 1'b0;
|
else
|
else
|
set1_q <=#Tp set2_q2;
|
set1_q <=#Tp set2_q2;
|
end
|
end
|
|
|
|
|
always @ (posedge clk1 or posedge reset1)
|
always @ (posedge clk1 or posedge reset1)
|
begin
|
begin
|
if(reset1)
|
if(reset1)
|
set1_q2 <=#Tp 1'b0;
|
set1_q2 <=#Tp 1'b0;
|
else
|
else
|
set1_q2 <=#Tp set1_q;
|
set1_q2 <=#Tp set1_q;
|
end
|
end
|
|
|
|
|
// Synchronizing "clear" to clk2
|
// Synchronizing "clear" to clk2
|
always @ (posedge clk2 or posedge reset2)
|
always @ (posedge clk2 or posedge reset2)
|
begin
|
begin
|
if(reset2)
|
if(reset2)
|
clear2_q <=#Tp 1'b0;
|
clear2_q <=#Tp 1'b0;
|
else
|
else
|
clear2_q <=#Tp set1_q2;
|
clear2_q <=#Tp set1_q2;
|
end
|
end
|
|
|
|
|
always @ (posedge clk2 or posedge reset2)
|
always @ (posedge clk2 or posedge reset2)
|
begin
|
begin
|
if(reset2)
|
if(reset2)
|
clear2_q2 <=#Tp 1'b0;
|
clear2_q2 <=#Tp 1'b0;
|
else
|
else
|
clear2_q2 <=#Tp clear2_q;
|
clear2_q2 <=#Tp clear2_q;
|
end
|
end
|
|
|
|
|
always @ (posedge clk1 or posedge reset1)
|
always @ (posedge clk1 or posedge reset1)
|
begin
|
begin
|
if(reset1)
|
if(reset1)
|
sync_out <=#Tp 1'b0;
|
sync_out <=#Tp 1'b0;
|
else
|
else
|
sync_out <=#Tp set1_q2;
|
sync_out <=#Tp set1_q2;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|