//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_top.v ////
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//// dbg_top.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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// Signal names changed to lower case.
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//
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//
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Intentional error removed.
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// Intentional error removed.
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//
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//
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// Revision 1.23 2002/04/17 11:16:33 mohor
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// Revision 1.23 2002/04/17 11:16:33 mohor
|
// A block for checking possible simulation/synthesis missmatch added.
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// A block for checking possible simulation/synthesis missmatch added.
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//
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//
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
|
// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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// logic necessery for debugging.
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//
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//
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// Revision 1.21 2002/03/08 15:28:16 mohor
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// Revision 1.21 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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// Structure changed. Hooks for jtag chain added.
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//
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//
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
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// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
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//
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//
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Stupid bug that was entered by previous update fixed.
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// Stupid bug that was entered by previous update fixed.
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//
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//
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// Revision 1.18 2002/02/05 12:41:01 mohor
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// Revision 1.18 2002/02/05 12:41:01 mohor
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// trst synchronization is not needed and was removed.
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// trst synchronization is not needed and was removed.
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//
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//
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// Revision 1.17 2002/01/25 07:58:35 mohor
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// Revision 1.17 2002/01/25 07:58:35 mohor
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
|
// not filled-in. Tested in hw.
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// not filled-in. Tested in hw.
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//
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//
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// Revision 1.16 2001/12/20 11:17:26 mohor
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// Revision 1.16 2001/12/20 11:17:26 mohor
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// TDO and TDO Enable signal are separated into two signals.
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// TDO and TDO Enable signal are separated into two signals.
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//
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//
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// trst signal is synchronized to wb_clk_i.
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// trst signal is synchronized to wb_clk_i.
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//
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//
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Register length fixed.
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// Register length fixed.
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//
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//
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// CRC is returned when chain selection data is transmitted.
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// CRC is returned when chain selection data is transmitted.
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//
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//
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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//
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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//
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//
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Reset signals are not combined any more.
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// Reset signals are not combined any more.
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//
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//
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.8 2001/10/17 10:39:03 mohor
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// Revision 1.8 2001/10/17 10:39:03 mohor
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// bs_chain_o added.
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// bs_chain_o added.
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//
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//
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// Revision 1.7 2001/10/16 10:09:56 mohor
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// Revision 1.7 2001/10/16 10:09:56 mohor
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// Signal names changed to lowercase.
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// Signal names changed to lowercase.
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//
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//
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//
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//
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// Revision 1.6 2001/10/15 09:55:47 mohor
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// Revision 1.6 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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// hooks for boundary scan testing added.
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//
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//
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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//
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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// Working version. Few bugs fixed, comments added.
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//
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//
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Asynchronous set/reset not used in trace any more.
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// Asynchronous set/reset not used in trace any more.
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//
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
|
// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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//
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// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Initial release
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// Initial release
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//
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//
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//
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//
|
|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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|
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// Top module
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// Top module
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module dbg_top(
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module dbg_top(
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|
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// RISC signals
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// RISC signals
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risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
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risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
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bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
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bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
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|
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// WISHBONE common signals
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// WISHBONE common signals
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wb_rst_i, wb_clk_i,
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wb_rst_i, wb_clk_i,
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|
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// WISHBONE master interface
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// WISHBONE master interface
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wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
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wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
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wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
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wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
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// TAP states
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// TAP states
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
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// Instructions
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// Instructions
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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|
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// TAP signals
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// TAP signals
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trst_in, tck, tdi, TDOData,
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trst_in, tck, tdi, TDOData,
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|
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BypassRegister,
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BypassRegister,
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// Monitor mux control
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// Monitor mux control
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mon_cntl_o
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mon_cntl_o
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|
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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// RISC signals
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// RISC signals
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input risc_clk_i; // Master clock (RISC clock)
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input risc_clk_i; // Master clock (RISC clock)
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input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
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input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
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input [10:0] wp_i; // Watchpoint inputs
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input [10:0] wp_i; // Watchpoint inputs
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input bp_i; // Breakpoint input
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input bp_i; // Breakpoint input
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input [3:0] lsstatus_i; // Load/store status inputs
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input [3:0] lsstatus_i; // Load/store status inputs
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input [1:0] istatus_i; // Instruction status inputs
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input [1:0] istatus_i; // Instruction status inputs
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output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
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output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
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output [31:0] risc_data_o; // RISC data output (data read from risc registers)
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output [31:0] risc_data_o; // RISC data output (data read from risc registers)
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output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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output risc_stall_o; // Stalls the RISC
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output risc_stall_o; // Stalls the RISC
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output reset_o; // Resets the RISC
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output reset_o; // Resets the RISC
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|
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// WISHBONE common signals
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// WISHBONE common signals
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input wb_rst_i; // WISHBONE reset
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input wb_rst_i; // WISHBONE reset
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input wb_clk_i; // WISHBONE clock
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input wb_clk_i; // WISHBONE clock
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|
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// WISHBONE master interface
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// WISHBONE master interface
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output [31:0] wb_adr_o;
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_cyc_o;
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output wb_stb_o;
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output wb_stb_o;
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output [3:0] wb_sel_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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output wb_we_o;
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input wb_ack_i;
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input wb_ack_i;
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output wb_cab_o;
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output wb_cab_o;
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input wb_err_i;
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input wb_err_i;
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// TAP states
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// TAP states
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input ShiftDR;
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input ShiftDR;
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input Exit1DR;
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input Exit1DR;
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input UpdateDR;
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input UpdateDR;
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input UpdateDR_q;
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input UpdateDR_q;
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input trst_in;
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input trst_in;
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input tck;
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input tck;
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input tdi;
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input tdi;
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|
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input BypassRegister;
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input BypassRegister;
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output TDOData;
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output TDOData;
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output [3:0] mon_cntl_o;
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output [3:0] mon_cntl_o;
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// Defining which instruction is selected
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// Defining which instruction is selected
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input IDCODESelected;
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input IDCODESelected;
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input CHAIN_SELECTSelected;
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input CHAIN_SELECTSelected;
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input DEBUGSelected;
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input DEBUGSelected;
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reg wb_cyc_o;
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reg wb_cyc_o;
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reg [31:0] ADDR;
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reg [31:0] ADDR;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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|
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reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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|
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reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
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reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
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reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
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reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
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reg RegAccessTck; // Indicates access to the registers (read or write)
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reg RegAccessTck; // Indicates access to the registers (read or write)
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reg RISCAccessTck; // Indicates access to the RISC (read or write)
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reg RISCAccessTck; // Indicates access to the RISC (read or write)
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reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
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reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
|
reg RW; // Read/Write bit
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reg RW; // Read/Write bit
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reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
|
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reg RegAccess_q; // Delayed signals used for accessing the registers
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reg RegAccess_q; // Delayed signals used for accessing the registers
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reg RegAccess_q2; // Delayed signals used for accessing the registers
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reg RegAccess_q2; // Delayed signals used for accessing the registers
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reg RISCAccess_q; // Delayed signals used for accessing the RISC
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reg RISCAccess_q; // Delayed signals used for accessing the RISC
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reg RISCAccess_q2; // Delayed signals used for accessing the RISC
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reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
|
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reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
|
|
|
wire trst;
|
wire trst;
|
|
|
|
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wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
|
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
wire RiscReset_reg; // RISC is reset by setting the register bit
|
wire RiscReset_reg; // RISC is reset by setting the register bit
|
wire RiscStall_trace; // RISC is stalled by trace module
|
wire RiscStall_trace; // RISC is stalled by trace module
|
|
|
|
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wire RegisterScanChain; // Register Scan chain selected
|
wire RegisterScanChain; // Register Scan chain selected
|
wire RiscDebugScanChain; // Risc Debug Scan chain selected
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wire RiscDebugScanChain; // Risc Debug Scan chain selected
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wire WishboneScanChain; // WISHBONE Scan chain selected
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wire WishboneScanChain; // WISHBONE Scan chain selected
|
|
|
wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
|
wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
|
wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
|
wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
|
wire RiscStall_access; // Stalling RISC because of the read or write access
|
wire RiscStall_access; // Stalling RISC because of the read or write access
|
|
|
wire BitCounter_Lt4;
|
wire BitCounter_Lt4;
|
wire BitCounter_Eq5;
|
wire BitCounter_Eq5;
|
wire BitCounter_Eq32;
|
wire BitCounter_Eq32;
|
wire BitCounter_Lt38;
|
wire BitCounter_Lt38;
|
wire BitCounter_Lt65;
|
wire BitCounter_Lt65;
|
|
|
|
|
|
|
// This signals are used only when TRACE is used in the design
|
// This signals are used only when TRACE is used in the design
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
wire [39:0] TraceChain; // Chain that comes from trace module
|
wire [39:0] TraceChain; // Chain that comes from trace module
|
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
|
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
|
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
|
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
|
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
|
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
|
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
|
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
|
|
|
// Outputs from registers
|
// Outputs from registers
|
wire ContinMode; // Trace working in continous mode
|
wire ContinMode; // Trace working in continous mode
|
wire TraceEnable; // Trace enabled
|
wire TraceEnable; // Trace enabled
|
|
|
wire [10:0] WpTrigger; // Watchpoint starts trigger
|
wire [10:0] WpTrigger; // Watchpoint starts trigger
|
wire BpTrigger; // Breakpoint starts trigger
|
wire BpTrigger; // Breakpoint starts trigger
|
wire [3:0] LSSTrigger; // Load/store status starts trigger
|
wire [3:0] LSSTrigger; // Load/store status starts trigger
|
wire [1:0] ITrigger; // Instruction status starts trigger
|
wire [1:0] ITrigger; // Instruction status starts trigger
|
wire [1:0] TriggerOper; // Trigger operation
|
wire [1:0] TriggerOper; // Trigger operation
|
|
|
wire WpTriggerValid; // Watchpoint trigger is valid
|
wire WpTriggerValid; // Watchpoint trigger is valid
|
wire BpTriggerValid; // Breakpoint trigger is valid
|
wire BpTriggerValid; // Breakpoint trigger is valid
|
wire LSSTriggerValid; // Load/store status trigger is valid
|
wire LSSTriggerValid; // Load/store status trigger is valid
|
wire ITriggerValid; // Instruction status trigger is valid
|
wire ITriggerValid; // Instruction status trigger is valid
|
|
|
wire [10:0] WpQualif; // Watchpoint starts qualifier
|
wire [10:0] WpQualif; // Watchpoint starts qualifier
|
wire BpQualif; // Breakpoint starts qualifier
|
wire BpQualif; // Breakpoint starts qualifier
|
wire [3:0] LSSQualif; // Load/store status starts qualifier
|
wire [3:0] LSSQualif; // Load/store status starts qualifier
|
wire [1:0] IQualif; // Instruction status starts qualifier
|
wire [1:0] IQualif; // Instruction status starts qualifier
|
wire [1:0] QualifOper; // Qualifier operation
|
wire [1:0] QualifOper; // Qualifier operation
|
|
|
wire WpQualifValid; // Watchpoint qualifier is valid
|
wire WpQualifValid; // Watchpoint qualifier is valid
|
wire BpQualifValid; // Breakpoint qualifier is valid
|
wire BpQualifValid; // Breakpoint qualifier is valid
|
wire LSSQualifValid; // Load/store status qualifier is valid
|
wire LSSQualifValid; // Load/store status qualifier is valid
|
wire IQualifValid; // Instruction status qualifier is valid
|
wire IQualifValid; // Instruction status qualifier is valid
|
|
|
wire [10:0] WpStop; // Watchpoint stops recording of the trace
|
wire [10:0] WpStop; // Watchpoint stops recording of the trace
|
wire BpStop; // Breakpoint stops recording of the trace
|
wire BpStop; // Breakpoint stops recording of the trace
|
wire [3:0] LSSStop; // Load/store status stops recording of the trace
|
wire [3:0] LSSStop; // Load/store status stops recording of the trace
|
wire [1:0] IStop; // Instruction status stops recording of the trace
|
wire [1:0] IStop; // Instruction status stops recording of the trace
|
wire [1:0] StopOper; // Stop operation
|
wire [1:0] StopOper; // Stop operation
|
|
|
wire WpStopValid; // Watchpoint stop is valid
|
wire WpStopValid; // Watchpoint stop is valid
|
wire BpStopValid; // Breakpoint stop is valid
|
wire BpStopValid; // Breakpoint stop is valid
|
wire LSSStopValid; // Load/store status stop is valid
|
wire LSSStopValid; // Load/store status stop is valid
|
wire IStopValid; // Instruction status stop is valid
|
wire IStopValid; // Instruction status stop is valid
|
|
|
wire RecordPC; // Recording program counter
|
wire RecordPC; // Recording program counter
|
wire RecordLSEA; // Recording load/store effective address
|
wire RecordLSEA; // Recording load/store effective address
|
wire RecordLDATA; // Recording load data
|
wire RecordLDATA; // Recording load data
|
wire RecordSDATA; // Recording store data
|
wire RecordSDATA; // Recording store data
|
wire RecordReadSPR; // Recording read SPR
|
wire RecordReadSPR; // Recording read SPR
|
wire RecordWriteSPR; // Recording write SPR
|
wire RecordWriteSPR; // Recording write SPR
|
wire RecordINSTR; // Recording instruction
|
wire RecordINSTR; // Recording instruction
|
|
|
// End: Outputs from registers
|
// End: Outputs from registers
|
|
|
wire TraceTestScanChain; // Trace Test Scan chain selected
|
wire TraceTestScanChain; // Trace Test Scan chain selected
|
wire [47:0] Trace_Data; // Trace data
|
wire [47:0] Trace_Data; // Trace data
|
|
|
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
|
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
|
// data is set to the risc_data_i)
|
// data is set to the risc_data_i)
|
wire BitCounter_Lt40;
|
wire BitCounter_Lt40;
|
|
|
`endif
|
`endif
|
|
|
|
|
assign trst = ~trst_in; // trst_pad_i is active low
|
assign trst = ~trst_in; // trst_pad_i is active low
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* JTAG_DR: JTAG Data Register *
|
* JTAG_DR: JTAG Data Register *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg TDOData;
|
reg TDOData;
|
|
|
|
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
else
|
else
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
else
|
else
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
end
|
end
|
else
|
else
|
if(CHAIN_SELECTSelected & ShiftDR)
|
if(CHAIN_SELECTSelected & ShiftDR)
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
else
|
else
|
if(DEBUGSelected & ShiftDR)
|
if(DEBUGSelected & ShiftDR)
|
begin
|
begin
|
if(RiscDebugScanChain | WishboneScanChain)
|
if(RiscDebugScanChain | WishboneScanChain)
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
end
|
end
|
end
|
end
|
|
|
wire [73:0] RISC_Data;
|
wire [73:0] RISC_Data;
|
wire [46:0] Register_Data;
|
wire [46:0] Register_Data;
|
wire [73:0] WISHBONE_Data;
|
wire [73:0] WISHBONE_Data;
|
wire [12:0] chain_sel_data;
|
wire [12:0] chain_sel_data;
|
wire wb_Access_wbClk;
|
wire wb_Access_wbClk;
|
|
|
|
|
reg select_crc_out;
|
reg select_crc_out;
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
select_crc_out <= 0;
|
select_crc_out <= 0;
|
else
|
else
|
if( RegisterScanChain & BitCounter_Eq5 |
|
if( RegisterScanChain & BitCounter_Eq5 |
|
RiscDebugScanChain & BitCounter_Eq32 |
|
RiscDebugScanChain & BitCounter_Eq32 |
|
WishboneScanChain & BitCounter_Eq32 )
|
WishboneScanChain & BitCounter_Eq32 )
|
select_crc_out <=#Tp tdi;
|
select_crc_out <=#Tp tdi;
|
else
|
else
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
select_crc_out <=#Tp 1;
|
select_crc_out <=#Tp 1;
|
else
|
else
|
if(UpdateDR)
|
if(UpdateDR)
|
select_crc_out <=#Tp 0;
|
select_crc_out <=#Tp 0;
|
end
|
end
|
|
|
wire [8:0] send_crc;
|
wire [8:0] send_crc;
|
|
|
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
|
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
|
{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
|
{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
|
|
|
assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
|
assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
|
assign Register_Data = {send_crc, DataReadLatch, 6'h0};
|
assign Register_Data = {send_crc, DataReadLatch, 6'h0};
|
assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
|
assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
|
assign chain_sel_data = {send_crc, 4'h0};
|
assign chain_sel_data = {send_crc, 4'h0};
|
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
`endif
|
`endif
|
|
|
//TDO is changing on the falling edge of tck
|
//TDO is changing on the falling edge of tck
|
always @ (negedge tck or posedge trst)
|
always @ (negedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
begin
|
begin
|
TDOData <= #Tp 0;
|
TDOData <= #Tp 0;
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
ReadBuffer_Tck<=#Tp 0;
|
ReadBuffer_Tck<=#Tp 0;
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
if(UpdateDR)
|
if(UpdateDR)
|
begin
|
begin
|
TDOData <= #Tp CrcMatch;
|
TDOData <= #Tp CrcMatch;
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample in the trace buffer is valid
|
if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample in the trace buffer is valid
|
ReadBuffer_Tck<=#Tp 1; // Increment read pointer
|
ReadBuffer_Tck<=#Tp 1; // Increment read pointer
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
begin
|
begin
|
if(IDCODESelected)
|
if(IDCODESelected)
|
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
|
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
|
else
|
else
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
else
|
else
|
if(DEBUGSelected)
|
if(DEBUGSelected)
|
begin
|
begin
|
if(RiscDebugScanChain)
|
if(RiscDebugScanChain)
|
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
|
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
else
|
else
|
if(WishboneScanChain)
|
if(WishboneScanChain)
|
TDOData <= #Tp WISHBONE_Data[BitCounter]; // Data read from the WISHBONE slave
|
TDOData <= #Tp WISHBONE_Data[BitCounter]; // Data read from the WISHBONE slave
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
else
|
else
|
if(TraceTestScanChain)
|
if(TraceTestScanChain)
|
TDOData <= #Tp Trace_Data[BitCounter]; // Data from the trace buffer is shifted out
|
TDOData <= #Tp Trace_Data[BitCounter]; // Data from the trace buffer is shifted out
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TDOData <= #Tp 0;
|
TDOData <= #Tp 0;
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
ReadBuffer_Tck<=#Tp 0;
|
ReadBuffer_Tck<=#Tp 0;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
//synopsys translate_off
|
//synopsys translate_off
|
always @ (posedge tck)
|
always @ (posedge tck)
|
begin
|
begin
|
if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
|
if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(ShiftDR & DEBUGSelected)
|
if(ShiftDR & DEBUGSelected)
|
begin
|
begin
|
if(RiscDebugScanChain & BitCounter > 73)
|
if(RiscDebugScanChain & BitCounter > 73)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(RegisterScanChain & BitCounter > 46)
|
if(RegisterScanChain & BitCounter > 46)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(WishboneScanChain & BitCounter > 73)
|
if(WishboneScanChain & BitCounter > 73)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
else
|
else
|
if(TraceTestScanChain & BitCounter > 47)
|
if(TraceTestScanChain & BitCounter > 47)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: JTAG_DR *
|
* End: JTAG_DR *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* CHAIN_SELECT logic *
|
* CHAIN_SELECT logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
else
|
else
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
|
end
|
end
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Register read/write logic *
|
* Register read/write logic *
|
* RISC registers read/write logic *
|
* RISC registers read/write logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
begin
|
begin
|
ADDR[31:0] <=#Tp 32'h0;
|
ADDR[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
RW <=#Tp 1'b0;
|
RW <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RISCAccessTck <=#Tp 1'b0;
|
RISCAccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'h0;
|
wb_AccessTck <=#Tp 1'h0;
|
end
|
end
|
else
|
else
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
begin
|
begin
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
begin
|
begin
|
ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
|
ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
|
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
|
RegAccessTck <=#Tp 1'b1;
|
RegAccessTck <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain)
|
if(RiscDebugScanChain)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck <=#Tp 1'b1;
|
RISCAccessTck <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(WishboneScanChain)
|
if(WishboneScanChain)
|
begin
|
begin
|
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
|
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
wb_AccessTck <=#Tp 1'b1; //
|
wb_AccessTck <=#Tp 1'b1; //
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RISCAccessTck <=#Tp 1'b0;
|
RISCAccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wb_adr_o = ADDR;
|
assign wb_adr_o = ADDR;
|
assign wb_we_o = RW;
|
assign wb_we_o = RW;
|
assign wb_dat_o = DataOut;
|
assign wb_dat_o = DataOut;
|
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
|
|
|
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
);
|
);
|
|
|
|
|
// Synchronizing the wb_Access signal to wishbone clock
|
// Synchronizing the wb_Access signal to wishbone clock
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
// Delayed signals used for accessing registers and RISC
|
// Delayed signals used for accessing registers and RISC
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RISCAccess_q <=#Tp RISCAccess;
|
RISCAccess_q <=#Tp RISCAccess;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
end
|
end
|
end
|
end
|
|
|
// Chip select and read/write signals for accessing RISC
|
// Chip select and read/write signals for accessing RISC
|
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
|
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
|
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
|
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
|
|
|
|
|
reg wb_Access_wbClk_q;
|
reg wb_Access_wbClk_q;
|
// Delayed signals used for accessing WISHBONE
|
// Delayed signals used for accessing WISHBONE
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
wb_Access_wbClk_q <=#Tp 1'b0;
|
wb_Access_wbClk_q <=#Tp 1'b0;
|
else
|
else
|
wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
|
wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
wb_cyc_o <=#Tp 1'b0;
|
wb_cyc_o <=#Tp 1'b0;
|
else
|
else
|
if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
|
if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
|
wb_cyc_o <=#Tp 1'b1;
|
wb_cyc_o <=#Tp 1'b1;
|
else
|
else
|
if(wb_ack_i | wb_err_i)
|
if(wb_ack_i | wb_err_i)
|
wb_cyc_o <=#Tp 1'b0;
|
wb_cyc_o <=#Tp 1'b0;
|
end
|
end
|
|
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
|
|
|
|
// Latching data read from registers
|
// Latching data read from registers
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WBReadLatch[31:0]<=#Tp 32'h0;
|
WBReadLatch[31:0]<=#Tp 32'h0;
|
else
|
else
|
if(wb_ack_i)
|
if(wb_ack_i)
|
WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
|
WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
|
end
|
end
|
|
|
// Latching WISHBONE error cycle
|
// Latching WISHBONE error cycle
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WBErrorLatch<=#Tp 1'b0;
|
WBErrorLatch<=#Tp 1'b0;
|
else
|
else
|
if(wb_err_i)
|
if(wb_err_i)
|
WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
|
WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
|
else
|
else
|
if(wb_ack_i)
|
if(wb_ack_i)
|
WBErrorLatch<=#Tp 1'b0; // Clearing status
|
WBErrorLatch<=#Tp 1'b0; // Clearing status
|
end
|
end
|
|
|
|
|
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
|
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
|
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
|
`else
|
`else
|
assign risc_stall_o = RiscStall_access | RiscStall_reg;
|
assign risc_stall_o = RiscStall_access | RiscStall_reg;
|
`endif
|
`endif
|
|
|
assign reset_o = RiscReset_reg;
|
assign reset_o = RiscReset_reg;
|
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
|
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
|
`else
|
`else
|
always @ (RiscStall_write_access or RiscStall_read_access)
|
always @ (RiscStall_write_access or RiscStall_read_access)
|
`endif
|
`endif
|
begin
|
begin
|
if(RiscStall_write_access)
|
if(RiscStall_write_access)
|
opselect_o = `DEBUG_WRITE_SPR; // Write spr
|
opselect_o = `DEBUG_WRITE_SPR; // Write spr
|
else
|
else
|
if(RiscStall_read_access)
|
if(RiscStall_read_access)
|
opselect_o = `DEBUG_READ_SPR; // Read spr
|
opselect_o = `DEBUG_READ_SPR; // Read spr
|
else
|
else
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
opselect_o = opselect_trace;
|
opselect_o = opselect_trace;
|
`else
|
`else
|
opselect_o = 3'h0;
|
opselect_o = 3'h0;
|
`endif
|
`endif
|
end
|
end
|
|
|
|
|
// Latching data read from RISC or registers
|
// Latching data read from RISC or registers
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
DataReadLatch[31:0]<=#Tp 0;
|
DataReadLatch[31:0]<=#Tp 0;
|
else
|
else
|
if(RISCAccess_q & ~RISCAccess_q2)
|
if(RISCAccess_q & ~RISCAccess_q2)
|
DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
|
DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
|
else
|
else
|
if(RegAccess_q & ~RegAccess_q2)
|
if(RegAccess_q & ~RegAccess_q2)
|
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
end
|
end
|
|
|
assign risc_addr_o = ADDR;
|
assign risc_addr_o = ADDR;
|
assign risc_data_o = DataOut;
|
assign risc_data_o = DataOut;
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Read Trace buffer logic *
|
* Read Trace buffer logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
);
|
);
|
|
|
|
|
|
|
always @(posedge risc_clk_i or posedge wb_rst_i)
|
always @(posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
ReadTraceBuffer_q <=#Tp 0;
|
ReadTraceBuffer_q <=#Tp 0;
|
else
|
else
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
end
|
end
|
|
|
assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
|
assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
|
|
|
`endif
|
`endif
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Read Trace buffer logic *
|
* End: Read Trace buffer logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Bit counter *
|
* Bit counter *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
BitCounter[7:0]<=#Tp 0;
|
BitCounter[7:0]<=#Tp 0;
|
else
|
else
|
if(ShiftDR)
|
if(ShiftDR)
|
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
|
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
|
else
|
else
|
if(UpdateDR)
|
if(UpdateDR)
|
BitCounter[7:0]<=#Tp 0;
|
BitCounter[7:0]<=#Tp 0;
|
end
|
end
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Bit counter *
|
* End: Bit counter *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Connecting Registers *
|
* Connecting Registers *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
|
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
|
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
|
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
|
.bp(bp_i), .reset(wb_rst_i),
|
.bp(bp_i), .reset(wb_rst_i),
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
|
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
|
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
|
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
|
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
|
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
|
.QualifOper(QualifOper), .RecordPC(RecordPC),
|
.QualifOper(QualifOper), .RecordPC(RecordPC),
|
.RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
|
.RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
|
.RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
|
.RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
|
.RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
|
.RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
|
.WpTriggerValid(WpTriggerValid),
|
.WpTriggerValid(WpTriggerValid),
|
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
|
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
|
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
|
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
|
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
|
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
|
.IQualifValid(IQualifValid),
|
.IQualifValid(IQualifValid),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
`endif
|
`endif
|
.risc_stall(RiscStall_reg), .risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
|
.risc_stall(RiscStall_reg), .risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
|
|
|
);
|
);
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Connecting Registers *
|
* End: Connecting Registers *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Connecting CRC module *
|
* Connecting CRC module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
wire AsyncResetCrc = trst;
|
wire AsyncResetCrc = trst;
|
wire SyncResetCrc = UpdateDR_q;
|
wire SyncResetCrc = UpdateDR_q;
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
|
|
assign BitCounter_Lt4 = BitCounter<4;
|
assign BitCounter_Lt4 = BitCounter<4;
|
assign BitCounter_Eq5 = BitCounter==5;
|
assign BitCounter_Eq5 = BitCounter==5;
|
assign BitCounter_Eq32 = BitCounter==32;
|
assign BitCounter_Eq32 = BitCounter==32;
|
assign BitCounter_Lt38 = BitCounter<38;
|
assign BitCounter_Lt38 = BitCounter<38;
|
assign BitCounter_Lt65 = BitCounter<65;
|
assign BitCounter_Lt65 = BitCounter<65;
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign BitCounter_Lt40 = BitCounter<40;
|
assign BitCounter_Lt40 = BitCounter<40;
|
`endif
|
`endif
|
|
|
|
|
wire EnableCrcIn = ShiftDR &
|
wire EnableCrcIn = ShiftDR &
|
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
);
|
);
|
|
|
wire EnableCrcOut= ShiftDR &
|
wire EnableCrcOut= ShiftDR &
|
(
|
(
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
`endif
|
`endif
|
);
|
);
|
|
|
// Calculating crc for input data
|
// Calculating crc for input data
|
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
.crc_out(CalculatedCrcIn), .clk(tck));
|
.crc_out(CalculatedCrcIn), .clk(tck));
|
|
|
// Calculating crc for output data
|
// Calculating crc for output data
|
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
.crc_out(CalculatedCrcOut), .clk(tck));
|
.crc_out(CalculatedCrcOut), .clk(tck));
|
|
|
|
|
// Generating CrcMatch signal
|
// Generating CrcMatch signal
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
CrcMatch <=#Tp 1'b0;
|
CrcMatch <=#Tp 1'b0;
|
else
|
else
|
if(Exit1DR)
|
if(Exit1DR)
|
begin
|
begin
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
|
else
|
else
|
begin
|
begin
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
else
|
else
|
if(RiscDebugScanChain)
|
if(RiscDebugScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
else
|
else
|
if(WishboneScanChain)
|
if(WishboneScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
// Active chain
|
// Active chain
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
|
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
`endif
|
`endif
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Connecting CRC module *
|
* End: Connecting CRC module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Connecting trace module *
|
* Connecting trace module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
|
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.WpTrigger(WpTrigger),
|
.WpTrigger(WpTrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
|
.RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
|
.RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
|
.RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
|
.RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
|
.RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
|
.RecordINSTR(RecordINSTR),
|
.RecordINSTR(RecordINSTR),
|
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
|
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
|
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
|
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
|
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
|
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
|
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
|
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
|
.ReadBuffer(ReadTraceBufferPulse),
|
.ReadBuffer(ReadTraceBufferPulse),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
|
);
|
);
|
`endif
|
`endif
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Connecting trace module *
|
* End: Connecting trace module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|