// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
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// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
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// Note; 1) Please include "+define+ OEb" in running script if you want to check
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// Note; 1) Please include "+define+ OEb" in running script if you want to check
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// timing in the case of OE_ being set.
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// timing in the case of OE_ being set.
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// 2) Please specify access time by defining tAC_10 or tAC_12.
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// 2) Please specify access time by defining tAC_10 or tAC_12.
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// `define OEb
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// `define OEb
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`define tAC_10
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`define tAC_10
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
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module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
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parameter dqbits = 16;
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parameter dqbits = 16;
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parameter memdepth = 262143;
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parameter memdepth = 262143;
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parameter addbits = 18;
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parameter addbits = 18;
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parameter Toha = 2;
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parameter Toha = 2;
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parameter Tsa = 2;
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parameter Tsa = 2;
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`ifdef tAC_10
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`ifdef tAC_10
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parameter Taa = 10,
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parameter Taa = 10,
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Thzce = 3,
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Thzce = 3,
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Thzwe = 5;
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Thzwe = 5;
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`endif
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`endif
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`ifdef tAC_12
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`ifdef tAC_12
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parameter Taa = 12,
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parameter Taa = 12,
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Thzce = 5,
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Thzce = 5,
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Thzwe = 6;
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Thzwe = 6;
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`endif
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`endif
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input CE_, OE_, WE_, LB_, UB_;
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input CE_, OE_, WE_, LB_, UB_;
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input [(addbits - 1) : 0] A;
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input [(addbits - 1) : 0] A;
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inout [(dqbits - 1) : 0] IO;
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inout [(dqbits - 1) : 0] IO;
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wire [(dqbits - 1) : 0] dout;
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wire [(dqbits - 1) : 0] dout;
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reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
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reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
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reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
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reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
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// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
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// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
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wire r_en = WE_ & (~CE_) & (~OE_);
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wire r_en = WE_ & (~CE_) & (~OE_);
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wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
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wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
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assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
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assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
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initial
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initial
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$timeformat (-9, 0.1, " ns", 10);
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$timeformat (-9, 0.1, " ns", 10);
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assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
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assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
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assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
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assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
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always @(A or w_en)
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always @(A or w_en)
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begin
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begin
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#Tsa
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#Tsa
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if (w_en)
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if (w_en)
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#Thzwe
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#Thzwe
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begin
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begin
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bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
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bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
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bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
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bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
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end
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end
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end
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end
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// Timing Check
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// Timing Check
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`ifdef tAC_10
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`ifdef tAC_10
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specify
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specify
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specparam
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specparam
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tSA = 0,
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tSA = 0,
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tAW = 8,
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tAW = 8,
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tSCE = 8,
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tSCE = 8,
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tSD = 6,
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tSD = 6,
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tPWE2 = 10,
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tPWE2 = 10,
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tPWE1 = 8,
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tPWE1 = 8,
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tPBW = 8;
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tPBW = 8;
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`else
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`else
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`ifdef tAC_10
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`ifdef tAC_10
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specify
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specify
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specparam
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specparam
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tSA = 0,
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tSA = 0,
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tAW = 8,
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tAW = 8,
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tSCE = 8,
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tSCE = 8,
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tSD = 6,
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tSD = 6,
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tPWE2 = 12,
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tPWE2 = 12,
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tPWE1 = 8,
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tPWE1 = 8,
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tPBW = 8;
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tPBW = 8;
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`endif
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`endif
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`endif
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`endif
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$setup (A, negedge CE_, tSA);
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$setup (A, negedge CE_, tSA);
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// $setup (A, posedge CE_, tAW);
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// $setup (A, posedge CE_, tAW);
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// $setup (IO, posedge CE_, tSD);
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// $setup (IO, posedge CE_, tSD);
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$setup (A, negedge WE_, tSA);
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$setup (A, negedge WE_, tSA);
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// $setup (IO, posedge WE_, tSD);
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// $setup (IO, posedge WE_, tSD);
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$setup (A, negedge LB_, tSA);
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$setup (A, negedge LB_, tSA);
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$setup (A, negedge UB_, tSA);
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$setup (A, negedge UB_, tSA);
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$width (negedge CE_, tSCE);
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$width (negedge CE_, tSCE);
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$width (negedge LB_, tPBW);
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$width (negedge LB_, tPBW);
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$width (negedge UB_, tPBW);
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$width (negedge UB_, tPBW);
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`ifdef OEb
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`ifdef OEb
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$width (negedge WE_, tPWE1);
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$width (negedge WE_, tPWE1);
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`else
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`else
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$width (negedge WE_, tPWE2);
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$width (negedge WE_, tPWE2);
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`endif
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`endif
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endspecify
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endspecify
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endmodule
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endmodule
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