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----------------------------------------------------------------------------------
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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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--
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-- Create Date: 01:21:32 06/30/2011
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-- Create Date: 01:21:32 06/30/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: debounce_atlys_top
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-- Module Name: debounce_atlys_top
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-- Project Name: debounce_vhdl
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-- Project Name: debounce_vhdl
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-- Target Devices: Spartan-6 LX45
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-- Target Devices: Spartan-6 LX45
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-- Tool versions: ISE 13.1
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-- Tool versions: ISE 13.1
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-- Description:
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-- Description:
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-- This is a verification project for the Digilent Atlys board, to test the GRP_DEBOUNCE core.
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-- This is a verification project for the Digilent Atlys board, to test the GRP_DEBOUNCE core.
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-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
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-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
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--
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--
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-- See the "debounce_atlys.ucf" file for pin assignments.
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-- See the "debounce_atlys.ucf" file for pin assignments.
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-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
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-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
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-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
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-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
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-- digital pod port.
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-- digital pod port.
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--
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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--
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-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
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-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
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-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
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-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
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-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
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-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
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-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
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-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
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-- this change made the design go up to 288MHz, after synthesis.
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-- this change made the design go up to 288MHz, after synthesis.
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-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
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-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
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-- external monitoring pins to the VHDCI ports.
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-- external monitoring pins to the VHDCI ports.
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 6.25MHz, 1MHz and 500kHz
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-- 6.25MHz, 1MHz and 500kHz
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
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-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
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--
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--
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity debounce_atlys_top is
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entity debounce_atlys_top is
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Port (
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Port (
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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--- input slide switches ---
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--- input slide switches ---
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sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
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sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
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--- output LEDs ----
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--- output LEDs ----
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led_o : out std_logic_vector (7 downto 0); -- output leds
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led_o : out std_logic_vector (7 downto 0); -- output leds
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--- debug outputs ---
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--- debug outputs ---
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strb_o : out std_logic; -- core strobe output
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strb_o : out std_logic; -- core strobe output
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dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
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dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
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);
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);
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end debounce_atlys_top;
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end debounce_atlys_top;
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architecture rtl of debounce_atlys_top is
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architecture rtl of debounce_atlys_top is
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--=============================================================================================
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--=============================================================================================
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-- Constants
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-- Constants
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--=============================================================================================
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--=============================================================================================
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-- debounce generics
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-- debounce generics
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constant N : integer := 8; -- 8 bits (8 switch inputs)
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constant N : integer := 8; -- 8 bits (8 switch inputs)
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constant CNT_VAL : integer := 1000; -- debounce period = 1000 * 10 ns (10 us)
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constant CNT_VAL : integer := 5000; -- debounce period = 1000 * 10 ns (50 us)
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--=============================================================================================
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--=============================================================================================
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-- Signals for internal operation
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-- Signals for internal operation
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--=============================================================================================
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--=============================================================================================
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--- switch debouncer signals ---
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--- switch debouncer signals ---
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
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signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
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signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
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signal sw_new : std_logic := '0';
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signal sw_new : std_logic := '0';
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-- debug output signals
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-- debug output signals
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signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
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signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
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signal dbg : std_logic_vector (15 downto 0) := (others => '0');
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signal dbg : std_logic_vector (15 downto 0) := (others => '0');
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begin
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begin
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--=============================================================================================
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--=============================================================================================
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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--=============================================================================================
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--=============================================================================================
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-- debounce for the input switches, with new data strobe output
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-- debounce for the input switches, with new data strobe output
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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generic map (N => N, CNT_VAL => CNT_VAL)
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generic map (N => N, CNT_VAL => CNT_VAL)
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port map(
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port map(
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clk_i => gclk_i, -- system clock
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clk_i => gclk_i, -- system clock
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data_i => sw_i, -- noisy input data
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data_i => sw_i, -- noisy input data
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data_o => sw_data, -- registered stable output data
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data_o => sw_data, -- registered stable output data
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strb_o => sw_new -- transition detection
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strb_o => sw_new -- transition detection
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);
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);
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--=============================================================================================
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--=============================================================================================
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-- REGISTER TRANSFER PROCESSES
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-- REGISTER TRANSFER PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- data registers: synchronous to the system clock
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-- data registers: synchronous to the system clock
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dat_reg_proc : process (gclk_i) is
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dat_reg_proc : process (gclk_i) is
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begin
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begin
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-- transfer switch data when new switch is detected
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-- transfer switch data when new switch is detected
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if gclk_i'event and gclk_i = '1' then
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if gclk_i'event and gclk_i = '1' then
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if sw_new = '1' then -- clock enable
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if sw_new = '1' then -- clock enable
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sw_reg <= sw_data; -- only provide local reset for the state registers
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sw_reg <= sw_data; -- only provide local reset for the state registers
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end if;
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end if;
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end if;
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end if;
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end process dat_reg_proc;
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end process dat_reg_proc;
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--=============================================================================================
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--=============================================================================================
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-- COMBINATORIAL LOGIC PROCESSES
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-- COMBINATORIAL LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- LED register update
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-- LED register update
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leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
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leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
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-- update debug register
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-- update debug register
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dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has debounced switch data
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dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has direct switch connections
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dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has direct switch connections
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dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has debounced switch data
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--=============================================================================================
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--=============================================================================================
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-- OUTPUT LOGIC PROCESSES
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-- OUTPUT LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- connect leds_reg signal to LED outputs
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-- connect leds_reg signal to LED outputs
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led_o_proc: led_o <= leds_reg; -- drive the output leds
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led_o_proc: led_o <= leds_reg; -- drive the output leds
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--=============================================================================================
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--=============================================================================================
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-- DEBUG LOGIC PROCESSES
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-- DEBUG LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- connect the debug vector outputs
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-- connect the debug vector outputs
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strb_o_proc: strb_o <= sw_new; -- connect strobe debug out
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strb_o_proc: strb_o <= sw_new; -- connect strobe debug out
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dbg_o_proc: dbg_o <= dbg; -- drive the logic analyzer port
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dbg_o_proc: dbg_o <= dbg; -- drive the logic analyzer port
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end rtl;
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end rtl;
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