DEBOUNCER_VHDL
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DEBOUNCER_VHDL
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This is a very simple switch debouncer written in VHDL.
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This is a very simple switch debouncer written in VHDL.
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It is a pipelined, fully static design, and handles a group of signals with common debouncing.
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It is a pipelined, fully static design, and handles a group of signals with common debouncing.
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The switch grouping in a std_logic_vector() has 2 main advantages:
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The switch grouping in a std_logic_vector() has 2 main advantages:
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-> saves silicon space, by having a common counter;
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-> saves silicon space, by having a common counter;
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-> guarantees that a given switch set will not show asynchronous state changes relative to each other inside the debouncing time window;
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-> guarantees that a given switch set will not show asynchronous state changes relative to each other inside the debouncing time window;
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The debouncer has a very simple interface, and is straightforward to use. No vendor-specific syntax or code is used in this design.
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The debouncer has a very simple interface, and is straightforward to use. No vendor-specific syntax or code is used in this design.
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VHDL files for spi master/slave project:
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VHDL files for spi master/slave project:
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grp_debouncer.vhd switch debouncer model
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grp_debouncer.vhd switch debouncer model
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grp_debouncer_test.vhd testbench for simulating the switch debouncer model
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The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device.
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The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device.
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ISIM SIMULATION
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ISIM SIMULATION
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VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest Spartan-6 device.
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VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest Spartan-6 device.
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SILICON VERIFICATION
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SILICON VERIFICATION
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Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board.
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Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board.
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If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
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If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
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If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
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If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
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http://opencores.org/project,debouncer_vhdl,bugtracker.
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http://opencores.org/project,debouncer_vhdl,bugtracker.
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If you use this module, please drop some feedback at jdoin@opencores.org
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If you use this module, please drop some feedback at jdoin@opencores.org
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In any case, thank you for testing and using this core.
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In any case, thank you for testing and using this core.
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Jonny Doin
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Jonny Doin
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jdoin@opencores.org
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jdoin@opencores.org
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