/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// DES ////
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//// DES ////
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//// DES Top Level module ////
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//// DES Top Level module ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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module des(desOut, desIn, key, decrypt, clk);
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module des(desOut, desIn, key, decrypt, clk);
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output [63:0] desOut;
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output [63:0] desOut;
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input [63:0] desIn;
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input [63:0] desIn;
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input [55:0] key;
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input [55:0] key;
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input decrypt;
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input decrypt;
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input clk;
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input clk;
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wire [1:64] IP, FP;
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wire [1:64] IP, FP;
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reg [63:0] desIn_r;
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reg [63:0] desIn_r;
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reg [55:0] key_r;
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reg [55:0] key_r;
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reg [63:0] desOut;
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reg [63:0] desOut;
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reg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
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reg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
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reg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
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reg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
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wire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
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wire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
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wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
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wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
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wire [1:48] K10, K11, K12, K13, K14, K15, K16;
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wire [1:48] K10, K11, K12, K13, K14, K15, K16;
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// Register the 56 bit key
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// Register the 56 bit key
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always @(posedge clk)
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always @(posedge clk)
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key_r <= #1 key;
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key_r <= #1 key;
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// Register the 64 bit input
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// Register the 64 bit input
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always @(posedge clk)
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always @(posedge clk)
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desIn_r <= #1 desIn;
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desIn_r <= #1 desIn;
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// XOR 32 bit out15 with 32 bit L14 ( FP 1:32 )
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// XOR 32 bit out15 with 32 bit L14 ( FP 1:32 )
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// then concatinate the 32 bit R14 value ( FP 33:64 )
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// then concatinate the 32 bit R14 value ( FP 33:64 )
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// This value ( FP 1:64 ) is then registered by the desOut[63:0] register
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// This value ( FP 1:64 ) is then registered by the desOut[63:0] register
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assign FP = { (out15 ^ L14), R14};
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assign FP = { (out15 ^ L14), R14};
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// Key schedule provides a linear means of intermixing the 56 bit key to form a
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// Key schedule provides a linear means of intermixing the 56 bit key to form a
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// different 48 bit key for each of the 16 bit rounds
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// different 48 bit key for each of the 16 bit rounds
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key_sel uk(
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key_sel uk(
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.clk( clk ),
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.clk( clk ),
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.K( key_r ),
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.K( key_r ),
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.decrypt( decrypt ),
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.decrypt( decrypt ),
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.K1( K1 ),
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.K1( K1 ),
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.K2( K2 ),
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.K2( K2 ),
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.K3( K3 ),
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.K3( K3 ),
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.K4( K4 ),
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.K4( K4 ),
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.K5( K5 ),
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.K5( K5 ),
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.K6( K6 ),
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.K6( K6 ),
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.K7( K7 ),
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.K7( K7 ),
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.K8( K8 ),
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.K8( K8 ),
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.K9( K9 ),
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.K9( K9 ),
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.K10( K10 ),
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.K10( K10 ),
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.K11( K11 ),
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.K11( K11 ),
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.K12( K12 ),
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.K12( K12 ),
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.K13( K13 ),
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.K13( K13 ),
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.K14( K14 ),
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.K14( K14 ),
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.K15( K15 ),
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.K15( K15 ),
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.K16( K16 )
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.K16( K16 )
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);
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);
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// 16 CRP blocks
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// 16 CRP blocks
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crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
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crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
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crp u1( .P(out1), .R(R0), .K_sub(K2) );
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crp u1( .P(out1), .R(R0), .K_sub(K2) );
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crp u2( .P(out2), .R(R1), .K_sub(K3) );
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crp u2( .P(out2), .R(R1), .K_sub(K3) );
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crp u3( .P(out3), .R(R2), .K_sub(K4) );
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crp u3( .P(out3), .R(R2), .K_sub(K4) );
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crp u4( .P(out4), .R(R3), .K_sub(K5) );
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crp u4( .P(out4), .R(R3), .K_sub(K5) );
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crp u5( .P(out5), .R(R4), .K_sub(K6) );
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crp u5( .P(out5), .R(R4), .K_sub(K6) );
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crp u6( .P(out6), .R(R5), .K_sub(K7) );
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crp u6( .P(out6), .R(R5), .K_sub(K7) );
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crp u7( .P(out7), .R(R6), .K_sub(K8) );
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crp u7( .P(out7), .R(R6), .K_sub(K8) );
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crp u8( .P(out8), .R(R7), .K_sub(K9) );
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crp u8( .P(out8), .R(R7), .K_sub(K9) );
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crp u9( .P(out9), .R(R8), .K_sub(K10) );
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crp u9( .P(out9), .R(R8), .K_sub(K10) );
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crp u10( .P(out10), .R(R9), .K_sub(K11) );
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crp u10( .P(out10), .R(R9), .K_sub(K11) );
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crp u11( .P(out11), .R(R10), .K_sub(K12) );
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crp u11( .P(out11), .R(R10), .K_sub(K12) );
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crp u12( .P(out12), .R(R11), .K_sub(K13) );
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crp u12( .P(out12), .R(R11), .K_sub(K13) );
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crp u13( .P(out13), .R(R12), .K_sub(K14) );
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crp u13( .P(out13), .R(R12), .K_sub(K14) );
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crp u14( .P(out14), .R(R13), .K_sub(K15) );
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crp u14( .P(out14), .R(R13), .K_sub(K15) );
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crp u15( .P(out15), .R(R14), .K_sub(K16) );
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crp u15( .P(out15), .R(R14), .K_sub(K16) );
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// 32 bit L0 get upper 32 bits of IP
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// 32 bit L0 get upper 32 bits of IP
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always @(posedge clk)
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always @(posedge clk)
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L0 <= #1 IP[33:64];
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L0 <= #1 IP[33:64];
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// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0
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// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0
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always @(posedge clk)
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always @(posedge clk)
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R0 <= #1 IP[01:32] ^ out0;
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R0 <= #1 IP[01:32] ^ out0;
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// 32 bit L1 gets 32 bit R0
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// 32 bit L1 gets 32 bit R0
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always @(posedge clk)
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always @(posedge clk)
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L1 <= #1 R0;
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L1 <= #1 R0;
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// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1
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// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1
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always @(posedge clk)
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always @(posedge clk)
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R1 <= #1 L0 ^ out1;
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R1 <= #1 L0 ^ out1;
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// 32 bit L2 gets 32 bit R1
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// 32 bit L2 gets 32 bit R1
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always @(posedge clk)
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always @(posedge clk)
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L2 <= #1 R1;
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L2 <= #1 R1;
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// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2
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// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2
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always @(posedge clk)
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always @(posedge clk)
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R2 <= #1 L1 ^ out2;
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R2 <= #1 L1 ^ out2;
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always @(posedge clk)
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always @(posedge clk)
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L3 <= #1 R2;
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L3 <= #1 R2;
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always @(posedge clk)
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always @(posedge clk)
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R3 <= #1 L2 ^ out3;
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R3 <= #1 L2 ^ out3;
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always @(posedge clk)
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always @(posedge clk)
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L4 <= #1 R3;
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L4 <= #1 R3;
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always @(posedge clk)
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always @(posedge clk)
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R4 <= #1 L3 ^ out4;
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R4 <= #1 L3 ^ out4;
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always @(posedge clk)
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always @(posedge clk)
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L5 <= #1 R4;
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L5 <= #1 R4;
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always @(posedge clk)
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always @(posedge clk)
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R5 <= #1 L4 ^ out5;
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R5 <= #1 L4 ^ out5;
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always @(posedge clk)
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always @(posedge clk)
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L6 <= #1 R5;
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L6 <= #1 R5;
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always @(posedge clk)
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always @(posedge clk)
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R6 <= #1 L5 ^ out6;
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R6 <= #1 L5 ^ out6;
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always @(posedge clk)
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always @(posedge clk)
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L7 <= #1 R6;
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L7 <= #1 R6;
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always @(posedge clk)
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always @(posedge clk)
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R7 <= #1 L6 ^ out7;
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R7 <= #1 L6 ^ out7;
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always @(posedge clk)
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always @(posedge clk)
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L8 <= #1 R7;
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L8 <= #1 R7;
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always @(posedge clk)
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always @(posedge clk)
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R8 <= #1 L7 ^ out8;
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R8 <= #1 L7 ^ out8;
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always @(posedge clk)
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always @(posedge clk)
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L9 <= #1 R8;
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L9 <= #1 R8;
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always @(posedge clk)
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always @(posedge clk)
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R9 <= #1 L8 ^ out9;
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R9 <= #1 L8 ^ out9;
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always @(posedge clk)
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always @(posedge clk)
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L10 <= #1 R9;
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L10 <= #1 R9;
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always @(posedge clk)
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always @(posedge clk)
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R10 <= #1 L9 ^ out10;
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R10 <= #1 L9 ^ out10;
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always @(posedge clk)
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always @(posedge clk)
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L11 <= #1 R10;
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L11 <= #1 R10;
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always @(posedge clk)
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always @(posedge clk)
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R11 <= #1 L10 ^ out11;
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R11 <= #1 L10 ^ out11;
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always @(posedge clk)
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always @(posedge clk)
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L12 <= #1 R11;
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L12 <= #1 R11;
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always @(posedge clk)
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always @(posedge clk)
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R12 <= #1 L11 ^ out12;
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R12 <= #1 L11 ^ out12;
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always @(posedge clk)
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always @(posedge clk)
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L13 <= #1 R12;
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L13 <= #1 R12;
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always @(posedge clk)
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always @(posedge clk)
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R13 <= #1 L12 ^ out13;
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R13 <= #1 L12 ^ out13;
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always @(posedge clk)
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always @(posedge clk)
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L14 <= #1 R13;
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L14 <= #1 R13;
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always @(posedge clk)
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always @(posedge clk)
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R14 <= #1 L13 ^ out14;
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R14 <= #1 L13 ^ out14;
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// 32 bit L15 gets 32 bit R14
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// 32 bit L15 gets 32 bit R14
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always @(posedge clk)
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always @(posedge clk)
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L15 <= #1 R14;
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L15 <= #1 R14;
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// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15
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// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15
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always @(posedge clk)
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always @(posedge clk)
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R15 <= #1 L14 ^ out15;
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R15 <= #1 L14 ^ out15;
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// Perform the initial permutationi with the registerd desIn
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// Perform the initial permutationi with the registerd desIn
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assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
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assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
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desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
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desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
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desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],
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desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],
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desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],
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desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],
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desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40],
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desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40],
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desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31],
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desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31],
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desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
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desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
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desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
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desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
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desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
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desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
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desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
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desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
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desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };
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desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };
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// Perform the final permutation
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// Perform the final permutation
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always @(posedge clk)
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always @(posedge clk)
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desOut <= #1 { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
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desOut <= #1 { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
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FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
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FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
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FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
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FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
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FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
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FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
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FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
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FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
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FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
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FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
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FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
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FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
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FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
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FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
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endmodule
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endmodule
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