Release 9.2i par J.36
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Release 9.2i par J.36
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Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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thoreau:: Mon Jan 28 21:05:26 2008
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thoreau:: Mon Jan 28 21:05:26 2008
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par -w -intstyle ise -ol std -t 1 mysio_map.ncd mysio.ncd mysio.pcf
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par -w -intstyle ise -ol std -t 1 mysio_map.ncd mysio.ncd mysio.pcf
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Constraints file: mysio.pcf.
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Constraints file: mysio.pcf.
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Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.
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Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.
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"mysio" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4
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"mysio" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
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Device speed data version: "PRODUCTION 1.26 2007-04-13".
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Device speed data version: "PRODUCTION 1.26 2007-04-13".
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Design Summary Report:
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Design Summary Report:
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Number of External IOBs 35 out of 232 15%
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Number of External IOBs 35 out of 232 15%
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Number of External Input IOBs 11
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Number of External Input IOBs 11
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Number of External Input IBUFs 11
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Number of External Input IBUFs 11
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Number of LOCed External Input IBUFs 11 out of 11 100%
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Number of LOCed External Input IBUFs 11 out of 11 100%
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Number of External Output IOBs 24
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Number of External Output IOBs 24
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Number of External Output IOBs 24
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Number of External Output IOBs 24
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Number of LOCed External Output IOBs 24 out of 24 100%
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Number of LOCed External Output IOBs 24 out of 24 100%
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Number of External Bidir IOBs 0
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Number of External Bidir IOBs 0
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Number of BUFGMUXs 1 out of 24 4%
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Number of BUFGMUXs 1 out of 24 4%
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Number of RAMB16s 7 out of 20 35%
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Number of RAMB16s 7 out of 20 35%
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Number of Slices 784 out of 4656 16%
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Number of Slices 784 out of 4656 16%
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Number of SLICEMs 65 out of 2328 2%
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Number of SLICEMs 65 out of 2328 2%
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Overall effort level (-ol): Standard
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard
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Router effort level (-rl): Standard
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Starting initial Timing Analysis. REAL time: 3 secs
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Starting initial Timing Analysis. REAL time: 3 secs
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Finished initial Timing Analysis. REAL time: 3 secs
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Finished initial Timing Analysis. REAL time: 3 secs
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Starting Placer
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Starting Placer
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Phase 1.1
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Phase 1.1
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Phase 1.1 (Checksum:98b044) REAL time: 5 secs
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Phase 1.1 (Checksum:98b044) REAL time: 5 secs
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Phase 2.7
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Phase 2.7
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Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
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Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
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Phase 3.31
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
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Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
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Phase 4.2
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Phase 4.2
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.....
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.....
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Phase 4.2 (Checksum:989e4f) REAL time: 6 secs
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Phase 4.2 (Checksum:989e4f) REAL time: 6 secs
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Phase 5.30
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Phase 5.30
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Phase 5.30 (Checksum:2faf07b) REAL time: 6 secs
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Phase 5.30 (Checksum:2faf07b) REAL time: 6 secs
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Phase 6.8
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Phase 6.8
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..................................................
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..................................................
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..........
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..........
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..................................................
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..................................................
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...........
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...........
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..................
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..................
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...........................................................................................
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...........................................................................................
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Phase 6.8 (Checksum:c205ad) REAL time: 21 secs
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Phase 6.8 (Checksum:c205ad) REAL time: 21 secs
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Phase 7.5
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Phase 7.5
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Phase 7.5 (Checksum:42c1d79) REAL time: 21 secs
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Phase 7.5 (Checksum:42c1d79) REAL time: 21 secs
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Phase 8.18
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Phase 8.18
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Phase 8.18 (Checksum:4c4b3f8) REAL time: 30 secs
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Phase 8.18 (Checksum:4c4b3f8) REAL time: 30 secs
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Phase 9.5
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Phase 9.5
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Phase 9.5 (Checksum:55d4a77) REAL time: 30 secs
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Phase 9.5 (Checksum:55d4a77) REAL time: 30 secs
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REAL time consumed by placer: 31 secs
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REAL time consumed by placer: 31 secs
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CPU time consumed by placer: 31 secs
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CPU time consumed by placer: 31 secs
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Writing design to file mysio.ncd
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Writing design to file mysio.ncd
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Total REAL time to Placer completion: 31 secs
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Total REAL time to Placer completion: 31 secs
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Total CPU time to Placer completion: 31 secs
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Total CPU time to Placer completion: 31 secs
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Starting Router
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Starting Router
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Phase 1: 6359 unrouted; REAL time: 34 secs
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Phase 1: 6359 unrouted; REAL time: 34 secs
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Phase 2: 5861 unrouted; REAL time: 35 secs
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Phase 2: 5861 unrouted; REAL time: 35 secs
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Phase 3: 1866 unrouted; REAL time: 36 secs
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Phase 3: 1866 unrouted; REAL time: 36 secs
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Phase 4: 1866 unrouted; (23259) REAL time: 37 secs
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Phase 4: 1866 unrouted; (23259) REAL time: 37 secs
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Phase 5: 1939 unrouted; (198) REAL time: 38 secs
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Phase 5: 1939 unrouted; (198) REAL time: 38 secs
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Phase 6: 1948 unrouted; (0) REAL time: 38 secs
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Phase 6: 1948 unrouted; (0) REAL time: 38 secs
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Phase 7: 0 unrouted; (0) REAL time: 41 secs
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Phase 7: 0 unrouted; (0) REAL time: 41 secs
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Phase 8: 0 unrouted; (0) REAL time: 42 secs
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Phase 8: 0 unrouted; (0) REAL time: 42 secs
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WARNING:Route:455 - CLK Net:diogenes_cpu/pipestage2/big_op<13> may have excessive skew because
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WARNING:Route:455 - CLK Net:diogenes_cpu/pipestage2/big_op<13> may have excessive skew because
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0 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
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0 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
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Total REAL time to Router completion: 43 secs
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Total REAL time to Router completion: 43 secs
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Total CPU time to Router completion: 43 secs
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Total CPU time to Router completion: 43 secs
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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-------------------------------
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-------------------------------
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Generating "PAR" statistics.
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Generating "PAR" statistics.
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**************************
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**************************
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Generating Clock Report
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Generating Clock Report
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**************************
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| gclk_BUFGP | BUFGMUX_X1Y11| No | 383 | 0.088 | 0.205 |
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| gclk_BUFGP | BUFGMUX_X1Y11| No | 383 | 0.088 | 0.205 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|diogenes_cpu/pipesta | | | | | |
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|diogenes_cpu/pipesta | | | | | |
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| ge2/big_op<13> | Local| | 8 | 0.329 | 2.290 |
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| ge2/big_op<13> | Local| | 8 | 0.329 | 2.290 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| was_button | Local| | 8 | 0.460 | 2.228 |
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| was_button | Local| | 8 | 0.460 | 2.228 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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the minimum and maximum path delays which includes logic delays.
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The Delay Summary Report
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The Delay Summary Report
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The AVERAGE CONNECTION DELAY for this design is: 1.183
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The AVERAGE CONNECTION DELAY for this design is: 1.183
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The MAXIMUM PIN DELAY IS: 4.331
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The MAXIMUM PIN DELAY IS: 4.331
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.777
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.777
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Listing Pin Delays by value: (nsec)
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Listing Pin Delays by value: (nsec)
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d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
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d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
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--------- --------- --------- --------- --------- ---------
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--------- --------- --------- --------- --------- ---------
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2773 2441 981 64 3 0
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2773 2441 981 64 3 0
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Timing Score: 0
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Timing Score: 0
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Asterisk (*) preceding a constraint indicates it was not met.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIG | SETUP | 0.040ns| 11.960ns| 0| 0
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NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIG | SETUP | 0.040ns| 11.960ns| 0| 0
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H 50% | HOLD | 0.814ns| | 0| 0
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H 50% | HOLD | 0.814ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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All constraints were met.
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Generating Pad Report.
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Generating Pad Report.
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 44 secs
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Total REAL time to PAR completion: 44 secs
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Total CPU time to PAR completion: 44 secs
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Total CPU time to PAR completion: 44 secs
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Peak Memory Usage: 149 MB
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Peak Memory Usage: 149 MB
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Placement: Completed - No errors found.
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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Number of warning messages: 1
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Number of warning messages: 1
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Number of info messages: 0
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Number of info messages: 0
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Writing design to file mysio.ncd
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Writing design to file mysio.ncd
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PAR done!
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PAR done!
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