-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * with the License. You may obtain a copy of the License at
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-- * with the License. You may obtain a copy of the License at
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-- * http://www.mozilla.org/MPL/
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-- * http://www.mozilla.org/MPL/
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-- *
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-- *
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * the specific language governing rights and limitations under the License.
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-- * the specific language governing rights and limitations under the License.
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-- *
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-- *
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-- * The Original Code is BBC Research and Development code.
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-- * The Original Code is BBC Research and Development code.
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-- *
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-- *
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * Corporation.
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-- * Corporation.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * All Rights Reserved.
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-- * All Rights Reserved.
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-- *
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-- *
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-- * Contributor(s): Peter Bleackley (Original author)
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-- * Contributor(s): Peter Bleackley (Original author)
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-- *
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-- *
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * allow use of your version of this file only under the terms of the either
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-- * allow use of your version of this file only under the terms of the either
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * and replace them with the notice and other provisions required by the GPL
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-- * and replace them with the notice and other provisions required by the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity INPUT_CONTROL is
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entity INPUT_CONTROL is
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Port ( ENABLE : in std_logic;
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Port ( ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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BUFFER_CONTROL : in std_logic;
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BUFFER_CONTROL : in std_logic;
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DEMAND : in std_logic;
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DEMAND : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic);
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end INPUT_CONTROL;
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end INPUT_CONTROL;
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architecture RTL of INPUT_CONTROL is
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architecture RTL of INPUT_CONTROL is
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component FIFO
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component FIFO
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port( WRITE_ENABLE : in std_logic;
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port( WRITE_ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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READ_ENABLE : in std_logic;
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READ_ENABLE : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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DATA_OUT : out std_logic;
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DATA_OUT : out std_logic;
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EMPTY : out std_logic);
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EMPTY : out std_logic);
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end component FIFO;
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end component FIFO;
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signal FIFO_WRITE_ENABLE : std_logic;
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signal FIFO_WRITE_ENABLE : std_logic;
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signal FIFO_READ_ENABLE : std_logic;
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signal FIFO_READ_ENABLE : std_logic;
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signal FIFO_DATA_IN : std_logic;
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signal FIFO_DATA_IN : std_logic;
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signal FIFO_DATA_OUT : std_logic;
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signal FIFO_DATA_OUT : std_logic;
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signal FIFO_EMPTY : std_logic;
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signal FIFO_EMPTY : std_logic;
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signal USE_BUFFER : std_logic;
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signal USE_BUFFER : std_logic;
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signal PUT_IN_BUFFER : std_logic;
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signal PUT_IN_BUFFER : std_logic;
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begin
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begin
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STORAGE : FIFO
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STORAGE : FIFO
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port map(WRITE_ENABLE => FIFO_WRITE_ENABLE,
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port map(WRITE_ENABLE => FIFO_WRITE_ENABLE,
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DATA_IN => FIFO_DATA_IN,
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DATA_IN => FIFO_DATA_IN,
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READ_ENABLE => FIFO_READ_ENABLE,
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READ_ENABLE => FIFO_READ_ENABLE,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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DATA_OUT => FIFO_DATA_OUT,
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DATA_OUT => FIFO_DATA_OUT,
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EMPTY => FIFO_EMPTY);
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EMPTY => FIFO_EMPTY);
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FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER;
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FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER;
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FIFO_DATA_IN <= DATA_IN and USE_BUFFER;
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FIFO_DATA_IN <= DATA_IN and USE_BUFFER;
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FIFO_READ_ENABLE <= DEMAND and USE_BUFFER;
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FIFO_READ_ENABLE <= DEMAND and USE_BUFFER;
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PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL;
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PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL;
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USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY;
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USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY;
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OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN)
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OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN)
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begin
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begin
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if USE_BUFFER = '1' then
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if USE_BUFFER = '1' then
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SENDING <= DEMAND;
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SENDING <= DEMAND;
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DATA_OUT <= FIFO_DATA_OUT;
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DATA_OUT <= FIFO_DATA_OUT;
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else
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else
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SENDING <= ENABLE;
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SENDING <= ENABLE;
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DATA_OUT <= DATA_IN;
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DATA_OUT <= DATA_IN;
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end if;
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end if;
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end process OUTPUT_SELECT;
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end process OUTPUT_SELECT;
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end RTL;
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end RTL;
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