-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: ARITHMETICDECODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: ARITHMETICDECODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * with the License. You may obtain a copy of the License at
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-- * with the License. You may obtain a copy of the License at
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-- * http://www.mozilla.org/MPL/
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-- * http://www.mozilla.org/MPL/
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-- *
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-- *
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * the specific language governing rights and limitations under the License.
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-- * the specific language governing rights and limitations under the License.
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-- *
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-- *
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-- * The Original Code is BBC Research and Development code.
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-- * The Original Code is BBC Research and Development code.
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-- *
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-- *
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * Corporation.
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-- * Corporation.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * All Rights Reserved.
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-- * All Rights Reserved.
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-- *
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-- *
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-- * Contributor(s): Peter Bleackley (Original author)
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-- * Contributor(s): Peter Bleackley (Original author)
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-- *
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-- *
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * allow use of your version of this file only under the terms of the either
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-- * allow use of your version of this file only under the terms of the either
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * and replace them with the notice and other provisions required by the GPL
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-- * and replace them with the notice and other provisions required by the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity ARITHMETICDECODER is
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entity ARITHMETICDECODER is
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generic (PROB : std_logic_vector (9 downto 0) := "1010101010");
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generic (PROB : std_logic_vector (9 downto 0) := "1010101010");
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Port ( ENABLE : in std_logic;
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Port ( ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic);
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end ARITHMETICDECODER;
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end ARITHMETICDECODER;
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architecture RTL of ARITHMETICDECODER is
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architecture RTL of ARITHMETICDECODER is
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component INPUT_CONTROL
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component INPUT_CONTROL
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port( ENABLE : in std_logic;
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port( ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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BUFFER_CONTROL : in std_logic;
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BUFFER_CONTROL : in std_logic;
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DEMAND : in std_logic;
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DEMAND : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic);
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end component INPUT_CONTROL;
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end component INPUT_CONTROL;
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component STORAGE_REGISTER
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component STORAGE_REGISTER
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Port ( LOAD : in std_logic_vector(15 downto 0);
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Port ( LOAD : in std_logic_vector(15 downto 0);
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SHIFT_IN : in std_logic;
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SHIFT_IN : in std_logic;
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SET_VALUE : in std_logic;
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SET_VALUE : in std_logic;
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SHIFT_ALL : in std_logic;
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SHIFT_ALL : in std_logic;
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SHIFT_MOST : in std_logic;
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SHIFT_MOST : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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OUTPUT : out std_logic_vector(15 downto 0));
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OUTPUT : out std_logic_vector(15 downto 0));
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end component STORAGE_REGISTER;
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end component STORAGE_REGISTER;
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component CONVERGENCE_CHECK
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component CONVERGENCE_CHECK
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port ( HIGH_MSB : in std_logic;
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port ( HIGH_MSB : in std_logic;
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LOW_MSB : in std_logic;
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LOW_MSB : in std_logic;
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HIGH_SECONDBIT : in std_logic;
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HIGH_SECONDBIT : in std_logic;
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LOW_SECONDBIT : in std_logic;
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LOW_SECONDBIT : in std_logic;
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CHECK : in std_logic;
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CHECK : in std_logic;
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TRIGGER_OUTPUT : out std_logic;
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TRIGGER_OUTPUT : out std_logic;
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TRIGGER_FOLLOW : out std_logic);
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TRIGGER_FOLLOW : out std_logic);
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end component CONVERGENCE_CHECK;
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end component CONVERGENCE_CHECK;
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component ARITHMETIC_UNIT
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component ARITHMETIC_UNIT
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port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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PROB : in std_logic_vector(9 downto 0);
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PROB : in std_logic_vector(9 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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ENABLE : in std_logic;
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ENABLE : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
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RESULT_OUT0 : out std_logic_vector(15 downto 0);
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RESULT_OUT0 : out std_logic_vector(15 downto 0);
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RESULT_OUT1 : out std_logic_vector(15 downto 0);
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RESULT_OUT1 : out std_logic_vector(15 downto 0);
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DATA_LOAD : out std_logic);
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DATA_LOAD : out std_logic);
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end component ARITHMETIC_UNIT;
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end component ARITHMETIC_UNIT;
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component SYMBOL_DETECTOR
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component SYMBOL_DETECTOR
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port ( ENABLE : in std_logic;
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port ( ENABLE : in std_logic;
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DATA_IN : in std_logic_vector (15 downto 0);
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DATA_IN : in std_logic_vector (15 downto 0);
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THRESHOLD : in std_logic_vector (15 downto 0);
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THRESHOLD : in std_logic_vector (15 downto 0);
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic);
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end component SYMBOL_DETECTOR;
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end component SYMBOL_DETECTOR;
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signal HIGH_SET : std_logic;
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signal HIGH_SET : std_logic;
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signal LOW_SET : std_logic;
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signal LOW_SET : std_logic;
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signal SHIFT_ALL : std_logic;
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signal SHIFT_ALL : std_logic;
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signal DIFFERENCE_SHIFT_ALL : std_logic;
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signal DIFFERENCE_SHIFT_ALL : std_logic;
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signal SHIFT_MOST : std_logic;
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signal SHIFT_MOST : std_logic;
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signal ZERO_OUTPUT : std_logic;
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signal ZERO_OUTPUT : std_logic;
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signal ARITHMETIC_UNIT_ENABLE : std_logic;
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signal ARITHMETIC_UNIT_ENABLE : std_logic;
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signal CONVERGENCE_TEST : std_logic;
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signal CONVERGENCE_TEST : std_logic;
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signal TRIGGER_INPUT : std_logic;
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signal TRIGGER_INPUT : std_logic;
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signal TRIGGER_FOLLOW: std_logic;
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signal TRIGGER_FOLLOW: std_logic;
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signal DATA_LOAD: std_logic;
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signal DATA_LOAD: std_logic;
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signal GET_DATA : std_logic;
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signal GET_DATA : std_logic;
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signal DATA_AVAILABLE : std_logic;
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signal DATA_AVAILABLE : std_logic;
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signal BUFFERED_DATA : std_logic;
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signal BUFFERED_DATA : std_logic;
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signal SYMBOL : std_logic;
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signal SYMBOL : std_logic;
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signal HOLD : std_logic;
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signal HOLD : std_logic;
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signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
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signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector(15 downto 0);
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector(15 downto 0);
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
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signal DIFFERENCE_VALUE : std_logic_vector (15 downto 0);
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signal DIFFERENCE_VALUE : std_logic_vector (15 downto 0);
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signal HIGH_VALUE : std_logic_vector (15 downto 0);
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signal HIGH_VALUE : std_logic_vector (15 downto 0);
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signal LOW_VALUE : std_logic_vector (15 downto 0);
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signal LOW_VALUE : std_logic_vector (15 downto 0);
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signal CURRENT_VALUE : std_logic_vector (15 downto 0);
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signal CURRENT_VALUE : std_logic_vector (15 downto 0);
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begin
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begin
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-- input buffering
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-- input buffering
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INBUFFER: INPUT_CONTROL
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INBUFFER: INPUT_CONTROL
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port map(ENABLE => ENABLE,
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port map(ENABLE => ENABLE,
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DATA_IN => DATA_IN,
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DATA_IN => DATA_IN,
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BUFFER_CONTROL => HOLD,
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BUFFER_CONTROL => HOLD,
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DEMAND => GET_DATA,
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DEMAND => GET_DATA,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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SENDING => DATA_AVAILABLE,
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SENDING => DATA_AVAILABLE,
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DATA_OUT => BUFFERED_DATA);
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DATA_OUT => BUFFERED_DATA);
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-- Specify the registers
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-- Specify the registers
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HIGH: STORAGE_REGISTER
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HIGH: STORAGE_REGISTER
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
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SHIFT_IN => '1',
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SHIFT_IN => '1',
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SET_VALUE => HIGH_SET,
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SET_VALUE => HIGH_SET,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_MOST => SHIFT_MOST,
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SHIFT_MOST => SHIFT_MOST,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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OUTPUT => HIGH_VALUE);
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OUTPUT => HIGH_VALUE);
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LOW: STORAGE_REGISTER
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LOW: STORAGE_REGISTER
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
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SHIFT_IN => '0',
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SHIFT_IN => '0',
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SET_VALUE => LOW_SET,
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SET_VALUE => LOW_SET,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_MOST => SHIFT_MOST,
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SHIFT_MOST => SHIFT_MOST,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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OUTPUT => LOW_VALUE);
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OUTPUT => LOW_VALUE);
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DIFFERENCE: STORAGE_REGISTER
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DIFFERENCE: STORAGE_REGISTER
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port map( LOAD => DIFFERENCE_IN,
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port map( LOAD => DIFFERENCE_IN,
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SHIFT_IN => '1',
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SHIFT_IN => '1',
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SET_VALUE => DATA_LOAD,
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SET_VALUE => DATA_LOAD,
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SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
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SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
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SHIFT_MOST => '0',
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SHIFT_MOST => '0',
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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OUTPUT => DIFFERENCE_VALUE);
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OUTPUT => DIFFERENCE_VALUE);
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CURRENT: STORAGE_REGISTER
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CURRENT: STORAGE_REGISTER
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port map( LOAD => "0000000000000000",
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port map( LOAD => "0000000000000000",
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SHIFT_IN => BUFFERED_DATA,
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SHIFT_IN => BUFFERED_DATA,
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SET_VALUE => '0',
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SET_VALUE => '0',
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_MOST => SHIFT_MOST,
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SHIFT_MOST => SHIFT_MOST,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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OUTPUT => CURRENT_VALUE);
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OUTPUT => CURRENT_VALUE);
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-- The arithmetic
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-- The arithmetic
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ARITH: ARITHMETIC_UNIT
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ARITH: ARITHMETIC_UNIT
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port map(DIFFERENCE => DIFFERENCE_VALUE,
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port map(DIFFERENCE => DIFFERENCE_VALUE,
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PROB => PROB,
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PROB => PROB,
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LOW => LOW_VALUE,
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LOW => LOW_VALUE,
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ENABLE => ARITHMETIC_UNIT_ENABLE,
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ENABLE => ARITHMETIC_UNIT_ENABLE,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
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DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
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DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
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DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
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RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
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RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
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RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
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RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
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DATA_LOAD => DATA_LOAD);
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DATA_LOAD => DATA_LOAD);
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--The convergence checks
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--The convergence checks
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CONVERGE: CONVERGENCE_CHECK
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CONVERGE: CONVERGENCE_CHECK
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port map(HIGH_MSB => HIGH_VALUE(15),
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port map(HIGH_MSB => HIGH_VALUE(15),
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LOW_MSB => LOW_VALUE(15),
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LOW_MSB => LOW_VALUE(15),
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HIGH_SECONDBIT => HIGH_VALUE(14),
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HIGH_SECONDBIT => HIGH_VALUE(14),
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LOW_SECONDBIT => LOW_VALUE(14),
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LOW_SECONDBIT => LOW_VALUE(14),
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CHECK => CONVERGENCE_TEST,
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CHECK => CONVERGENCE_TEST,
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TRIGGER_OUTPUT => TRIGGER_INPUT,
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TRIGGER_OUTPUT => TRIGGER_INPUT,
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TRIGGER_FOLLOW => TRIGGER_FOLLOW);
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TRIGGER_FOLLOW => TRIGGER_FOLLOW);
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--The output unit
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--The output unit
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OUTPUT: SYMBOL_DETECTOR
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OUTPUT: SYMBOL_DETECTOR
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port map(ENABLE => DATA_LOAD,
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port map(ENABLE => DATA_LOAD,
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DATA_IN => CURRENT_VALUE,
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DATA_IN => CURRENT_VALUE,
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THRESHOLD => ARITHMETIC_UNIT_RESULT_OUT1,
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THRESHOLD => ARITHMETIC_UNIT_RESULT_OUT1,
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DATA_OUT => SYMBOL);
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DATA_OUT => SYMBOL);
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SENDING <= DATA_LOAD;
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SENDING <= DATA_LOAD;
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DATA_OUT <= SYMBOL;
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DATA_OUT <= SYMBOL;
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-- Input logic
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-- Input logic
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HIGH_SET <= ZERO_OUTPUT and DATA_LOAD;
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HIGH_SET <= ZERO_OUTPUT and DATA_LOAD;
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ZERO_OUTPUT <= not SYMBOL;
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ZERO_OUTPUT <= not SYMBOL;
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LOW_SET <= SYMBOL and DATA_LOAD;
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LOW_SET <= SYMBOL and DATA_LOAD;
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GET_DATA <= TRIGGER_INPUT or TRIGGER_FOLLOW;
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GET_DATA <= TRIGGER_INPUT or TRIGGER_FOLLOW;
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HOLD <= DATA_LOAD or not GET_DATA;
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HOLD <= DATA_LOAD or not GET_DATA;
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-- Control logic for DIFFERENCE register
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-- Control logic for DIFFERENCE register
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DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
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DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
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-- Control logic for convergence check
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-- Control logic for convergence check
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-- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD or RESET;
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-- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD or RESET;
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-- CONVERGENCE_TEST_DELAY: D_TYPE
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-- CONVERGENCE_TEST_DELAY: D_TYPE
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-- port map( D => CHECK,
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-- port map( D => CHECK,
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-- CLOCK => CLOCK,
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-- CLOCK => CLOCK,
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-- Q => CONVERGENCE_TEST);
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-- Q => CONVERGENCE_TEST);
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CONVERGENCE_TEST <= not DATA_LOAD;
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CONVERGENCE_TEST <= not DATA_LOAD;
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-- Control logic for arithmetic unit
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-- Control logic for arithmetic unit
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ARITHMETIC_UNIT_ENABLE <= GET_DATA nor DATA_LOAD;
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ARITHMETIC_UNIT_ENABLE <= GET_DATA nor DATA_LOAD;
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-- Control Logic for input control
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-- Control Logic for input control
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SHIFT_ALL <= TRIGGER_INPUT and DATA_AVAILABLE;
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SHIFT_ALL <= TRIGGER_INPUT and DATA_AVAILABLE;
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SHIFT_MOST <= TRIGGER_FOLLOW and DATA_AVAILABLE;
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SHIFT_MOST <= TRIGGER_FOLLOW and DATA_AVAILABLE;
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--Select new difference value
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--Select new difference value
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NEWDIFF : process(SYMBOL,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
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NEWDIFF : process(SYMBOL,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
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begin
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begin
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if(SYMBOL = '1') then
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if(SYMBOL = '1') then
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DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
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DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
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else
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else
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DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
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DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
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end if;
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end if;
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end process NEWDIFF;
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end process NEWDIFF;
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end RTL;
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end RTL;
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