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-- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005
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-- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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use IEEE.std_logic_textio.all;
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use IEEE.std_logic_textio.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use STD.textio.all;
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use STD.textio.all;
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ENTITY arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
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ENTITY arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
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END arithmeticcoder_ArithmeticCoderTestbench_vhd_tb;
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END arithmeticcoder_ArithmeticCoderTestbench_vhd_tb;
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ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
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ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
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COMPONENT arithmeticcoder
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COMPONENT arithmeticcoder
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generic(
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generic(
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PROB : std_logic_vector (9 downto 0));
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PROB : std_logic_vector (9 downto 0));
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PORT(
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PORT(
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ENABLE : IN std_logic;
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ENABLE : IN std_logic;
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DATA_IN : IN std_logic;
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DATA_IN : IN std_logic;
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CONTEXT_ENABLE : in std_logic;
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CONTEXT_ENABLE : in std_logic;
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CONTEXT_IN : in std_logic_vector (5 downto 0);
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CONTEXT_IN : in std_logic_vector (5 downto 0);
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RESET : IN std_logic;
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RESET : IN std_logic;
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CLOCK : IN std_logic;
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CLOCK : IN std_logic;
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SENDING : OUT std_logic;
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SENDING : OUT std_logic;
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DATA_OUT : OUT std_logic
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DATA_OUT : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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component ARITHMETICDECODER
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component ARITHMETICDECODER
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generic(
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generic(
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PROB : std_logic_vector (9 downto 0));
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PROB : std_logic_vector (9 downto 0));
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port (ENABLE : in std_logic;
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port (ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic);
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end component ARITHMETICDECODER;
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end component ARITHMETICDECODER;
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SIGNAL ENABLE : std_logic;
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SIGNAL ENABLE : std_logic;
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SIGNAL DATA_IN : std_logic := '0';
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SIGNAL DATA_IN : std_logic := '0';
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SIGNAL RESET : std_logic;
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SIGNAL RESET : std_logic;
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SIGNAL CLOCK : std_logic := '0';
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SIGNAL CLOCK : std_logic := '0';
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SIGNAL SENDING : std_logic;
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SIGNAL SENDING : std_logic;
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SIGNAL DATA_OUT : std_logic;
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SIGNAL DATA_OUT : std_logic;
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signal TRANSMIT : std_logic;
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signal TRANSMIT : std_logic;
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signal DATA_TRANSFER : std_logic;
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signal DATA_TRANSFER : std_logic;
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constant PERIOD : time := 10 ns;
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constant PERIOD : time := 10 ns;
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signal CONTEXT_ENABLE : std_logic;
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signal CONTEXT_ENABLE : std_logic;
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signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
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signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
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file TESTDATA : text is in "";
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file TESTDATA : text is in "";
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file RESULTS : text is out "results";
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file RESULTS : text is out "results";
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BEGIN
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BEGIN
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uut: arithmeticcoder
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uut: arithmeticcoder
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generic map(
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generic map(
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PROB => "1110010000")
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PROB => "1110010000")
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PORT MAP(
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PORT MAP(
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ENABLE => ENABLE,
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ENABLE => ENABLE,
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DATA_IN => DATA_IN,
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DATA_IN => DATA_IN,
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CONTEXT_ENABLE => CONTEXT_ENABLE,
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CONTEXT_ENABLE => CONTEXT_ENABLE,
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CONTEXT_IN => CONTEXT,
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CONTEXT_IN => CONTEXT,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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SENDING => TRANSMIT,
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SENDING => TRANSMIT,
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DATA_OUT => DATA_TRANSFER
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DATA_OUT => DATA_TRANSFER
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);
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);
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CLOCK <= not CLOCK after PERIOD/2;
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CLOCK <= not CLOCK after PERIOD/2;
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DECODER: ARITHMETICDECODER
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DECODER: ARITHMETICDECODER
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generic map(
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generic map(
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PROB => "1110010000")
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PROB => "1110010000")
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port map( ENABLE => TRANSMIT,
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port map( ENABLE => TRANSMIT,
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DATA_IN => DATA_TRANSFER,
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DATA_IN => DATA_TRANSFER,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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SENDING => SENDING,
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SENDING => SENDING,
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DATA_OUT => DATA_OUT);
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DATA_OUT => DATA_OUT);
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--*** Test Bench - User Defined Section ***
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--*** Test Bench - User Defined Section ***
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tb : PROCESS
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tb : PROCESS
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variable GETLINE : line;
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variable GETLINE : line;
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variable INDATA : std_logic;
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variable INDATA : std_logic;
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BEGIN
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BEGIN
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for COUNT in 0 to 4194307 loop
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for COUNT in 0 to 4194307 loop
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wait until CLOCK'event and CLOCK = '1';
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wait until CLOCK'event and CLOCK = '1';
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if COUNT = 0 then
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if COUNT = 0 then
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RESET <= '1';
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RESET <= '1';
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ENABLE <= '0';
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ENABLE <= '0';
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DATA_IN <= '0';
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DATA_IN <= '0';
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elsif COUNT = 1 then
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elsif COUNT = 1 then
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RESET <= '0';
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RESET <= '0';
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elsif (COUNT - 2) mod 4 = 0 then
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elsif (COUNT - 2) mod 4 = 0 then
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if (COUNT < 4194307) then
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if (COUNT < 4194307) then
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if (COUNT - 2) mod 128 = 0 then
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if (COUNT - 2) mod 128 = 0 then
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readline(TESTDATA,GETLINE);
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readline(TESTDATA,GETLINE);
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end if;
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end if;
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read(GETLINE,INDATA);
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read(GETLINE,INDATA);
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DATA_IN <= INDATA;
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DATA_IN <= INDATA;
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ENABLE <= '1';
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ENABLE <= '1';
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else
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else
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DATA_IN <= '1';
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DATA_IN <= '1';
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ENABLE <= '1';
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ENABLE <= '1';
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end if;
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end if;
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elsif COUNT < 4194307 then
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elsif COUNT < 4194307 then
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ENABLE <= '0';
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ENABLE <= '0';
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else
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else
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wait; -- will wait forever
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wait; -- will wait forever
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end if;
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end if;
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end loop;
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end loop;
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END PROCESS;
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END PROCESS;
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OUTPUT : process
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OUTPUT : process
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variable OUTLINE : line;
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variable OUTLINE : line;
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begin
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begin
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for WRITTEN in 0 to 1048576 loop
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for WRITTEN in 0 to 1048576 loop
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wait until CLOCK'event and CLOCK = '1' and SENDING = '1';
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wait until CLOCK'event and CLOCK = '1' and SENDING = '1';
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if WRITTEN = 1048576 then
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if WRITTEN = 1048576 then
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report "Process Complete" severity failure;
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report "Process Complete" severity failure;
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wait;
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wait;
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else
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else
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write(OUTLINE,DATA_OUT);
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write(OUTLINE,DATA_OUT);
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if (WRITTEN mod 32) = 31 then
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if (WRITTEN mod 32) = 31 then
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writeline(RESULTS,OUTLINE);
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writeline(RESULTS,OUTLINE);
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end if;
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end if;
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end loop;
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end loop;
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end process;
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end process;
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-- *** End Test Bench - User Defined Section ***
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-- *** End Test Bench - User Defined Section ***
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COUNT_BITS: process (CLOCK, TRANSMIT)
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COUNT_BITS: process (CLOCK, TRANSMIT)
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variable BITS_SENT : integer range 0 to 1048576 := 0;
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variable BITS_SENT : integer range 0 to 1048576 := 0;
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begin
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begin
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if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then
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if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then
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BITS_SENT := BITS_SENT+1;
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BITS_SENT := BITS_SENT+1;
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end if;
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end if;
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end process;
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end process;
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END;
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END;
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