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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:00 2011
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//-- Invoked Fri Mar 25 23:33:00 2011
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//--
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//--
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//-- Source file: dma_core_channels_mux.v
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//-- Source file: dma_core_channels_mux.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_ahb64_core0_channels_mux(ch_fifo_rd_valid,fifo_rd_valid,ch_fifo_rdata,fifo_rdata,ch_periph_rx_clr,periph_rx_clr,ch_periph_tx_clr,periph_tx_clr,ch_rd_page_cross,ch_wr_page_cross,rd_page_cross,wr_page_cross,timeout_aw,timeout_w,timeout_ar,timeout_num_aw,timeout_num_w,timeout_num_ar,wdt_timeout,wdt_ch_num,ch_timeout_aw,ch_timeout_w,ch_timeout_ar,ch_wdt_timeout,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,ch_joint_in_prog,ch_joint_not_in_prog,ch_joint_mux_in_prog,wr_cmd_pending,ch_wr_cmd_pending,rd_ch_num,rd_cmd_num,load_req_in_prog,rd_line_cmd,rd_go_next_line,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_cmd_port,rd_periph_delay,rd_clr_valid,rd_cmd_split,rd_cmd_line,rd_clr_stall,ch_load_req_in_prog,ch_rd_line_cmd,ch_rd_go_next_line,ch_rd_burst_start,ch_rd_burst_addr,ch_rd_burst_size,ch_rd_tokens,ch_rd_port_num,ch_rd_periph_delay,ch_rd_clr_valid,ch_rd_cmd_split,ch_rd_cmd_line,ch_rd_clr_stall,load_wr_num,load_wr,ch_load_wr,ch_fifo_wr_num,rd_transfer_num,rd_clr_line_num,rd_transfer,rd_clr_line,fifo_wr,ch_rd_transfer,ch_rd_clr_line,ch_fifo_wr,rd_ch_num_resp,rd_slverr,rd_decerr,rd_clr,rd_clr_load,ch_rd_slverr,ch_rd_decerr,ch_rd_clr,ch_rd_clr_load,wr_ch_num,wr_cmd_num,wr_last_cmd,wr_line_cmd,wr_go_next_line,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_cmd_port,wr_periph_delay,wr_clr_valid,wr_cmd_split,wr_clr_stall,ch_wr_last_cmd,ch_wr_line_cmd,ch_wr_go_next_line,ch_wr_burst_start,ch_wr_burst_addr,ch_wr_burst_size,ch_wr_tokens,ch_wr_port_num,ch_wr_periph_delay,ch_wr_clr_valid,ch_wr_cmd_split,ch_wr_clr_stall,ch_fifo_rd_num,wr_transfer_num,wr_clr_line_num,wr_transfer,wr_clr_line,fifo_rd,ch_fifo_wr_ready,ch_wr_transfer,ch_wr_clr_line,ch_fifo_rd,fifo_wr_ready,wr_ch_num_resp,wr_slverr,wr_decerr,wr_clr,wr_clr_last,ch_wr_slverr,ch_wr_decerr,ch_wr_clr_last,ch_wr_clr);
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module dma_ahb64_core0_channels_mux(ch_fifo_rd_valid,fifo_rd_valid,ch_fifo_rdata,fifo_rdata,ch_periph_rx_clr,periph_rx_clr,ch_periph_tx_clr,periph_tx_clr,ch_rd_page_cross,ch_wr_page_cross,rd_page_cross,wr_page_cross,timeout_aw,timeout_w,timeout_ar,timeout_num_aw,timeout_num_w,timeout_num_ar,wdt_timeout,wdt_ch_num,ch_timeout_aw,ch_timeout_w,ch_timeout_ar,ch_wdt_timeout,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,ch_joint_in_prog,ch_joint_not_in_prog,ch_joint_mux_in_prog,wr_cmd_pending,ch_wr_cmd_pending,rd_ch_num,rd_cmd_num,load_req_in_prog,rd_line_cmd,rd_go_next_line,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_cmd_port,rd_periph_delay,rd_clr_valid,rd_cmd_split,rd_cmd_line,rd_clr_stall,ch_load_req_in_prog,ch_rd_line_cmd,ch_rd_go_next_line,ch_rd_burst_start,ch_rd_burst_addr,ch_rd_burst_size,ch_rd_tokens,ch_rd_port_num,ch_rd_periph_delay,ch_rd_clr_valid,ch_rd_cmd_split,ch_rd_cmd_line,ch_rd_clr_stall,load_wr_num,load_wr,ch_load_wr,ch_fifo_wr_num,rd_transfer_num,rd_clr_line_num,rd_transfer,rd_clr_line,fifo_wr,ch_rd_transfer,ch_rd_clr_line,ch_fifo_wr,rd_ch_num_resp,rd_slverr,rd_decerr,rd_clr,rd_clr_load,ch_rd_slverr,ch_rd_decerr,ch_rd_clr,ch_rd_clr_load,wr_ch_num,wr_cmd_num,wr_last_cmd,wr_line_cmd,wr_go_next_line,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_cmd_port,wr_periph_delay,wr_clr_valid,wr_cmd_split,wr_clr_stall,ch_wr_last_cmd,ch_wr_line_cmd,ch_wr_go_next_line,ch_wr_burst_start,ch_wr_burst_addr,ch_wr_burst_size,ch_wr_tokens,ch_wr_port_num,ch_wr_periph_delay,ch_wr_clr_valid,ch_wr_cmd_split,ch_wr_clr_stall,ch_fifo_rd_num,wr_transfer_num,wr_clr_line_num,wr_transfer,wr_clr_line,fifo_rd,ch_fifo_wr_ready,ch_wr_transfer,ch_wr_clr_line,ch_fifo_rd,fifo_wr_ready,wr_ch_num_resp,wr_slverr,wr_decerr,wr_clr,wr_clr_last,ch_wr_slverr,ch_wr_decerr,ch_wr_clr_last,ch_wr_clr);
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//data
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//data
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input [7:0] ch_fifo_rd_valid;
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input [7:0] ch_fifo_rd_valid;
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output fifo_rd_valid;
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output fifo_rd_valid;
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input [8*64-1:0] ch_fifo_rdata;
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input [8*64-1:0] ch_fifo_rdata;
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output [64-1:0] fifo_rdata;
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output [64-1:0] fifo_rdata;
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//periph
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//periph
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input [8*31-1:0] ch_periph_rx_clr;
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input [8*31-1:0] ch_periph_rx_clr;
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output [30:0] periph_rx_clr;
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output [30:0] periph_rx_clr;
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input [8*31-1:0] ch_periph_tx_clr;
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input [8*31-1:0] ch_periph_tx_clr;
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output [30:0] periph_tx_clr;
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output [30:0] periph_tx_clr;
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output [7:0] ch_rd_page_cross;
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output [7:0] ch_rd_page_cross;
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output [7:0] ch_wr_page_cross;
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output [7:0] ch_wr_page_cross;
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input rd_page_cross;
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input rd_page_cross;
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input wr_page_cross;
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input wr_page_cross;
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//axim timeout
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//axim timeout
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input timeout_aw;
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input timeout_aw;
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input timeout_w;
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input timeout_w;
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input timeout_ar;
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input timeout_ar;
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input [2:0] timeout_num_aw;
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input [2:0] timeout_num_aw;
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input [2:0] timeout_num_w;
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input [2:0] timeout_num_w;
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input [2:0] timeout_num_ar;
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input [2:0] timeout_num_ar;
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input wdt_timeout;
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input wdt_timeout;
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input [2:0] wdt_ch_num;
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input [2:0] wdt_ch_num;
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output [7:0] ch_timeout_aw;
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output [7:0] ch_timeout_aw;
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output [7:0] ch_timeout_w;
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output [7:0] ch_timeout_w;
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output [7:0] ch_timeout_ar;
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output [7:0] ch_timeout_ar;
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output [7:0] ch_wdt_timeout;
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output [7:0] ch_wdt_timeout;
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output joint_in_prog;
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output joint_in_prog;
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output joint_not_in_prog;
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output joint_not_in_prog;
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output joint_mux_in_prog;
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output joint_mux_in_prog;
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input [7:0] ch_joint_in_prog;
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input [7:0] ch_joint_in_prog;
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input [7:0] ch_joint_not_in_prog;
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input [7:0] ch_joint_not_in_prog;
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input [7:0] ch_joint_mux_in_prog;
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input [7:0] ch_joint_mux_in_prog;
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input wr_cmd_pending;
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input wr_cmd_pending;
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output [7:0] ch_wr_cmd_pending;
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output [7:0] ch_wr_cmd_pending;
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//rd cmd
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//rd cmd
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input [2:0] rd_ch_num;
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input [2:0] rd_ch_num;
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input [2:0] rd_cmd_num;
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input [2:0] rd_cmd_num;
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output load_req_in_prog;
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output load_req_in_prog;
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output rd_line_cmd;
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output rd_line_cmd;
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output rd_go_next_line;
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output rd_go_next_line;
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input rd_burst_start;
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input rd_burst_start;
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output [32-1:0] rd_burst_addr;
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output [32-1:0] rd_burst_addr;
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output [8-1:0] rd_burst_size;
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output [8-1:0] rd_burst_size;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output [`TOKEN_BITS-1:0] rd_tokens;
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output rd_cmd_port;
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output rd_cmd_port;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output [`DELAY_BITS-1:0] rd_periph_delay;
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output rd_clr_valid;
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output rd_clr_valid;
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input rd_cmd_split;
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input rd_cmd_split;
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input rd_cmd_line;
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input rd_cmd_line;
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output rd_clr_stall;
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output rd_clr_stall;
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input [7:0] ch_load_req_in_prog;
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input [7:0] ch_load_req_in_prog;
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input [7:0] ch_rd_line_cmd;
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input [7:0] ch_rd_line_cmd;
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input [7:0] ch_rd_go_next_line;
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input [7:0] ch_rd_go_next_line;
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output [7:0] ch_rd_burst_start;
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output [7:0] ch_rd_burst_start;
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input [8*32-1:0] ch_rd_burst_addr;
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input [8*32-1:0] ch_rd_burst_addr;
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input [8*8-1:0] ch_rd_burst_size;
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input [8*8-1:0] ch_rd_burst_size;
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input [8*`TOKEN_BITS-1:0] ch_rd_tokens;
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input [8*`TOKEN_BITS-1:0] ch_rd_tokens;
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input [7:0] ch_rd_port_num;
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input [7:0] ch_rd_port_num;
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input [8*`DELAY_BITS-1:0] ch_rd_periph_delay;
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input [8*`DELAY_BITS-1:0] ch_rd_periph_delay;
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input [7:0] ch_rd_clr_valid;
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input [7:0] ch_rd_clr_valid;
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output [7:0] ch_rd_cmd_split;
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output [7:0] ch_rd_cmd_split;
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output [7:0] ch_rd_cmd_line;
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output [7:0] ch_rd_cmd_line;
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input [7:0] ch_rd_clr_stall;
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input [7:0] ch_rd_clr_stall;
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//rd data - load cmd
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//rd data - load cmd
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input [2:0] load_wr_num;
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input [2:0] load_wr_num;
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input load_wr;
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input load_wr;
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output [7:0] ch_load_wr;
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output [7:0] ch_load_wr;
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//rd data
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//rd data
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input [2:0] ch_fifo_wr_num;
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input [2:0] ch_fifo_wr_num;
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input [2:0] rd_transfer_num;
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input [2:0] rd_transfer_num;
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input [2:0] rd_clr_line_num;
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input [2:0] rd_clr_line_num;
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input rd_transfer;
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input rd_transfer;
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input rd_clr_line;
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input rd_clr_line;
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input fifo_wr;
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input fifo_wr;
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output [7:0] ch_rd_transfer;
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output [7:0] ch_rd_transfer;
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output [7:0] ch_rd_clr_line;
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output [7:0] ch_rd_clr_line;
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output [7:0] ch_fifo_wr;
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output [7:0] ch_fifo_wr;
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//rd resp
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//rd resp
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input [2:0] rd_ch_num_resp;
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input [2:0] rd_ch_num_resp;
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input rd_slverr;
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input rd_slverr;
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input rd_decerr;
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input rd_decerr;
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input rd_clr;
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input rd_clr;
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input rd_clr_load;
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input rd_clr_load;
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output [7:0] ch_rd_slverr;
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output [7:0] ch_rd_slverr;
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output [7:0] ch_rd_decerr;
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output [7:0] ch_rd_decerr;
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output [7:0] ch_rd_clr;
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output [7:0] ch_rd_clr;
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output [7:0] ch_rd_clr_load;
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output [7:0] ch_rd_clr_load;
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//wr cmd
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//wr cmd
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input [2:0] wr_ch_num;
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input [2:0] wr_ch_num;
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input [2:0] wr_cmd_num;
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input [2:0] wr_cmd_num;
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output wr_last_cmd;
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output wr_last_cmd;
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output wr_line_cmd;
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output wr_line_cmd;
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output wr_go_next_line;
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output wr_go_next_line;
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input wr_burst_start;
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input wr_burst_start;
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output [32-1:0] wr_burst_addr;
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output [32-1:0] wr_burst_addr;
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output [8-1:0] wr_burst_size;
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output [8-1:0] wr_burst_size;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output [`TOKEN_BITS-1:0] wr_tokens;
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output wr_cmd_port;
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output wr_cmd_port;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output [`DELAY_BITS-1:0] wr_periph_delay;
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output wr_clr_valid;
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output wr_clr_valid;
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input wr_cmd_split;
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input wr_cmd_split;
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output wr_clr_stall;
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output wr_clr_stall;
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input [7:0] ch_wr_last_cmd;
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input [7:0] ch_wr_last_cmd;
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input [7:0] ch_wr_line_cmd;
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input [7:0] ch_wr_line_cmd;
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input [7:0] ch_wr_go_next_line;
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input [7:0] ch_wr_go_next_line;
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output [7:0] ch_wr_burst_start;
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output [7:0] ch_wr_burst_start;
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input [8*32-1:0] ch_wr_burst_addr;
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input [8*32-1:0] ch_wr_burst_addr;
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input [8*8-1:0] ch_wr_burst_size;
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input [8*8-1:0] ch_wr_burst_size;
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input [8*`TOKEN_BITS-1:0] ch_wr_tokens;
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input [8*`TOKEN_BITS-1:0] ch_wr_tokens;
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input [7:0] ch_wr_port_num;
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input [7:0] ch_wr_port_num;
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input [8*`DELAY_BITS-1:0] ch_wr_periph_delay;
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input [8*`DELAY_BITS-1:0] ch_wr_periph_delay;
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input [7:0] ch_wr_clr_valid;
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input [7:0] ch_wr_clr_valid;
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output [7:0] ch_wr_cmd_split;
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output [7:0] ch_wr_cmd_split;
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input [7:0] ch_wr_clr_stall;
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input [7:0] ch_wr_clr_stall;
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//wr data
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//wr data
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input [2:0] ch_fifo_rd_num;
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input [2:0] ch_fifo_rd_num;
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input [2:0] wr_transfer_num;
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input [2:0] wr_transfer_num;
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input [2:0] wr_clr_line_num;
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input [2:0] wr_clr_line_num;
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input wr_transfer;
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input wr_transfer;
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input wr_clr_line;
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input wr_clr_line;
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input fifo_rd;
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input fifo_rd;
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input [7:0] ch_fifo_wr_ready;
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input [7:0] ch_fifo_wr_ready;
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output [7:0] ch_wr_transfer;
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output [7:0] ch_wr_transfer;
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output [7:0] ch_wr_clr_line;
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output [7:0] ch_wr_clr_line;
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output [7:0] ch_fifo_rd;
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output [7:0] ch_fifo_rd;
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output fifo_wr_ready;
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output fifo_wr_ready;
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//wr resp
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//wr resp
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input [2:0] wr_ch_num_resp;
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input [2:0] wr_ch_num_resp;
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input wr_slverr;
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input wr_slverr;
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input wr_decerr;
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input wr_decerr;
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input wr_clr;
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input wr_clr;
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input wr_clr_last;
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input wr_clr_last;
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output [7:0] ch_wr_slverr;
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output [7:0] ch_wr_slverr;
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output [7:0] ch_wr_decerr;
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output [7:0] ch_wr_decerr;
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output [7:0] ch_wr_clr_last;
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output [7:0] ch_wr_clr_last;
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output [7:0] ch_wr_clr;
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output [7:0] ch_wr_clr;
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prgen_or8 #(1)
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prgen_or8 #(1)
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mux_2(.ch_x(ch_fifo_rd_valid),
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mux_2(.ch_x(ch_fifo_rd_valid),
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.x(fifo_rd_valid)
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.x(fifo_rd_valid)
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);
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);
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prgen_or8 #(64)
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prgen_or8 #(64)
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mux_3(.ch_x(ch_fifo_rdata),
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mux_3(.ch_x(ch_fifo_rdata),
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.x(fifo_rdata)
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.x(fifo_rdata)
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);
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);
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prgen_or8 #(31)
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prgen_or8 #(31)
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mux_4(.ch_x(ch_periph_rx_clr),
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mux_4(.ch_x(ch_periph_rx_clr),
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.x(periph_rx_clr)
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.x(periph_rx_clr)
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);
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);
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prgen_or8 #(31)
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prgen_or8 #(31)
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mux_5(.ch_x(ch_periph_tx_clr),
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mux_5(.ch_x(ch_periph_tx_clr),
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.x(periph_tx_clr)
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.x(periph_tx_clr)
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);
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);
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prgen_mux8 #(`DELAY_BITS)
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prgen_mux8 #(`DELAY_BITS)
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mux_30(.sel(rd_ch_num),
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mux_30(.sel(rd_ch_num),
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.ch_x(ch_rd_periph_delay),
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.ch_x(ch_rd_periph_delay),
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.x(rd_periph_delay)
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.x(rd_periph_delay)
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);
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);
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prgen_mux8 #(`DELAY_BITS)
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prgen_mux8 #(`DELAY_BITS)
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mux_51(.sel(wr_ch_num),
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mux_51(.sel(wr_ch_num),
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.ch_x(ch_wr_periph_delay),
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.ch_x(ch_wr_periph_delay),
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.x(wr_periph_delay)
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.x(wr_periph_delay)
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);
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);
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prgen_demux8 #(1)
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prgen_demux8 #(1)
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mux_6(.sel(timeout_num_aw),
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mux_6(.sel(timeout_num_aw),
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.x(timeout_aw),
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.x(timeout_aw),
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.ch_x(ch_timeout_aw)
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.ch_x(ch_timeout_aw)
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);
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);
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prgen_demux8 #(1)
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prgen_demux8 #(1)
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mux_7(.sel(timeout_num_w),
|
mux_7(.sel(timeout_num_w),
|
.x(timeout_w),
|
.x(timeout_w),
|
.ch_x(ch_timeout_w)
|
.ch_x(ch_timeout_w)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_8(.sel(timeout_num_ar),
|
mux_8(.sel(timeout_num_ar),
|
.x(timeout_ar),
|
.x(timeout_ar),
|
.ch_x(ch_timeout_ar)
|
.ch_x(ch_timeout_ar)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_9(.sel(wdt_ch_num),
|
mux_9(.sel(wdt_ch_num),
|
.x(wdt_timeout),
|
.x(wdt_timeout),
|
.ch_x(ch_wdt_timeout)
|
.ch_x(ch_wdt_timeout)
|
);
|
);
|
|
|
prgen_or8 #(1)
|
prgen_or8 #(1)
|
mux_55(.ch_x(ch_joint_in_prog),
|
mux_55(.ch_x(ch_joint_in_prog),
|
.x(joint_in_prog)
|
.x(joint_in_prog)
|
);
|
);
|
|
|
prgen_or8 #(1)
|
prgen_or8 #(1)
|
mux_56(.ch_x(ch_joint_not_in_prog),
|
mux_56(.ch_x(ch_joint_not_in_prog),
|
.x(joint_not_in_prog)
|
.x(joint_not_in_prog)
|
);
|
);
|
|
|
prgen_or8 #(1)
|
prgen_or8 #(1)
|
mux_57(.ch_x(ch_joint_mux_in_prog),
|
mux_57(.ch_x(ch_joint_mux_in_prog),
|
.x(joint_mux_in_prog)
|
.x(joint_mux_in_prog)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_60(.sel(wr_ch_num),
|
mux_60(.sel(wr_ch_num),
|
.x(wr_cmd_pending),
|
.x(wr_cmd_pending),
|
.ch_x(ch_wr_cmd_pending)
|
.ch_x(ch_wr_cmd_pending)
|
);
|
);
|
|
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_11(.sel(rd_ch_num),
|
mux_11(.sel(rd_ch_num),
|
.x(rd_burst_start),
|
.x(rd_burst_start),
|
.ch_x(ch_rd_burst_start)
|
.ch_x(ch_rd_burst_start)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_13(.sel(load_wr_num),
|
mux_13(.sel(load_wr_num),
|
.x(load_wr),
|
.x(load_wr),
|
.ch_x(ch_load_wr)
|
.ch_x(ch_load_wr)
|
);
|
);
|
|
|
assign ch_rd_clr_line = 'd0;
|
assign ch_rd_clr_line = 'd0;
|
assign ch_rd_cmd_line = 'd0;
|
assign ch_rd_cmd_line = 'd0;
|
assign rd_line_cmd = 'd0;
|
assign rd_line_cmd = 'd0;
|
assign rd_go_next_line = 'd0;
|
assign rd_go_next_line = 'd0;
|
assign rd_clr_stall = 'd0;
|
assign rd_clr_stall = 'd0;
|
assign wr_clr_stall = 'd0;
|
assign wr_clr_stall = 'd0;
|
assign ch_wr_clr_line = 'd0;
|
assign ch_wr_clr_line = 'd0;
|
assign wr_line_cmd = 'd0;
|
assign wr_line_cmd = 'd0;
|
assign wr_go_next_line = 'd0;
|
assign wr_go_next_line = 'd0;
|
|
|
prgen_mux8 #(1)
|
prgen_mux8 #(1)
|
mux_33(.sel(rd_ch_num),
|
mux_33(.sel(rd_ch_num),
|
.ch_x(ch_rd_clr_valid),
|
.ch_x(ch_rd_clr_valid),
|
.x(rd_clr_valid)
|
.x(rd_clr_valid)
|
);
|
);
|
|
|
prgen_mux8 #(1)
|
prgen_mux8 #(1)
|
mux_53(.sel(wr_ch_num),
|
mux_53(.sel(wr_ch_num),
|
.ch_x(ch_wr_clr_valid),
|
.ch_x(ch_wr_clr_valid),
|
.x(wr_clr_valid)
|
.x(wr_clr_valid)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_15(.sel(rd_transfer_num),
|
mux_15(.sel(rd_transfer_num),
|
.x(rd_transfer),
|
.x(rd_transfer),
|
.ch_x(ch_rd_transfer)
|
.ch_x(ch_rd_transfer)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_16(.sel(rd_ch_num_resp),
|
mux_16(.sel(rd_ch_num_resp),
|
.x(rd_slverr),
|
.x(rd_slverr),
|
.ch_x(ch_rd_slverr)
|
.ch_x(ch_rd_slverr)
|
);
|
);
|
|
|
assign ch_rd_decerr = 'd0;
|
assign ch_rd_decerr = 'd0;
|
assign ch_wr_decerr = 'd0;
|
assign ch_wr_decerr = 'd0;
|
assign ch_rd_cmd_split = 'd0;
|
assign ch_rd_cmd_split = 'd0;
|
assign ch_wr_cmd_split = 'd0;
|
assign ch_wr_cmd_split = 'd0;
|
assign ch_rd_page_cross = 'd0;
|
assign ch_rd_page_cross = 'd0;
|
assign ch_wr_page_cross = 'd0;
|
assign ch_wr_page_cross = 'd0;
|
|
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_18(.sel(rd_ch_num_resp),
|
mux_18(.sel(rd_ch_num_resp),
|
.x(rd_clr),
|
.x(rd_clr),
|
.ch_x(ch_rd_clr)
|
.ch_x(ch_rd_clr)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_19(.sel(rd_ch_num_resp),
|
mux_19(.sel(rd_ch_num_resp),
|
.x(rd_clr_load),
|
.x(rd_clr_load),
|
.ch_x(ch_rd_clr_load)
|
.ch_x(ch_rd_clr_load)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_21(.sel(ch_fifo_rd_num),
|
mux_21(.sel(ch_fifo_rd_num),
|
.x(fifo_rd),
|
.x(fifo_rd),
|
.ch_x(ch_fifo_rd)
|
.ch_x(ch_fifo_rd)
|
);
|
);
|
|
|
prgen_mux8 #(1)
|
prgen_mux8 #(1)
|
mux_23(.sel(rd_ch_num),
|
mux_23(.sel(rd_ch_num),
|
.ch_x(ch_load_req_in_prog),
|
.ch_x(ch_load_req_in_prog),
|
.x(load_req_in_prog)
|
.x(load_req_in_prog)
|
);
|
);
|
|
|
prgen_mux8 #(32)
|
prgen_mux8 #(32)
|
mux_26(.sel(rd_ch_num),
|
mux_26(.sel(rd_ch_num),
|
.ch_x(ch_rd_burst_addr),
|
.ch_x(ch_rd_burst_addr),
|
.x(rd_burst_addr)
|
.x(rd_burst_addr)
|
);
|
);
|
|
|
prgen_mux8 #(8)
|
prgen_mux8 #(8)
|
mux_27(.sel(rd_ch_num),
|
mux_27(.sel(rd_ch_num),
|
.ch_x(ch_rd_burst_size),
|
.ch_x(ch_rd_burst_size),
|
.x(rd_burst_size)
|
.x(rd_burst_size)
|
);
|
);
|
|
|
prgen_mux8 #(`TOKEN_BITS)
|
prgen_mux8 #(`TOKEN_BITS)
|
mux_28(.sel(rd_ch_num),
|
mux_28(.sel(rd_ch_num),
|
.ch_x(ch_rd_tokens),
|
.ch_x(ch_rd_tokens),
|
.x(rd_tokens)
|
.x(rd_tokens)
|
);
|
);
|
|
|
prgen_mux8 #(`TOKEN_BITS)
|
prgen_mux8 #(`TOKEN_BITS)
|
mux_49(.sel(wr_ch_num),
|
mux_49(.sel(wr_ch_num),
|
.ch_x(ch_wr_tokens),
|
.ch_x(ch_wr_tokens),
|
.x(wr_tokens)
|
.x(wr_tokens)
|
);
|
);
|
|
|
assign rd_cmd_port = 'd0;
|
assign rd_cmd_port = 'd0;
|
assign wr_cmd_port = 'd0;
|
assign wr_cmd_port = 'd0;
|
|
|
|
|
prgen_mux8 #(1)
|
prgen_mux8 #(1)
|
mux_31(.sel(ch_fifo_rd_num),
|
mux_31(.sel(ch_fifo_rd_num),
|
.ch_x(ch_fifo_wr_ready),
|
.ch_x(ch_fifo_wr_ready),
|
.x(fifo_wr_ready)
|
.x(fifo_wr_ready)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_34(.sel(wr_ch_num),
|
mux_34(.sel(wr_ch_num),
|
.x(wr_burst_start),
|
.x(wr_burst_start),
|
.ch_x(ch_wr_burst_start)
|
.ch_x(ch_wr_burst_start)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_37(.sel(wr_transfer_num),
|
mux_37(.sel(wr_transfer_num),
|
.x(wr_transfer),
|
.x(wr_transfer),
|
.ch_x(ch_wr_transfer)
|
.ch_x(ch_wr_transfer)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_38(.sel(wr_ch_num_resp),
|
mux_38(.sel(wr_ch_num_resp),
|
.x(wr_slverr),
|
.x(wr_slverr),
|
.ch_x(ch_wr_slverr)
|
.ch_x(ch_wr_slverr)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_40(.sel(wr_ch_num_resp),
|
mux_40(.sel(wr_ch_num_resp),
|
.x(wr_clr),
|
.x(wr_clr),
|
.ch_x(ch_wr_clr)
|
.ch_x(ch_wr_clr)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_41(.sel(wr_ch_num_resp),
|
mux_41(.sel(wr_ch_num_resp),
|
.x(wr_clr_last),
|
.x(wr_clr_last),
|
.ch_x(ch_wr_clr_last)
|
.ch_x(ch_wr_clr_last)
|
);
|
);
|
|
|
prgen_demux8 #(1)
|
prgen_demux8 #(1)
|
mux_43(.sel(ch_fifo_wr_num),
|
mux_43(.sel(ch_fifo_wr_num),
|
.x(fifo_wr),
|
.x(fifo_wr),
|
.ch_x(ch_fifo_wr)
|
.ch_x(ch_fifo_wr)
|
);
|
);
|
|
|
prgen_mux8 #(1)
|
prgen_mux8 #(1)
|
mux_44(.sel(wr_ch_num),
|
mux_44(.sel(wr_ch_num),
|
.ch_x(ch_wr_last_cmd),
|
.ch_x(ch_wr_last_cmd),
|
.x(wr_last_cmd)
|
.x(wr_last_cmd)
|
);
|
);
|
|
|
prgen_mux8 #(32)
|
prgen_mux8 #(32)
|
mux_47(.sel(wr_ch_num),
|
mux_47(.sel(wr_ch_num),
|
.ch_x(ch_wr_burst_addr),
|
.ch_x(ch_wr_burst_addr),
|
.x(wr_burst_addr)
|
.x(wr_burst_addr)
|
);
|
);
|
|
|
prgen_mux8 #(8)
|
prgen_mux8 #(8)
|
mux_48(.sel(wr_ch_num),
|
mux_48(.sel(wr_ch_num),
|
.ch_x(ch_wr_burst_size),
|
.ch_x(ch_wr_burst_size),
|
.x(wr_burst_size)
|
.x(wr_burst_size)
|
);
|
);
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|