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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:02 2011
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//-- Invoked Fri Mar 25 23:33:02 2011
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//--
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//--
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//-- Source file: prgen_swap32.v
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//-- Source file: prgen_swap32.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module prgen_swap32 (end_swap,data_in,data_out,bsel_in,bsel_out);
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module prgen_swap32 (end_swap,data_in,data_out,bsel_in,bsel_out);
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input [1:0] end_swap;
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input [1:0] end_swap;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output [31:0] data_out;
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input [3:0] bsel_in;
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input [3:0] bsel_in;
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output [3:0] bsel_out;
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output [3:0] bsel_out;
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reg [31:0] data_out;
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reg [31:0] data_out;
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reg [3:0] bsel_out;
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reg [3:0] bsel_out;
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always @(/*AUTOSENSE*/data_in or end_swap)
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always @(/*AUTOSENSE*/data_in or end_swap)
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begin
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begin
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case (end_swap[1:0])
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case (end_swap[1:0])
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2'b00 : data_out = data_in;
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2'b00 : data_out = data_in;
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2'b01 : data_out = {data_in[23:16], data_in[31:24], data_in[7:0], data_in[15:8]};
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2'b01 : data_out = {data_in[23:16], data_in[31:24], data_in[7:0], data_in[15:8]};
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2'b10 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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2'b10 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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2'b11 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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2'b11 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]};
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endcase
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endcase
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end
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end
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always @(/*AUTOSENSE*/bsel_in or end_swap)
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always @(/*AUTOSENSE*/bsel_in or end_swap)
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begin
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begin
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case (end_swap[1:0])
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case (end_swap[1:0])
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2'b00 : bsel_out = bsel_in;
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2'b00 : bsel_out = bsel_in;
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2'b01 : bsel_out = {bsel_in[2], bsel_in[3], bsel_in[0], bsel_in[1]};
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2'b01 : bsel_out = {bsel_in[2], bsel_in[3], bsel_in[0], bsel_in[1]};
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2'b10 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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2'b10 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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2'b11 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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2'b11 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]};
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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