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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:50 2011
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//-- Invoked Fri Mar 25 23:34:50 2011
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//--
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//--
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//-- Source file: dma_dual_core.v
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//-- Source file: dma_dual_core.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi32_dual_core(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,rd_port_num0,wr_port_num0,rd_port_num1,wr_port_num1,M0_AWID,M0_AWADDR,M0_AWLEN,M0_AWSIZE,M0_AWVALID,M0_AWREADY,M0_WID,M0_WDATA,M0_WSTRB,M0_WLAST,M0_WVALID,M0_WREADY,M0_BID,M0_BRESP,M0_BVALID,M0_BREADY,M0_ARID,M0_ARADDR,M0_ARLEN,M0_ARSIZE,M0_ARVALID,M0_ARREADY,M0_RID,M0_RDATA,M0_RRESP,M0_RLAST,M0_RVALID,M0_RREADY);
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module dma_axi32_dual_core(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,rd_port_num0,wr_port_num0,rd_port_num1,wr_port_num1,M0_AWID,M0_AWADDR,M0_AWLEN,M0_AWSIZE,M0_AWVALID,M0_AWREADY,M0_WID,M0_WDATA,M0_WSTRB,M0_WLAST,M0_WVALID,M0_WREADY,M0_BID,M0_BRESP,M0_BVALID,M0_BREADY,M0_ARID,M0_ARADDR,M0_ARLEN,M0_ARSIZE,M0_ARVALID,M0_ARREADY,M0_RID,M0_RDATA,M0_RRESP,M0_RLAST,M0_RVALID,M0_RREADY);
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input clk;
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input clk;
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input reset;
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input reset;
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input scan_en;
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input scan_en;
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output idle;
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output idle;
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output [1-1:0] INT;
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output [1-1:0] INT;
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input [31:1] periph_tx_req;
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input [31:1] periph_tx_req;
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output [31:1] periph_tx_clr;
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output [31:1] periph_tx_clr;
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input [31:1] periph_rx_req;
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input [31:1] periph_rx_req;
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output [31:1] periph_rx_clr;
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output [31:1] periph_rx_clr;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [12:0] paddr;
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input [12:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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output pready;
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output pready;
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output rd_port_num0;
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output rd_port_num0;
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output wr_port_num0;
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output wr_port_num0;
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output rd_port_num1;
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output rd_port_num1;
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output wr_port_num1;
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output wr_port_num1;
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output [`ID_BITS-1:0] M0_AWID;
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output [`ID_BITS-1:0] M0_AWID;
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output [32-1:0] M0_AWADDR;
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output [32-1:0] M0_AWADDR;
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output [`LEN_BITS-1:0] M0_AWLEN;
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output [`LEN_BITS-1:0] M0_AWLEN;
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output [`SIZE_BITS-1:0] M0_AWSIZE;
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output [`SIZE_BITS-1:0] M0_AWSIZE;
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output M0_AWVALID;
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output M0_AWVALID;
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input M0_AWREADY;
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input M0_AWREADY;
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output [`ID_BITS-1:0] M0_WID;
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output [`ID_BITS-1:0] M0_WID;
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output [32-1:0] M0_WDATA;
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output [32-1:0] M0_WDATA;
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output [32/8-1:0] M0_WSTRB;
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output [32/8-1:0] M0_WSTRB;
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output M0_WLAST;
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output M0_WLAST;
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output M0_WVALID;
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output M0_WVALID;
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input M0_WREADY;
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input M0_WREADY;
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input [`ID_BITS-1:0] M0_BID;
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input [`ID_BITS-1:0] M0_BID;
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input [1:0] M0_BRESP;
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input [1:0] M0_BRESP;
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input M0_BVALID;
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input M0_BVALID;
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output M0_BREADY;
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output M0_BREADY;
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output [`ID_BITS-1:0] M0_ARID;
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output [`ID_BITS-1:0] M0_ARID;
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output [32-1:0] M0_ARADDR;
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output [32-1:0] M0_ARADDR;
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output [`LEN_BITS-1:0] M0_ARLEN;
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output [`LEN_BITS-1:0] M0_ARLEN;
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output [`SIZE_BITS-1:0] M0_ARSIZE;
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output [`SIZE_BITS-1:0] M0_ARSIZE;
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output M0_ARVALID;
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output M0_ARVALID;
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input M0_ARREADY;
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input M0_ARREADY;
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input [`ID_BITS-1:0] M0_RID;
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input [`ID_BITS-1:0] M0_RID;
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input [32-1:0] M0_RDATA;
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input [32-1:0] M0_RDATA;
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input [1:0] M0_RRESP;
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input [1:0] M0_RRESP;
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input M0_RLAST;
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input M0_RLAST;
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input M0_RVALID;
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input M0_RVALID;
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output M0_RREADY;
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output M0_RREADY;
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wire psel0;
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wire psel0;
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wire [31:0] prdata0;
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wire [31:0] prdata0;
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wire pslverr0;
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wire pslverr0;
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wire psel1;
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wire psel1;
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wire [31:0] prdata1;
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wire [31:0] prdata1;
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wire pslverr1;
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wire pslverr1;
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wire psel_reg;
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wire psel_reg;
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wire [31:0] prdata_reg;
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wire [31:0] prdata_reg;
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wire pslverr_reg;
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wire pslverr_reg;
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wire [8*1-1:0] ch_int_all_proc0;
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wire [8*1-1:0] ch_int_all_proc0;
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//outputs of dma_axi32 reg
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//outputs of dma_axi32 reg
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wire [1-1:0] int_all_proc;
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wire [1-1:0] int_all_proc;
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wire [3:0] core0_clkdiv;
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wire [3:0] core0_clkdiv;
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wire [7:0] core0_ch_start;
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wire [7:0] core0_ch_start;
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wire joint_mode0;
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wire joint_mode0;
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wire joint_remote0;
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wire joint_remote0;
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wire rd_prio_top0;
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wire rd_prio_top0;
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wire rd_prio_high0;
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wire rd_prio_high0;
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wire [2:0] rd_prio_top_num0;
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wire [2:0] rd_prio_top_num0;
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wire [2:0] rd_prio_high_num0;
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wire [2:0] rd_prio_high_num0;
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wire wr_prio_top0;
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wire wr_prio_top0;
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wire wr_prio_high0;
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wire wr_prio_high0;
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wire [2:0] wr_prio_top_num0;
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wire [2:0] wr_prio_top_num0;
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wire [2:0] wr_prio_high_num0;
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wire [2:0] wr_prio_high_num0;
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wire [31:1] periph_rx_req_reg;
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wire [31:1] periph_rx_req_reg;
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wire [31:1] periph_tx_req_reg;
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wire [31:1] periph_tx_req_reg;
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wire [31:1] periph_rx_req0;
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wire [31:1] periph_rx_req0;
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wire [31:1] periph_tx_req0;
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wire [31:1] periph_tx_req0;
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wire [31:1] periph_rx_req1;
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wire [31:1] periph_rx_req1;
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wire [31:1] periph_tx_req1;
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wire [31:1] periph_tx_req1;
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wire [31:1] periph_rx_clr0;
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wire [31:1] periph_rx_clr0;
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wire [31:1] periph_tx_clr0;
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wire [31:1] periph_tx_clr0;
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wire [31:1] periph_rx_clr1;
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wire [31:1] periph_rx_clr1;
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wire [31:1] periph_tx_clr1;
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wire [31:1] periph_tx_clr1;
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wire core0_idle;
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wire core0_idle;
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assign idle = core0_idle;
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assign idle = core0_idle;
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assign INT = int_all_proc;
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assign INT = int_all_proc;
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assign periph_rx_req0 = periph_rx_req | periph_rx_req_reg;
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assign periph_rx_req0 = periph_rx_req | periph_rx_req_reg;
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assign periph_tx_req0 = periph_tx_req | periph_tx_req_reg;
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assign periph_tx_req0 = periph_tx_req | periph_tx_req_reg;
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assign periph_rx_req1 = periph_rx_req0;
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assign periph_rx_req1 = periph_rx_req0;
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assign periph_tx_req1 = periph_tx_req0;
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assign periph_tx_req1 = periph_tx_req0;
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assign periph_rx_clr = periph_rx_clr0 | periph_rx_clr1;
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assign periph_rx_clr = periph_rx_clr0 | periph_rx_clr1;
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assign periph_tx_clr = periph_tx_clr0 | periph_tx_clr1;
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assign periph_tx_clr = periph_tx_clr0 | periph_tx_clr1;
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assign joint_remote0 = joint_mode0 & 0 & 0;
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assign joint_remote0 = joint_mode0 & 0 & 0;
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dma_axi32_apb_mux dma_axi32_apb_mux (
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dma_axi32_apb_mux dma_axi32_apb_mux (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.pclken(pclken),
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.pclken(pclken),
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.psel(psel),
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.psel(psel),
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.penable(penable),
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.penable(penable),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.paddr(paddr[12:11]),
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.paddr(paddr[12:11]),
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.prdata(prdata),
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.prdata(prdata),
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.pslverr(pslverr),
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.pslverr(pslverr),
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.pready(pready),
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.pready(pready),
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.psel0(psel0),
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.psel0(psel0),
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.prdata0(prdata0),
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.prdata0(prdata0),
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.pslverr0(pslverr0),
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.pslverr0(pslverr0),
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.psel1(psel1),
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.psel1(psel1),
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.prdata1(prdata1),
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.prdata1(prdata1),
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.pslverr1(pslverr1),
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.pslverr1(pslverr1),
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.psel_reg(psel_reg),
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.psel_reg(psel_reg),
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.prdata_reg(prdata_reg),
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.prdata_reg(prdata_reg),
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.pslverr_reg(pslverr_reg)
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.pslverr_reg(pslverr_reg)
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);
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);
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dma_axi32_reg dma_axi32_reg (
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dma_axi32_reg dma_axi32_reg (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.pclken(pclken),
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.pclken(pclken),
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.psel(psel_reg),
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.psel(psel_reg),
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.penable(penable),
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.penable(penable),
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.paddr(paddr[7:0]),
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.paddr(paddr[7:0]),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.pwdata(pwdata),
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.pwdata(pwdata),
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.prdata(prdata_reg),
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.prdata(prdata_reg),
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.pslverr(pslverr_reg),
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.pslverr(pslverr_reg),
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.core0_idle(core0_idle),
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.core0_idle(core0_idle),
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.ch_int_all_proc0(ch_int_all_proc0),
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.ch_int_all_proc0(ch_int_all_proc0),
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.int_all_proc(int_all_proc),
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.int_all_proc(int_all_proc),
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.core0_clkdiv(core0_clkdiv),
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.core0_clkdiv(core0_clkdiv),
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.core0_ch_start(core0_ch_start),
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.core0_ch_start(core0_ch_start),
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.joint_mode0(joint_mode0),
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.joint_mode0(joint_mode0),
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.rd_prio_top0(rd_prio_top0),
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.rd_prio_top0(rd_prio_top0),
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.rd_prio_high0(rd_prio_high0),
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.rd_prio_high0(rd_prio_high0),
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.rd_prio_top_num0(rd_prio_top_num0),
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.rd_prio_top_num0(rd_prio_top_num0),
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.rd_prio_high_num0(rd_prio_high_num0),
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.rd_prio_high_num0(rd_prio_high_num0),
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.wr_prio_top0(wr_prio_top0),
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.wr_prio_top0(wr_prio_top0),
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.wr_prio_high0(wr_prio_high0),
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.wr_prio_high0(wr_prio_high0),
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.wr_prio_top_num0(wr_prio_top_num0),
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.wr_prio_top_num0(wr_prio_top_num0),
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.wr_prio_high_num0(wr_prio_high_num0),
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.wr_prio_high_num0(wr_prio_high_num0),
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.periph_rx_req_reg(periph_rx_req_reg),
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.periph_rx_req_reg(periph_rx_req_reg),
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.periph_tx_req_reg(periph_tx_req_reg),
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.periph_tx_req_reg(periph_tx_req_reg),
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.periph_rx_clr(periph_rx_clr),
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.periph_rx_clr(periph_rx_clr),
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.periph_tx_clr(periph_tx_clr)
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.periph_tx_clr(periph_tx_clr)
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);
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);
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dma_axi32_core0_top
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dma_axi32_core0_top
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dma_axi32_core0_top (
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dma_axi32_core0_top (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.scan_en(scan_en),
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.scan_en(scan_en),
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.idle(core0_idle),
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.idle(core0_idle),
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.ch_int_all_proc(ch_int_all_proc0),
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.ch_int_all_proc(ch_int_all_proc0),
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.ch_start(core0_ch_start),
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.ch_start(core0_ch_start),
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.clkdiv(core0_clkdiv),
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.clkdiv(core0_clkdiv),
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.periph_tx_req(periph_tx_req0),
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.periph_tx_req(periph_tx_req0),
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.periph_tx_clr(periph_tx_clr0),
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.periph_tx_clr(periph_tx_clr0),
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.periph_rx_req(periph_rx_req0),
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.periph_rx_req(periph_rx_req0),
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.periph_rx_clr(periph_rx_clr0),
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.periph_rx_clr(periph_rx_clr0),
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.pclken(pclken),
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.pclken(pclken),
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.psel(psel0),
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.psel(psel0),
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.penable(penable),
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.penable(penable),
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.paddr(paddr[10:0]),
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.paddr(paddr[10:0]),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.pwdata(pwdata),
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.pwdata(pwdata),
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.prdata(prdata0),
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.prdata(prdata0),
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.pslverr(pslverr0),
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.pslverr(pslverr0),
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.rd_port_num(rd_port_num0),
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.rd_port_num(rd_port_num0),
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.wr_port_num(wr_port_num0),
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.wr_port_num(wr_port_num0),
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.joint_mode(joint_mode0),
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.joint_mode(joint_mode0),
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.joint_remote(joint_remote0),
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.joint_remote(joint_remote0),
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.rd_prio_top(rd_prio_top0),
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.rd_prio_top(rd_prio_top0),
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.rd_prio_high(rd_prio_high0),
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.rd_prio_high(rd_prio_high0),
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.rd_prio_top_num(rd_prio_top_num0),
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.rd_prio_top_num(rd_prio_top_num0),
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.rd_prio_high_num(rd_prio_high_num0),
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.rd_prio_high_num(rd_prio_high_num0),
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.wr_prio_top(wr_prio_top0),
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.wr_prio_top(wr_prio_top0),
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.wr_prio_high(wr_prio_high0),
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.wr_prio_high(wr_prio_high0),
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.wr_prio_top_num(wr_prio_top_num0),
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.wr_prio_top_num(wr_prio_top_num0),
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.wr_prio_high_num(wr_prio_high_num0),
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.wr_prio_high_num(wr_prio_high_num0),
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.AWADDR(M0_AWADDR),
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.AWADDR(M0_AWADDR),
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.AWLEN(M0_AWLEN),
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.AWLEN(M0_AWLEN),
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.AWSIZE(M0_AWSIZE),
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.AWSIZE(M0_AWSIZE),
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.AWVALID(M0_AWVALID),
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.AWVALID(M0_AWVALID),
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.AWREADY(M0_AWREADY),
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.AWREADY(M0_AWREADY),
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.WDATA(M0_WDATA),
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.WDATA(M0_WDATA),
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.WSTRB(M0_WSTRB),
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.WSTRB(M0_WSTRB),
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.WLAST(M0_WLAST),
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.WLAST(M0_WLAST),
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.WVALID(M0_WVALID),
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.WVALID(M0_WVALID),
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.WREADY(M0_WREADY),
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.WREADY(M0_WREADY),
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.BRESP(M0_BRESP),
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.BRESP(M0_BRESP),
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.BVALID(M0_BVALID),
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.BVALID(M0_BVALID),
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.BREADY(M0_BREADY),
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.BREADY(M0_BREADY),
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.ARADDR(M0_ARADDR),
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.ARADDR(M0_ARADDR),
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.ARLEN(M0_ARLEN),
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.ARLEN(M0_ARLEN),
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.ARSIZE(M0_ARSIZE),
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.ARSIZE(M0_ARSIZE),
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.ARVALID(M0_ARVALID),
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.ARVALID(M0_ARVALID),
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.ARREADY(M0_ARREADY),
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.ARREADY(M0_ARREADY),
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.RDATA(M0_RDATA),
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.RDATA(M0_RDATA),
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.RRESP(M0_RRESP),
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.RRESP(M0_RRESP),
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.RLAST(M0_RLAST),
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.RLAST(M0_RLAST),
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.RVALID(M0_RVALID),
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.RVALID(M0_RVALID),
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.RREADY(M0_RREADY)
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.RREADY(M0_RREADY)
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);
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);
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prgen_delay #(1) delay_pslverr1 (.clk(clk), .reset(reset), .din(psel1), .dout(pslverr1)); //return error
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prgen_delay #(1) delay_pslverr1 (.clk(clk), .reset(reset), .din(psel1), .dout(pslverr1)); //return error
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assign prdata1 = {32{1'b0}};
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assign prdata1 = {32{1'b0}};
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assign periph_rx_clr1 = {31{1'b0}};
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assign periph_rx_clr1 = {31{1'b0}};
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assign periph_tx_clr1 = {31{1'b0}};
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assign periph_tx_clr1 = {31{1'b0}};
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assign rd_port_num1 = 1'b0;
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assign rd_port_num1 = 1'b0;
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assign wr_port_num1 = 1'b0;
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assign wr_port_num1 = 1'b0;
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endmodule
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endmodule
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